arch/arm/boot/dts/ste-dbx5x0.dtsi

   1 /*
   2  * Copyright 2012 Linaro Ltd
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/mfd/dbx500-prcmu.h>
  14 #include <dt-bindings/arm/ux500_pm_domains.h>
  15 #include "skeleton.dtsi"
  16
  17 / {
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21                 enable-method = "ste,dbx500-smp";
  22
  23                 cpu-map {
  24                         cluster0 {
  25                                 core0 {
  26                                         cpu = <&CPU0>;
  27                                 };
  28                                 core1 {
  29                                         cpu = <&CPU1>;
  30                                 };
  31                         };
  32                 };
  33                 CPU0: cpu@300 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a9";
  36                         reg = <0x300>;
  37                 };
  38                 CPU1: cpu@301 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a9";
  41                         reg = <0x301>;
  42                 };
  43         };
  44
  45         soc {
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48                 compatible = "stericsson,db8500";
  49                 interrupt-parent = <&intc>;
  50                 ranges;
  51
  52                 ptm@801ae000 {
  53                         compatible = "arm,coresight-etm3x", "arm,primecell";
  54                         reg = <0x801ae000 0x1000>;
  55
  56                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  57                         clock-names = "apb_pclk", "atclk";
  58                         cpu = <&CPU0>;
  59                         port {
  60                                 ptm0_out_port: endpoint {
  61                                         remote-endpoint = <&funnel_in_port0>;
  62                                 };
  63                         };
  64                 };
  65
  66                 ptm@801af000 {
  67                         compatible = "arm,coresight-etm3x", "arm,primecell";
  68                         reg = <0x801af000 0x1000>;
  69
  70                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  71                         clock-names = "apb_pclk", "atclk";
  72                         cpu = <&CPU1>;
  73                         port {
  74                                 ptm1_out_port: endpoint {
  75                                         remote-endpoint = <&funnel_in_port1>;
  76                                 };
  77                         };
  78                 };
  79
  80                 funnel@801a6000 {
  81                         compatible = "arm,coresight-funnel", "arm,primecell";
  82                         reg = <0x801a6000 0x1000>;
  83
  84                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  85                         clock-names = "apb_pclk", "atclk";
  86                         ports {
  87                                 #address-cells = <1>;
  88                                 #size-cells = <0>;
  89
  90                                 /* funnel output ports */
  91                                 port@0 {
  92                                         reg = <0>;
  93                                         funnel_out_port: endpoint {
  94                                                 remote-endpoint =
  95                                                         <&replicator_in_port0>;
  96                                         };
  97                                 };
  98
  99                                 /* funnel input ports */
 100                                 port@1 {
 101                                         reg = <0>;
 102                                         funnel_in_port0: endpoint {
 103                                                 slave-mode;
 104                                                 remote-endpoint = <&ptm0_out_port>;
 105                                         };
 106                                 };
 107
 108                                 port@2 {
 109                                         reg = <1>;
 110                                         funnel_in_port1: endpoint {
 111                                                 slave-mode;
 112                                                 remote-endpoint = <&ptm1_out_port>;
 113                                         };
 114                                 };
 115                         };
 116                 };
 117
 118                 replicator {
 119                         compatible = "arm,coresight-replicator";
 120                         clocks = <&prcmu_clk PRCMU_APEATCLK>;
 121                         clock-names = "atclk";
 122
 123                         ports {
 124                                 #address-cells = <1>;
 125                                 #size-cells = <0>;
 126
 127                                 /* replicator output ports */
 128                                 port@0 {
 129                                         reg = <0>;
 130                                         replicator_out_port0: endpoint {
 131                                                 remote-endpoint = <&tpiu_in_port>;
 132                                         };
 133                                 };
 134                                 port@1 {
 135                                         reg = <1>;
 136                                         replicator_out_port1: endpoint {
 137                                                 remote-endpoint = <&etb_in_port>;
 138                                         };
 139                                 };
 140
 141                                 /* replicator input port */
 142                                 port@2 {
 143                                         reg = <0>;
 144                                         replicator_in_port0: endpoint {
 145                                                 slave-mode;
 146                                                 remote-endpoint = <&funnel_out_port>;
 147                                         };
 148                                 };
 149                         };
 150                 };
 151
 152                 tpiu@80190000 {
 153                         compatible = "arm,coresight-tpiu", "arm,primecell";
 154                         reg = <0x80190000 0x1000>;
 155
 156                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
 157                         clock-names = "apb_pclk", "atclk";
 158                         port {
 159                                 tpiu_in_port: endpoint {
 160                                         slave-mode;
 161                                         remote-endpoint = <&replicator_out_port0>;
 162                                 };
 163                         };
 164                 };
 165
 166                 etb@801a4000 {
 167                         compatible = "arm,coresight-etb10", "arm,primecell";
 168                         reg = <0x801a4000 0x1000>;
 169
 170                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
 171                         clock-names = "apb_pclk", "atclk";
 172                         port {
 173                                 etb_in_port: endpoint {
 174                                         slave-mode;
 175                                         remote-endpoint = <&replicator_out_port1>;
 176                                 };
 177                         };
 178                 };
 179
 180                 intc: interrupt-controller@a0411000 {
 181                         compatible = "arm,cortex-a9-gic";
 182                         #interrupt-cells = <3>;
 183                         #address-cells = <1>;
 184                         interrupt-controller;
 185                         reg = <0xa0411000 0x1000>,
 186                               <0xa0410100 0x100>;
 187                 };
 188
 189                 scu@a04100000 {
 190                         compatible = "arm,cortex-a9-scu";
 191                         reg = <0xa0410000 0x100>;
 192                 };
 193
 194                 /*
 195                  * The backup RAM is used for retention during sleep
 196                  * and various things like spin tables
 197                  */
 198                 backupram@80150000 {
 199                         compatible = "ste,dbx500-backupram";
 200                         reg = <0x80150000 0x2000>;
 201                 };
 202
 203                 L2: l2-cache {
 204                         compatible = "arm,pl310-cache";
 205                         reg = <0xa0412000 0x1000>;
 206                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
 207                         cache-unified;
 208                         cache-level = <2>;
 209                 };
 210
 211                 pmu {
 212                         compatible = "arm,cortex-a9-pmu";
 213                         interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 214                 };
 215
 216                 pm_domains: pm_domains0 {
 217                         compatible = "stericsson,ux500-pm-domains";
 218                         #power-domain-cells = <1>;
 219                 };
 220
 221                 clocks {
 222                         compatible = "stericsson,u8500-clks";
 223
 224                         prcmu_clk: prcmu-clock {
 225                                 #clock-cells = <1>;
 226                         };
 227
 228                         prcc_pclk: prcc-periph-clock {
 229                                 #clock-cells = <2>;
 230                         };
 231
 232                         prcc_kclk: prcc-kernel-clock {
 233                                 #clock-cells = <2>;
 234                         };
 235
 236                         rtc_clk: rtc32k-clock {
 237                                 #clock-cells = <0>;
 238                         };
 239
 240                         smp_twd_clk: smp-twd-clock {
 241                                 #clock-cells = <0>;
 242                         };
 243                 };
 244
 245                 mtu@a03c6000 {
 246                         /* Nomadik System Timer */
 247                         compatible = "st,nomadik-mtu";
 248                         reg = <0xa03c6000 0x1000>;
 249                         interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
 250
 251                         clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
 252                         clock-names = "timclk", "apb_pclk";
 253                 };
 254
 255                 timer@a0410600 {
 256                         compatible = "arm,cortex-a9-twd-timer";
 257                         reg = <0xa0410600 0x20>;
 258                         interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
 259
 260                         clocks = <&smp_twd_clk>;
 261                 };
 262
 263                 watchdog@a0410620 {
 264                         compatible = "arm,cortex-a9-twd-wdt";
 265                         reg = <0xa0410620 0x20>;
 266                         interrupts = <1 14 0x304>;
 267                         clocks = <&smp_twd_clk>;
 268                 };
 269
 270                 rtc@80154000 {
 271                         compatible = "arm,rtc-pl031", "arm,primecell";
 272                         reg = <0x80154000 0x1000>;
 273                         interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 274
 275                         clocks = <&rtc_clk>;
 276                         clock-names = "apb_pclk";
 277                 };
 278
 279                 gpio0: gpio@8012e000 {
 280                         compatible = "stericsson,db8500-gpio",
 281                                 "st,nomadik-gpio";
 282                         reg =  <0x8012e000 0x80>;
 283                         interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
 284                         interrupt-controller;
 285                         #interrupt-cells = <2>;
 286                         st,supports-sleepmode;
 287                         gpio-controller;
 288                         #gpio-cells = <2>;
 289                         gpio-bank = <0>;
 290
 291                         clocks = <&prcc_pclk 1 9>;
 292                 };
 293
 294                 gpio1: gpio@8012e080 {
 295                         compatible = "stericsson,db8500-gpio",
 296                                 "st,nomadik-gpio";
 297                         reg =  <0x8012e080 0x80>;
 298                         interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
 299                         interrupt-controller;
 300                         #interrupt-cells = <2>;
 301                         st,supports-sleepmode;
 302                         gpio-controller;
 303                         #gpio-cells = <2>;
 304                         gpio-bank = <1>;
 305
 306                         clocks = <&prcc_pclk 1 9>;
 307                 };
 308
 309                 gpio2: gpio@8000e000 {
 310                         compatible = "stericsson,db8500-gpio",
 311                                 "st,nomadik-gpio";
 312                         reg =  <0x8000e000 0x80>;
 313                         interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>;
 314                         interrupt-controller;
 315                         #interrupt-cells = <2>;
 316                         st,supports-sleepmode;
 317                         gpio-controller;
 318                         #gpio-cells = <2>;
 319                         gpio-bank = <2>;
 320
 321                         clocks = <&prcc_pclk 3 8>;
 322                 };
 323
 324                 gpio3: gpio@8000e080 {
 325                         compatible = "stericsson,db8500-gpio",
 326                                 "st,nomadik-gpio";
 327                         reg =  <0x8000e080 0x80>;
 328                         interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>;
 329                         interrupt-controller;
 330                         #interrupt-cells = <2>;
 331                         st,supports-sleepmode;
 332                         gpio-controller;
 333                         #gpio-cells = <2>;
 334                         gpio-bank = <3>;
 335
 336                         clocks = <&prcc_pclk 3 8>;
 337                 };
 338
 339                 gpio4: gpio@8000e100 {
 340                         compatible = "stericsson,db8500-gpio",
 341                                 "st,nomadik-gpio";
 342                         reg =  <0x8000e100 0x80>;
 343                         interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
 344                         interrupt-controller;
 345                         #interrupt-cells = <2>;
 346                         st,supports-sleepmode;
 347                         gpio-controller;
 348                         #gpio-cells = <2>;
 349                         gpio-bank = <4>;
 350
 351                         clocks = <&prcc_pclk 3 8>;
 352                 };
 353
 354                 gpio5: gpio@8000e180 {
 355                         compatible = "stericsson,db8500-gpio",
 356                                 "st,nomadik-gpio";
 357                         reg =  <0x8000e180 0x80>;
 358                         interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 359                         interrupt-controller;
 360                         #interrupt-cells = <2>;
 361                         st,supports-sleepmode;
 362                         gpio-controller;
 363                         #gpio-cells = <2>;
 364                         gpio-bank = <5>;
 365
 366                         clocks = <&prcc_pclk 3 8>;
 367                 };
 368
 369                 gpio6: gpio@8011e000 {
 370                         compatible = "stericsson,db8500-gpio",
 371                                 "st,nomadik-gpio";
 372                         reg =  <0x8011e000 0x80>;
 373                         interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 374                         interrupt-controller;
 375                         #interrupt-cells = <2>;
 376                         st,supports-sleepmode;
 377                         gpio-controller;
 378                         #gpio-cells = <2>;
 379                         gpio-bank = <6>;
 380
 381                         clocks = <&prcc_pclk 2 11>;
 382                 };
 383
 384                 gpio7: gpio@8011e080 {
 385                         compatible = "stericsson,db8500-gpio",
 386                                 "st,nomadik-gpio";
 387                         reg =  <0x8011e080 0x80>;
 388                         interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
 389                         interrupt-controller;
 390                         #interrupt-cells = <2>;
 391                         st,supports-sleepmode;
 392                         gpio-controller;
 393                         #gpio-cells = <2>;
 394                         gpio-bank = <7>;
 395
 396                         clocks = <&prcc_pclk 2 11>;
 397                 };
 398
 399                 gpio8: gpio@a03fe000 {
 400                         compatible = "stericsson,db8500-gpio",
 401                                 "st,nomadik-gpio";
 402                         reg =  <0xa03fe000 0x80>;
 403                         interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>;
 404                         interrupt-controller;
 405                         #interrupt-cells = <2>;
 406                         st,supports-sleepmode;
 407                         gpio-controller;
 408                         #gpio-cells = <2>;
 409                         gpio-bank = <8>;
 410
 411                         clocks = <&prcc_pclk 5 1>;
 412                 };
 413
 414                 pinctrl {
 415                         compatible = "stericsson,db8500-pinctrl";
 416                         prcm = <&prcmu>;
 417                 };
 418
 419                 usb_per5@a03e0000 {
 420                         compatible = "stericsson,db8500-musb";
 421                         reg = <0xa03e0000 0x10000>;
 422                         interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 423                         interrupt-names = "mc";
 424
 425                         dr_mode = "otg";
 426
 427                         dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
 428                                <&dma 38 0 0x0>, /* Logical - MemToDev */
 429                                <&dma 37 0 0x2>, /* Logical - DevToMem */
 430                                <&dma 37 0 0x0>, /* Logical - MemToDev */
 431                                <&dma 36 0 0x2>, /* Logical - DevToMem */
 432                                <&dma 36 0 0x0>, /* Logical - MemToDev */
 433                                <&dma 19 0 0x2>, /* Logical - DevToMem */
 434                                <&dma 19 0 0x0>, /* Logical - MemToDev */
 435                                <&dma 18 0 0x2>, /* Logical - DevToMem */
 436                                <&dma 18 0 0x0>, /* Logical - MemToDev */
 437                                <&dma 17 0 0x2>, /* Logical - DevToMem */
 438                                <&dma 17 0 0x0>, /* Logical - MemToDev */
 439                                <&dma 16 0 0x2>, /* Logical - DevToMem */
 440                                <&dma 16 0 0x0>, /* Logical - MemToDev */
 441                                <&dma 39 0 0x2>, /* Logical - DevToMem */
 442                                <&dma 39 0 0x0>; /* Logical - MemToDev */
 443
 444                         dma-names = "iep_1_9",  "oep_1_9",
 445                                     "iep_2_10", "oep_2_10",
 446                                     "iep_3_11", "oep_3_11",
 447                                     "iep_4_12", "oep_4_12",
 448                                     "iep_5_13", "oep_5_13",
 449                                     "iep_6_14", "oep_6_14",
 450                                     "iep_7_15", "oep_7_15",
 451                                     "iep_8",    "oep_8";
 452
 453                         clocks = <&prcc_pclk 5 0>;
 454                 };
 455
 456                 dma: dma-controller@801C0000 {
 457                         compatible = "stericsson,db8500-dma40", "stericsson,dma40";
 458                         reg = <0x801C0000 0x1000 0x40010000 0x800>;
 459                         reg-names = "base", "lcpa";
 460                         interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 461
 462                         #dma-cells = <3>;
 463                         memcpy-channels = <56 57 58 59 60>;
 464
 465                         clocks = <&prcmu_clk PRCMU_DMACLK>;
 466                 };
 467
 468                 prcmu: prcmu@80157000 {
 469                         compatible = "stericsson,db8500-prcmu";
 470                         reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
 471                         reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
 472                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 473                         #address-cells = <1>;
 474                         #size-cells = <1>;
 475                         interrupt-controller;
 476                         #interrupt-cells = <2>;
 477                         ranges;
 478
 479                         prcmu-timer-4@80157450 {
 480                                 compatible = "stericsson,db8500-prcmu-timer-4";
 481                                 reg = <0x80157450 0xC>;
 482                         };
 483
 484                         cpufreq {
 485                                 compatible = "stericsson,cpufreq-ux500";
 486                                 clocks = <&prcmu_clk PRCMU_ARMSS>;
 487                                 clock-names = "armss";
 488                                 status = "disabled";
 489                         };
 490
 491                         thermal@801573c0 {
 492                                 compatible = "stericsson,db8500-thermal";
 493                                 reg = <0x801573c0 0x40>;
 494                                 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
 495                                              <22 IRQ_TYPE_LEVEL_HIGH>;
 496                                 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
 497                                 status = "disabled";
 498                         };
 499
 500                         db8500-prcmu-regulators {
 501                                 compatible = "stericsson,db8500-prcmu-regulator";
 502
 503                                 // DB8500_REGULATOR_VAPE
 504                                 db8500_vape_reg: db8500_vape {
 505                                         regulator-compatible = "db8500_vape";
 506                                         regulator-always-on;
 507                                 };
 508
 509                                 // DB8500_REGULATOR_VARM
 510                                 db8500_varm_reg: db8500_varm {
 511                                         regulator-compatible = "db8500_varm";
 512                                 };
 513
 514                                 // DB8500_REGULATOR_VMODEM
 515                                 db8500_vmodem_reg: db8500_vmodem {
 516                                         regulator-compatible = "db8500_vmodem";
 517                                 };
 518
 519                                 // DB8500_REGULATOR_VPLL
 520                                 db8500_vpll_reg: db8500_vpll {
 521                                         regulator-compatible = "db8500_vpll";
 522                                 };
 523
 524                                 // DB8500_REGULATOR_VSMPS1
 525                                 db8500_vsmps1_reg: db8500_vsmps1 {
 526                                         regulator-compatible = "db8500_vsmps1";
 527                                 };
 528
 529                                 // DB8500_REGULATOR_VSMPS2
 530                                 db8500_vsmps2_reg: db8500_vsmps2 {
 531                                         regulator-compatible = "db8500_vsmps2";
 532                                 };
 533
 534                                 // DB8500_REGULATOR_VSMPS3
 535                                 db8500_vsmps3_reg: db8500_vsmps3 {
 536                                         regulator-compatible = "db8500_vsmps3";
 537                                 };
 538
 539                                 // DB8500_REGULATOR_VRF1
 540                                 db8500_vrf1_reg: db8500_vrf1 {
 541                                         regulator-compatible = "db8500_vrf1";
 542                                 };
 543
 544                                 // DB8500_REGULATOR_SWITCH_SVAMMDSP
 545                                 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
 546                                         regulator-compatible = "db8500_sva_mmdsp";
 547                                 };
 548
 549                                 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
 550                                 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
 551                                         regulator-compatible = "db8500_sva_mmdsp_ret";
 552                                 };
 553
 554                                 // DB8500_REGULATOR_SWITCH_SVAPIPE
 555                                 db8500_sva_pipe_reg: db8500_sva_pipe {
 556                                         regulator-compatible = "db8500_sva_pipe";
 557                                 };
 558
 559                                 // DB8500_REGULATOR_SWITCH_SIAMMDSP
 560                                 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
 561                                         regulator-compatible = "db8500_sia_mmdsp";
 562                                 };
 563
 564                                 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
 565                                 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
 566                                 };
 567
 568                                 // DB8500_REGULATOR_SWITCH_SIAPIPE
 569                                 db8500_sia_pipe_reg: db8500_sia_pipe {
 570                                         regulator-compatible = "db8500_sia_pipe";
 571                                 };
 572
 573                                 // DB8500_REGULATOR_SWITCH_SGA
 574                                 db8500_sga_reg: db8500_sga {
 575                                         regulator-compatible = "db8500_sga";
 576                                         vin-supply = <&db8500_vape_reg>;
 577                                 };
 578
 579                                 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
 580                                 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
 581                                         regulator-compatible = "db8500_b2r2_mcde";
 582                                         vin-supply = <&db8500_vape_reg>;
 583                                 };
 584
 585                                 // DB8500_REGULATOR_SWITCH_ESRAM12
 586                                 db8500_esram12_reg: db8500_esram12 {
 587                                         regulator-compatible = "db8500_esram12";
 588                                 };
 589
 590                                 // DB8500_REGULATOR_SWITCH_ESRAM12RET
 591                                 db8500_esram12_ret_reg: db8500_esram12_ret {
 592                                         regulator-compatible = "db8500_esram12_ret";
 593                                 };
 594
 595                                 // DB8500_REGULATOR_SWITCH_ESRAM34
 596                                 db8500_esram34_reg: db8500_esram34 {
 597                                         regulator-compatible = "db8500_esram34";
 598                                 };
 599
 600                                 // DB8500_REGULATOR_SWITCH_ESRAM34RET
 601                                 db8500_esram34_ret_reg: db8500_esram34_ret {
 602                                         regulator-compatible = "db8500_esram34_ret";
 603                                 };
 604                         };
 605
 606                         ab8500 {
 607                                 compatible = "stericsson,ab8500";
 608                                 interrupt-parent = <&intc>;
 609                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 610                                 interrupt-controller;
 611                                 #interrupt-cells = <2>;
 612
 613                                 ab8500_gpio: ab8500-gpio {
 614                                         gpio-controller;
 615                                         #gpio-cells = <2>;
 616                                 };
 617
 618                                 ab8500-rtc {
 619                                         compatible = "stericsson,ab8500-rtc";
 620                                         interrupts = <17 IRQ_TYPE_LEVEL_HIGH
 621                                                       18 IRQ_TYPE_LEVEL_HIGH>;
 622                                         interrupt-names = "60S", "ALARM";
 623                                 };
 624
 625                                 ab8500-gpadc {
 626                                         compatible = "stericsson,ab8500-gpadc";
 627                                         interrupts = <32 IRQ_TYPE_LEVEL_HIGH
 628                                                       39 IRQ_TYPE_LEVEL_HIGH>;
 629                                         interrupt-names = "HW_CONV_END", "SW_CONV_END";
 630                                         vddadc-supply = <&ab8500_ldo_tvout_reg>;
 631                                 };
 632
 633                                 ab8500_battery: ab8500_battery {
 634                                         stericsson,battery-type = "LIPO";
 635                                         thermistor-on-batctrl;
 636                                 };
 637
 638                                 ab8500_fg {
 639                                         compatible = "stericsson,ab8500-fg";
 640                                         battery    = <&ab8500_battery>;
 641                                 };
 642
 643                                 ab8500_btemp {
 644                                         compatible = "stericsson,ab8500-btemp";
 645                                         battery    = <&ab8500_battery>;
 646                                 };
 647
 648                                 ab8500_charger {
 649                                         compatible      = "stericsson,ab8500-charger";
 650                                         battery         = <&ab8500_battery>;
 651                                         vddadc-supply   = <&ab8500_ldo_tvout_reg>;
 652                                 };
 653
 654                                 ab8500_chargalg {
 655                                         compatible      = "stericsson,ab8500-chargalg";
 656                                         battery         = <&ab8500_battery>;
 657                                 };
 658
 659                                 ab8500_usb {
 660                                         compatible = "stericsson,ab8500-usb";
 661                                         interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
 662                                                        96 IRQ_TYPE_LEVEL_HIGH
 663                                                        14 IRQ_TYPE_LEVEL_HIGH
 664                                                        15 IRQ_TYPE_LEVEL_HIGH
 665                                                        79 IRQ_TYPE_LEVEL_HIGH
 666                                                        74 IRQ_TYPE_LEVEL_HIGH
 667                                                        75 IRQ_TYPE_LEVEL_HIGH>;
 668                                         interrupt-names = "ID_WAKEUP_R",
 669                                                           "ID_WAKEUP_F",
 670                                                           "VBUS_DET_F",
 671                                                           "VBUS_DET_R",
 672                                                           "USB_LINK_STATUS",
 673                                                           "USB_ADP_PROBE_PLUG",
 674                                                           "USB_ADP_PROBE_UNPLUG";
 675                                         vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
 676                                         v-ape-supply = <&db8500_vape_reg>;
 677                                         musb_1v8-supply = <&db8500_vsmps2_reg>;
 678                                 };
 679
 680                                 ab8500-ponkey {
 681                                         compatible = "stericsson,ab8500-poweron-key";
 682                                         interrupts = <6 IRQ_TYPE_LEVEL_HIGH
 683                                                       7 IRQ_TYPE_LEVEL_HIGH>;
 684                                         interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
 685                                 };
 686
 687                                 ab8500-sysctrl {
 688                                         compatible = "stericsson,ab8500-sysctrl";
 689                                 };
 690
 691                                 ab8500-pwm {
 692                                         compatible = "stericsson,ab8500-pwm";
 693                                 };
 694
 695                                 ab8500-debugfs {
 696                                         compatible = "stericsson,ab8500-debug";
 697                                 };
 698
 699                                 codec: ab8500-codec {
 700                                         compatible = "stericsson,ab8500-codec";
 701
 702                                         V-AUD-supply = <&ab8500_ldo_audio_reg>;
 703                                         V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
 704                                         V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
 705                                         V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
 706
 707                                         stericsson,earpeice-cmv = <950>; /* Units in mV. */
 708                                 };
 709
 710                                 ext_regulators: ab8500-ext-regulators {
 711                                         compatible = "stericsson,ab8500-ext-regulator";
 712
 713                                         ab8500_ext1_reg: ab8500_ext1 {
 714                                                 regulator-compatible = "ab8500_ext1";
 715                                                 regulator-min-microvolt = <1800000>;
 716                                                 regulator-max-microvolt = <1800000>;
 717                                                 regulator-boot-on;
 718                                                 regulator-always-on;
 719                                         };
 720
 721                                         ab8500_ext2_reg: ab8500_ext2 {
 722                                                 regulator-compatible = "ab8500_ext2";
 723                                                 regulator-min-microvolt = <1360000>;
 724                                                 regulator-max-microvolt = <1360000>;
 725                                                 regulator-boot-on;
 726                                                 regulator-always-on;
 727                                         };
 728
 729                                         ab8500_ext3_reg: ab8500_ext3 {
 730                                                 regulator-compatible = "ab8500_ext3";
 731                                                 regulator-min-microvolt = <3400000>;
 732                                                 regulator-max-microvolt = <3400000>;
 733                                                 regulator-boot-on;
 734                                         };
 735                                 };
 736
 737                                 ab8500-regulators {
 738                                         compatible = "stericsson,ab8500-regulator";
 739                                         vin-supply = <&ab8500_ext3_reg>;
 740
 741                                         // supplies to the display/camera
 742                                         ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
 743                                                 regulator-compatible = "ab8500_ldo_aux1";
 744                                                 regulator-min-microvolt = <2500000>;
 745                                                 regulator-max-microvolt = <2900000>;
 746                                                 regulator-boot-on;
 747                                                 /* BUG: If turned off MMC will be affected. */
 748                                                 regulator-always-on;
 749                                         };
 750
 751                                         // supplies to the on-board eMMC
 752                                         ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
 753                                                 regulator-compatible = "ab8500_ldo_aux2";
 754                                                 regulator-min-microvolt = <1100000>;
 755                                                 regulator-max-microvolt = <3300000>;
 756                                         };
 757
 758                                         // supply for VAUX3; SDcard slots
 759                                         ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
 760                                                 regulator-compatible = "ab8500_ldo_aux3";
 761                                                 regulator-min-microvolt = <1100000>;
 762                                                 regulator-max-microvolt = <3300000>;
 763                                         };
 764
 765                                         // supply for v-intcore12; VINTCORE12 LDO
 766                                         ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
 767                                                 regulator-compatible = "ab8500_ldo_intcore";
 768                                         };
 769
 770                                         // supply for tvout; gpadc; TVOUT LDO
 771                                         ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
 772                                                 regulator-compatible = "ab8500_ldo_tvout";
 773                                         };
 774
 775                                         // supply for ab8500-usb; USB LDO
 776                                         ab8500_ldo_usb_reg: ab8500_ldo_usb {
 777                                                 regulator-compatible = "ab8500_ldo_usb";
 778                                         };
 779
 780                                         // supply for ab8500-vaudio; VAUDIO LDO
 781                                         ab8500_ldo_audio_reg: ab8500_ldo_audio {
 782                                                 regulator-compatible = "ab8500_ldo_audio";
 783                                         };
 784
 785                                         // supply for v-anamic1 VAMIC1 LDO
 786                                         ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
 787                                                 regulator-compatible = "ab8500_ldo_anamic1";
 788                                         };
 789
 790                                         // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
 791                                         ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
 792                                                 regulator-compatible = "ab8500_ldo_anamic2";
 793                                         };
 794
 795                                         // supply for v-dmic; VDMIC LDO
 796                                         ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
 797                                                 regulator-compatible = "ab8500_ldo_dmic";
 798                                         };
 799
 800                                         // supply for U8500 CSI/DSI; VANA LDO
 801                                         ab8500_ldo_ana_reg: ab8500_ldo_ana {
 802                                                 regulator-compatible = "ab8500_ldo_ana";
 803                                         };
 804                                 };
 805                         };
 806                 };
 807
 808                 i2c@80004000 {
 809                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 810                         reg = <0x80004000 0x1000>;
 811                         interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 812
 813                         #address-cells = <1>;
 814                         #size-cells = <0>;
 815                         v-i2c-supply = <&db8500_vape_reg>;
 816
 817                         clock-frequency = <400000>;
 818                         clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
 819                         clock-names = "i2cclk", "apb_pclk";
 820                         power-domains = <&pm_domains DOMAIN_VAPE>;
 821                 };
 822
 823                 i2c@80122000 {
 824                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 825                         reg = <0x80122000 0x1000>;
 826                         interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 827
 828                         #address-cells = <1>;
 829                         #size-cells = <0>;
 830                         v-i2c-supply = <&db8500_vape_reg>;
 831
 832                         clock-frequency = <400000>;
 833
 834                         clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
 835                         clock-names = "i2cclk", "apb_pclk";
 836                         power-domains = <&pm_domains DOMAIN_VAPE>;
 837                 };
 838
 839                 i2c@80128000 {
 840                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 841                         reg = <0x80128000 0x1000>;
 842                         interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 843
 844                         #address-cells = <1>;
 845                         #size-cells = <0>;
 846                         v-i2c-supply = <&db8500_vape_reg>;
 847
 848                         clock-frequency = <400000>;
 849
 850                         clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
 851                         clock-names = "i2cclk", "apb_pclk";
 852                         power-domains = <&pm_domains DOMAIN_VAPE>;
 853                 };
 854
 855                 i2c@80110000 {
 856                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 857                         reg = <0x80110000 0x1000>;
 858                         interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
 859
 860                         #address-cells = <1>;
 861                         #size-cells = <0>;
 862                         v-i2c-supply = <&db8500_vape_reg>;
 863
 864                         clock-frequency = <400000>;
 865
 866                         clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
 867                         clock-names = "i2cclk", "apb_pclk";
 868                         power-domains = <&pm_domains DOMAIN_VAPE>;
 869                 };
 870
 871                 i2c@8012a000 {
 872                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 873                         reg = <0x8012a000 0x1000>;
 874                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 875
 876                         #address-cells = <1>;
 877                         #size-cells = <0>;
 878                         v-i2c-supply = <&db8500_vape_reg>;
 879
 880                         clock-frequency = <400000>;
 881
 882                         clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
 883                         clock-names = "i2cclk", "apb_pclk";
 884                         power-domains = <&pm_domains DOMAIN_VAPE>;
 885                 };
 886
 887                 ssp@80002000 {
 888                         compatible = "arm,pl022", "arm,primecell";
 889                         reg = <0x80002000 0x1000>;
 890                         interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 891                         #address-cells = <1>;
 892                         #size-cells = <0>;
 893                         clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
 894                         clock-names = "SSPCLK", "apb_pclk";
 895                         dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
 896                                <&dma 8 0 0x0>; /* Logical - MemToDev */
 897                         dma-names = "rx", "tx";
 898                         power-domains = <&pm_domains DOMAIN_VAPE>;
 899                 };
 900
 901                 ssp@80003000 {
 902                         compatible = "arm,pl022", "arm,primecell";
 903                         reg = <0x80003000 0x1000>;
 904                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 905                         #address-cells = <1>;
 906                         #size-cells = <0>;
 907                         clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
 908                         clock-names = "SSPCLK", "apb_pclk";
 909                         dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
 910                                <&dma 9 0 0x0>; /* Logical - MemToDev */
 911                         dma-names = "rx", "tx";
 912                         power-domains = <&pm_domains DOMAIN_VAPE>;
 913                 };
 914
 915                 spi@8011a000 {
 916                         compatible = "arm,pl022", "arm,primecell";
 917                         reg = <0x8011a000 0x1000>;
 918                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 919                         #address-cells = <1>;
 920                         #size-cells = <0>;
 921                         /* Same clock wired to kernel and pclk */
 922                         clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
 923                         clock-names = "SSPCLK", "apb_pclk";
 924                         dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
 925                                <&dma 0 0 0x0>; /* Logical - MemToDev */
 926                         dma-names = "rx", "tx";
 927                         power-domains = <&pm_domains DOMAIN_VAPE>;
 928                 };
 929
 930                 spi@80112000 {
 931                         compatible = "arm,pl022", "arm,primecell";
 932                         reg = <0x80112000 0x1000>;
 933                         interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
 934                         #address-cells = <1>;
 935                         #size-cells = <0>;
 936                         /* Same clock wired to kernel and pclk */
 937                         clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
 938                         clock-names = "SSPCLK", "apb_pclk";
 939                         dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
 940                                <&dma 35 0 0x0>; /* Logical - MemToDev */
 941                         dma-names = "rx", "tx";
 942                         power-domains = <&pm_domains DOMAIN_VAPE>;
 943                 };
 944
 945                 spi@80111000 {
 946                         compatible = "arm,pl022", "arm,primecell";
 947                         reg = <0x80111000 0x1000>;
 948                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 949                         #address-cells = <1>;
 950                         #size-cells = <0>;
 951                         /* Same clock wired to kernel and pclk */
 952                         clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
 953                         clock-names = "SSPCLK", "apb_pclk";
 954                         dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
 955                                <&dma 33 0 0x0>; /* Logical - MemToDev */
 956                         dma-names = "rx", "tx";
 957                         power-domains = <&pm_domains DOMAIN_VAPE>;
 958                 };
 959
 960                 spi@80129000 {
 961                         compatible = "arm,pl022", "arm,primecell";
 962                         reg = <0x80129000 0x1000>;
 963                         interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 964                         #address-cells = <1>;
 965                         #size-cells = <0>;
 966                         /* Same clock wired to kernel and pclk */
 967                         clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
 968                         clock-names = "SSPCLK", "apb_pclk";
 969                         dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
 970                                <&dma 40 0 0x0>; /* Logical - MemToDev */
 971                         dma-names = "rx", "tx";
 972                         power-domains = <&pm_domains DOMAIN_VAPE>;
 973                 };
 974
 975                 ux500_serial0: uart@80120000 {
 976                         compatible = "arm,pl011", "arm,primecell";
 977                         reg = <0x80120000 0x1000>;
 978                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 979
 980                         dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
 981                                <&dma 13 0 0x0>; /* Logical - MemToDev */
 982                         dma-names = "rx", "tx";
 983
 984                         clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
 985                         clock-names = "uart", "apb_pclk";
 986
 987                         status = "disabled";
 988                 };
 989
 990                 ux500_serial1: uart@80121000 {
 991                         compatible = "arm,pl011", "arm,primecell";
 992                         reg = <0x80121000 0x1000>;
 993                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
 994
 995                         dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
 996                                <&dma 12 0 0x0>; /* Logical - MemToDev */
 997                         dma-names = "rx", "tx";
 998
 999                         clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
1000                         clock-names = "uart", "apb_pclk";
1001
1002                         status = "disabled";
1003                 };
1004
1005                 ux500_serial2: uart@80007000 {
1006                         compatible = "arm,pl011", "arm,primecell";
1007                         reg = <0x80007000 0x1000>;
1008                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
1009
1010                         dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
1011                                <&dma 11 0 0x0>; /* Logical - MemToDev */
1012                         dma-names = "rx", "tx";
1013
1014                         clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
1015                         clock-names = "uart", "apb_pclk";
1016
1017                         status = "disabled";
1018                 };
1019
1020                 sdi0_per1@80126000 {
1021                         compatible = "arm,pl18x", "arm,primecell";
1022                         reg = <0x80126000 0x1000>;
1023                         interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
1024
1025                         dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
1026                                <&dma 29 0 0x0>; /* Logical - MemToDev */
1027                         dma-names = "rx", "tx";
1028
1029                         clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
1030                         clock-names = "sdi", "apb_pclk";
1031                         power-domains = <&pm_domains DOMAIN_VAPE>;
1032
1033                         status = "disabled";
1034                 };
1035
1036                 sdi1_per2@80118000 {
1037                         compatible = "arm,pl18x", "arm,primecell";
1038                         reg = <0x80118000 0x1000>;
1039                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
1040
1041                         dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
1042                                <&dma 32 0 0x0>; /* Logical - MemToDev */
1043                         dma-names = "rx", "tx";
1044
1045                         clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
1046                         clock-names = "sdi", "apb_pclk";
1047                         power-domains = <&pm_domains DOMAIN_VAPE>;
1048
1049                         status = "disabled";
1050                 };
1051
1052                 sdi2_per3@80005000 {
1053                         compatible = "arm,pl18x", "arm,primecell";
1054                         reg = <0x80005000 0x1000>;
1055                         interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
1056
1057                         dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
1058                                <&dma 28 0 0x0>; /* Logical - MemToDev */
1059                         dma-names = "rx", "tx";
1060
1061                         clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
1062                         clock-names = "sdi", "apb_pclk";
1063                         power-domains = <&pm_domains DOMAIN_VAPE>;
1064
1065                         status = "disabled";
1066                 };
1067
1068                 sdi3_per2@80119000 {
1069                         compatible = "arm,pl18x", "arm,primecell";
1070                         reg = <0x80119000 0x1000>;
1071                         interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
1072
1073                         dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
1074                                <&dma 41 0 0x0>; /* Logical - MemToDev */
1075                         dma-names = "rx", "tx";
1076
1077                         clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
1078                         clock-names = "sdi", "apb_pclk";
1079                         power-domains = <&pm_domains DOMAIN_VAPE>;
1080
1081                         status = "disabled";
1082                 };
1083
1084                 sdi4_per2@80114000 {
1085                         compatible = "arm,pl18x", "arm,primecell";
1086                         reg = <0x80114000 0x1000>;
1087                         interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
1088
1089                         dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
1090                                <&dma 42 0 0x0>; /* Logical - MemToDev */
1091                         dma-names = "rx", "tx";
1092
1093                         clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
1094                         clock-names = "sdi", "apb_pclk";
1095                         power-domains = <&pm_domains DOMAIN_VAPE>;
1096
1097                         status = "disabled";
1098                 };
1099
1100                 sdi5_per3@80008000 {
1101                         compatible = "arm,pl18x", "arm,primecell";
1102                         reg = <0x80008000 0x1000>;
1103                         interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
1104
1105                         dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
1106                                <&dma 43 0 0x0>; /* Logical - MemToDev */
1107                         dma-names = "rx", "tx";
1108
1109                         clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
1110                         clock-names = "sdi", "apb_pclk";
1111                         power-domains = <&pm_domains DOMAIN_VAPE>;
1112
1113                         status = "disabled";
1114                 };
1115
1116                 msp0: msp@80123000 {
1117                         compatible = "stericsson,ux500-msp-i2s";
1118                         reg = <0x80123000 0x1000>;
1119                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
1120                         v-ape-supply = <&db8500_vape_reg>;
1121
1122                         dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
1123                                <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
1124                         dma-names = "rx", "tx";
1125
1126                         clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
1127                         clock-names = "msp", "apb_pclk";
1128
1129                         status = "disabled";
1130                 };
1131
1132                 msp1: msp@80124000 {
1133                         compatible = "stericsson,ux500-msp-i2s";
1134                         reg = <0x80124000 0x1000>;
1135                         interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
1136                         v-ape-supply = <&db8500_vape_reg>;
1137
1138                         /* This DMA channel only exist on DB8500 v1 */
1139                         dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
1140                         dma-names = "tx";
1141
1142                         clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
1143                         clock-names = "msp", "apb_pclk";
1144
1145                         status = "disabled";
1146                 };
1147
1148                 // HDMI sound
1149                 msp2: msp@80117000 {
1150                         compatible = "stericsson,ux500-msp-i2s";
1151                         reg = <0x80117000 0x1000>;
1152                         interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
1153                         v-ape-supply = <&db8500_vape_reg>;
1154
1155                         dmas = <&dma 14 0 0x12>, /* Logical  - DevToMem - HighPrio */
1156                                <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
1157                                                     HighPrio - Fixed */
1158                         dma-names = "rx", "tx";
1159
1160                         clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
1161                         clock-names = "msp", "apb_pclk";
1162
1163                         status = "disabled";
1164                 };
1165
1166                 msp3: msp@80125000 {
1167                         compatible = "stericsson,ux500-msp-i2s";
1168                         reg = <0x80125000 0x1000>;
1169                         interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
1170                         v-ape-supply = <&db8500_vape_reg>;
1171
1172                         /* This DMA channel only exist on DB8500 v2 */
1173                         dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
1174                         dma-names = "rx";
1175
1176                         clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
1177                         clock-names = "msp", "apb_pclk";
1178
1179                         status = "disabled";
1180                 };
1181
1182                 external-bus@50000000 {
1183                         compatible = "simple-bus";
1184                         reg = <0x50000000 0x4000000>;
1185                         #address-cells = <1>;
1186                         #size-cells = <1>;
1187                         ranges = <0 0x50000000 0x4000000>;
1188                         status = "disabled";
1189                 };
1190
1191                 cpufreq-cooling {
1192                         compatible = "stericsson,db8500-cpufreq-cooling";
1193                         status = "disabled";
1194                 };
1195
1196                 mcde@a0350000 {
1197                         compatible = "stericsson,mcde";
1198                         reg = <0xa0350000 0x1000>, /* MCDE */
1199                               <0xa0351000 0x1000>, /* DSI link 1 */
1200                               <0xa0352000 0x1000>, /* DSI link 2 */
1201                               <0xa0353000 0x1000>; /* DSI link 3 */
1202                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
1203                         clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1204                                  <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1205                                  <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */
1206                                  <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */
1207                                  <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */
1208                                  <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */
1209                                  <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */
1210                                  <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */
1211                 };
1212
1213                 cryp@a03cb000 {
1214                         compatible = "stericsson,ux500-cryp";
1215                         reg = <0xa03cb000 0x1000>;
1216                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
1217
1218                         v-ape-supply = <&db8500_vape_reg>;
1219                         clocks = <&prcc_pclk 6 1>;
1220                 };
1221
1222                 hash@a03c2000 {
1223                         compatible = "stericsson,ux500-hash";
1224                         reg = <0xa03c2000 0x1000>;
1225
1226                         v-ape-supply = <&db8500_vape_reg>;
1227                         clocks = <&prcc_pclk 6 2>;
1228                 };
1229         };
1230 };