arch/arm/boot/dts/stih407-pinctrl.dtsi

   1 /*
   2  * Copyright (C) 2014 STMicroelectronics Limited.
   3  * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * publishhed by the Free Software Foundation.
   8  */
   9 #include "st-pincfg.h"
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 / {
  12
  13         aliases {
  14                 /* 0-5: PIO_SBC */
  15                 gpio0 = &pio0;
  16                 gpio1 = &pio1;
  17                 gpio2 = &pio2;
  18                 gpio3 = &pio3;
  19                 gpio4 = &pio4;
  20                 gpio5 = &pio5;
  21                 /* 10-19: PIO_FRONT0 */
  22                 gpio6 = &pio10;
  23                 gpio7 = &pio11;
  24                 gpio8 = &pio12;
  25                 gpio9 = &pio13;
  26                 gpio10 = &pio14;
  27                 gpio11 = &pio15;
  28                 gpio12 = &pio16;
  29                 gpio13 = &pio17;
  30                 gpio14 = &pio18;
  31                 gpio15 = &pio19;
  32                 /* 20: PIO_FRONT1 */
  33                 gpio16 = &pio20;
  34                 /* 30-35: PIO_REAR */
  35                 gpio17 = &pio30;
  36                 gpio18 = &pio31;
  37                 gpio19 = &pio32;
  38                 gpio20 = &pio33;
  39                 gpio21 = &pio34;
  40                 gpio22 = &pio35;
  41                 /* 40-42: PIO_FLASH */
  42                 gpio23 = &pio40;
  43                 gpio24 = &pio41;
  44                 gpio25 = &pio42;
  45         };
  46
  47         soc {
  48                 pin-controller-sbc {
  49                         #address-cells = <1>;
  50                         #size-cells = <1>;
  51                         compatible = "st,stih407-sbc-pinctrl";
  52                         st,syscfg = <&syscfg_sbc>;
  53                         reg = <0x0961f080 0x4>;
  54                         reg-names = "irqmux";
  55                         interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
  56                         interrupt-names = "irqmux";
  57                         ranges = <0 0x09610000 0x6000>;
  58
  59                         pio0: gpio@09610000 {
  60                                 gpio-controller;
  61                                 #gpio-cells = <2>;
  62                                 interrupt-controller;
  63                                 #interrupt-cells = <2>;
  64                                 reg = <0x0 0x100>;
  65                                 st,bank-name = "PIO0";
  66                         };
  67                         pio1: gpio@09611000 {
  68                                 gpio-controller;
  69                                 #gpio-cells = <2>;
  70                                 interrupt-controller;
  71                                 #interrupt-cells = <2>;
  72                                 reg = <0x1000 0x100>;
  73                                 st,bank-name = "PIO1";
  74                         };
  75                         pio2: gpio@09612000 {
  76                                 gpio-controller;
  77                                 #gpio-cells = <2>;
  78                                 interrupt-controller;
  79                                 #interrupt-cells = <2>;
  80                                 reg = <0x2000 0x100>;
  81                                 st,bank-name = "PIO2";
  82                         };
  83                         pio3: gpio@09613000 {
  84                                 gpio-controller;
  85                                 #gpio-cells = <2>;
  86                                 interrupt-controller;
  87                                 #interrupt-cells = <2>;
  88                                 reg = <0x3000 0x100>;
  89                                 st,bank-name = "PIO3";
  90                         };
  91                         pio4: gpio@09614000 {
  92                                 gpio-controller;
  93                                 #gpio-cells = <2>;
  94                                 interrupt-controller;
  95                                 #interrupt-cells = <2>;
  96                                 reg = <0x4000 0x100>;
  97                                 st,bank-name = "PIO4";
  98                         };
  99
 100                         pio5: gpio@09615000 {
 101                                 gpio-controller;
 102                                 #gpio-cells = <2>;
 103                                 interrupt-controller;
 104                                 #interrupt-cells = <2>;
 105                                 reg = <0x5000 0x100>;
 106                                 st,bank-name = "PIO5";
 107                                 st,retime-pin-mask = <0x3f>;
 108                         };
 109
 110                         cec0 {
 111                                 pinctrl_cec0_default: cec0-default {
 112                                         st,pins {
 113                                                 hdmi_cec = <&pio2 4 ALT1 BIDIR>;
 114                                         };
 115                                 };
 116                         };
 117
 118                         rc {
 119                                 pinctrl_ir: ir0 {
 120                                         st,pins {
 121                                                 ir = <&pio4 0 ALT2 IN>;
 122                                         };
 123                                 };
 124
 125                                 pinctrl_uhf: uhf0 {
 126                                         st,pins {
 127                                                 ir = <&pio4 1 ALT2 IN>;
 128                                         };
 129                                 };
 130
 131                                 pinctrl_tx: tx0 {
 132                                         st,pins {
 133                                                 tx = <&pio4 2 ALT2 OUT>;
 134                                         };
 135                                 };
 136
 137                                 pinctrl_tx_od: tx_od0 {
 138                                         st,pins {
 139                                                 tx_od = <&pio4 3 ALT2 OUT>;
 140                                         };
 141                                 };
 142                         };
 143
 144                         /* SBC_ASC0 - UART10 */
 145                         sbc_serial0 {
 146                                 pinctrl_sbc_serial0: sbc_serial0-0 {
 147                                         st,pins {
 148                                                 tx = <&pio3 4 ALT1 OUT>;
 149                                                 rx = <&pio3 5 ALT1 IN>;
 150                                         };
 151                                 };
 152                         };
 153                         /* SBC_ASC1 - UART11 */
 154                         sbc_serial1 {
 155                                 pinctrl_sbc_serial1: sbc_serial1-0 {
 156                                         st,pins {
 157                                                 tx = <&pio2 6 ALT3 OUT>;
 158                                                 rx = <&pio2 7 ALT3 IN>;
 159                                         };
 160                                 };
 161                         };
 162
 163                         i2c10 {
 164                                 pinctrl_i2c10_default: i2c10-default {
 165                                         st,pins {
 166                                                 sda = <&pio4 6 ALT1 BIDIR>;
 167                                                 scl = <&pio4 5 ALT1 BIDIR>;
 168                                         };
 169                                 };
 170                         };
 171
 172                         i2c11 {
 173                                 pinctrl_i2c11_default: i2c11-default {
 174                                         st,pins {
 175                                                 sda = <&pio5 1 ALT1 BIDIR>;
 176                                                 scl = <&pio5 0 ALT1 BIDIR>;
 177                                         };
 178                                 };
 179                         };
 180
 181                         keyscan {
 182                                 pinctrl_keyscan: keyscan {
 183                                         st,pins {
 184                                                 keyin0 = <&pio4 0 ALT6 IN>;
 185                                                 keyin1 = <&pio4 5 ALT4 IN>;
 186                                                 keyin2 = <&pio0 4 ALT2 IN>;
 187                                                 keyin3 = <&pio2 6 ALT2 IN>;
 188
 189                                                 keyout0 = <&pio4 6 ALT4 OUT>;
 190                                                 keyout1 = <&pio1 7 ALT2 OUT>;
 191                                                 keyout2 = <&pio0 6 ALT2 OUT>;
 192                                                 keyout3 = <&pio2 7 ALT2 OUT>;
 193                                         };
 194                                 };
 195                         };
 196
 197                         gmac1 {
 198                                 /*
 199                                  * Almost all the boards based on STiH407 SoC have an embedded
 200                                  * switch where the mdio/mdc have been used for managing the SMI
 201                                  * iface via I2C. For this reason these lines can be allocated
 202                                  * by using dedicated configuration (in case of there will be a
 203                                  * standard PHY transceiver on-board).
 204                                  */
 205                                 pinctrl_rgmii1: rgmii1-0 {
 206                                         st,pins {
 207
 208                                                 txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>;
 209                                                 txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>;
 210                                                 txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>;
 211                                                 txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>;
 212                                                 txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
 213                                                 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
 214                                                 rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>;
 215                                                 rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>;
 216                                                 rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
 217                                                 rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
 218                                                 rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>;
 219                                                 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
 220                                                 clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
 221                                                 phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>;
 222                                         };
 223                                 };
 224
 225                                 pinctrl_rgmii1_mdio: rgmii1-mdio {
 226                                         st,pins {
 227                                                 mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
 228                                                 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
 229                                                 mdint = <&pio1 3 ALT1 IN BYPASS 0>;
 230                                         };
 231                                 };
 232
 233                                 pinctrl_rgmii1_mdio_1: rgmii1-mdio-1 {
 234                                         st,pins {
 235                                                 mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
 236                                                 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
 237                                         };
 238                                 };
 239
 240                                 pinctrl_mii1: mii1 {
 241                                         st,pins {
 242                                                 txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 243                                                 txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 244                                                 txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 245                                                 txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 246                                                 txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 247                                                 txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 248                                                 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
 249                                                 col = <&pio0 7 ALT1 IN BYPASS 1000>;
 250
 251                                                 mdio = <&pio1 0 ALT1 OUT BYPASS 1500>;
 252                                                 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
 253                                                 crs = <&pio1 2 ALT1 IN BYPASS 1000>;
 254                                                 mdint = <&pio1 3 ALT1 IN BYPASS 0>;
 255                                                 rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 256                                                 rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 257                                                 rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 258                                                 rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 259
 260                                                 rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 261                                                 rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 262                                                 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
 263                                                 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
 264                                         };
 265                                 };
 266
 267                                 pinctrl_rmii1: rmii1-0 {
 268                                         st,pins {
 269                                                 txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 270                                                 txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 271                                                 txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 272                                                 mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
 273                                                 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
 274                                                 mdint = <&pio1 3 ALT1 IN BYPASS 0>;
 275                                                 rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_B>;
 276                                                 rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_B>;
 277                                                 rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_B>;
 278                                                 rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 279                                         };
 280                                 };
 281
 282                                 pinctrl_rmii1_phyclk: rmii1_phyclk {
 283                                         st,pins {
 284                                                 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
 285                                         };
 286                                 };
 287
 288                                 pinctrl_rmii1_phyclk_ext: rmii1_phyclk_ext {
 289                                         st,pins {
 290                                                 phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>;
 291                                         };
 292                                 };
 293                         };
 294
 295                         pwm1 {
 296                                 pinctrl_pwm1_chan0_default: pwm1-0-default {
 297                                         st,pins {
 298                                                 pwm-out = <&pio3 0 ALT1 OUT>;
 299                                         };
 300                                 };
 301                                 pinctrl_pwm1_chan1_default: pwm1-1-default {
 302                                         st,pins {
 303                                                 pwm-out = <&pio4 4 ALT1 OUT>;
 304                                         };
 305                                 };
 306                                 pinctrl_pwm1_chan2_default: pwm1-2-default {
 307                                         st,pins {
 308                                                 pwm-out = <&pio4 6 ALT3 OUT>;
 309                                         };
 310                                 };
 311                                 pinctrl_pwm1_chan3_default: pwm1-3-default {
 312                                         st,pins {
 313                                                 pwm-out = <&pio4 7 ALT3 OUT>;
 314                                         };
 315                                 };
 316                         };
 317
 318                         spi10 {
 319                                 pinctrl_spi10_default: spi10-4w-alt1-0 {
 320                                         st,pins {
 321                                                 mtsr = <&pio4 6 ALT1 OUT>;
 322                                                 mrst = <&pio4 7 ALT1 IN>;
 323                                                 scl = <&pio4 5 ALT1 OUT>;
 324                                         };
 325                                 };
 326
 327                                 pinctrl_spi10_3w_alt1_0: spi10-3w-alt1-0 {
 328                                         st,pins {
 329                                                 mtsr = <&pio4 6 ALT1 BIDIR_PU>;
 330                                                 scl = <&pio4 5 ALT1 OUT>;
 331                                         };
 332                                 };
 333                         };
 334
 335                         spi11 {
 336                                 pinctrl_spi11_default: spi11-4w-alt2-0 {
 337                                         st,pins {
 338                                                 mtsr = <&pio3 1 ALT2 OUT>;
 339                                                 mrst = <&pio3 0 ALT2 IN>;
 340                                                 scl = <&pio3 2 ALT2 OUT>;
 341                                         };
 342                                 };
 343
 344                                 pinctrl_spi11_3w_alt2_0: spi11-3w-alt2-0 {
 345                                         st,pins {
 346                                                 mtsr = <&pio3 1 ALT2 BIDIR_PU>;
 347                                                 scl = <&pio3 2 ALT2 OUT>;
 348                                         };
 349                                 };
 350                         };
 351
 352                         spi12 {
 353                                 pinctrl_spi12_default: spi12-4w-alt2-0 {
 354                                         st,pins {
 355                                                 mtsr = <&pio3 6 ALT2 OUT>;
 356                                                 mrst = <&pio3 4 ALT2 IN>;
 357                                                 scl = <&pio3 7 ALT2 OUT>;
 358                                         };
 359                                 };
 360
 361                                 pinctrl_spi12_3w_alt2_0: spi12-3w-alt2-0 {
 362                                         st,pins {
 363                                                 mtsr = <&pio3 6 ALT2 BIDIR_PU>;
 364                                                 scl = <&pio3 7 ALT2 OUT>;
 365                                         };
 366                                 };
 367                         };
 368                 };
 369
 370                 pin-controller-front0 {
 371                         #address-cells = <1>;
 372                         #size-cells = <1>;
 373                         compatible = "st,stih407-front-pinctrl";
 374                         st,syscfg = <&syscfg_front>;
 375                         reg = <0x0920f080 0x4>;
 376                         reg-names = "irqmux";
 377                         interrupts = <GIC_SPI 189 IRQ_TYPE_NONE>;
 378                         interrupt-names = "irqmux";
 379                         ranges = <0 0x09200000 0x10000>;
 380
 381                         pio10: pio@09200000 {
 382                                 gpio-controller;
 383                                 #gpio-cells = <2>;
 384                                 interrupt-controller;
 385                                 #interrupt-cells = <2>;
 386                                 reg = <0x0 0x100>;
 387                                 st,bank-name = "PIO10";
 388                         };
 389                         pio11: pio@09201000 {
 390                                 gpio-controller;
 391                                 #gpio-cells = <2>;
 392                                 interrupt-controller;
 393                                 #interrupt-cells = <2>;
 394                                 reg = <0x1000 0x100>;
 395                                 st,bank-name = "PIO11";
 396                         };
 397                         pio12: pio@09202000 {
 398                                 gpio-controller;
 399                                 #gpio-cells = <2>;
 400                                 interrupt-controller;
 401                                 #interrupt-cells = <2>;
 402                                 reg = <0x2000 0x100>;
 403                                 st,bank-name = "PIO12";
 404                         };
 405                         pio13: pio@09203000 {
 406                                 gpio-controller;
 407                                 #gpio-cells = <2>;
 408                                 interrupt-controller;
 409                                 #interrupt-cells = <2>;
 410                                 reg = <0x3000 0x100>;
 411                                 st,bank-name = "PIO13";
 412                         };
 413                         pio14: pio@09204000 {
 414                                 gpio-controller;
 415                                 #gpio-cells = <2>;
 416                                 interrupt-controller;
 417                                 #interrupt-cells = <2>;
 418                                 reg = <0x4000 0x100>;
 419                                 st,bank-name = "PIO14";
 420                         };
 421                         pio15: pio@09205000 {
 422                                 gpio-controller;
 423                                 #gpio-cells = <2>;
 424                                 interrupt-controller;
 425                                 #interrupt-cells = <2>;
 426                                 reg = <0x5000 0x100>;
 427                                 st,bank-name = "PIO15";
 428                         };
 429                         pio16: pio@09206000 {
 430                                 gpio-controller;
 431                                 #gpio-cells = <2>;
 432                                 interrupt-controller;
 433                                 #interrupt-cells = <2>;
 434                                 reg = <0x6000 0x100>;
 435                                 st,bank-name = "PIO16";
 436                         };
 437                         pio17: pio@09207000 {
 438                                 gpio-controller;
 439                                 #gpio-cells = <2>;
 440                                 interrupt-controller;
 441                                 #interrupt-cells = <2>;
 442                                 reg = <0x7000 0x100>;
 443                                 st,bank-name = "PIO17";
 444                         };
 445                         pio18: pio@09208000 {
 446                                 gpio-controller;
 447                                 #gpio-cells = <2>;
 448                                 interrupt-controller;
 449                                 #interrupt-cells = <2>;
 450                                 reg = <0x8000 0x100>;
 451                                 st,bank-name = "PIO18";
 452                         };
 453                         pio19: pio@09209000 {
 454                                 gpio-controller;
 455                                 #gpio-cells = <2>;
 456                                 interrupt-controller;
 457                                 #interrupt-cells = <2>;
 458                                 reg = <0x9000 0x100>;
 459                                 st,bank-name = "PIO19";
 460                         };
 461
 462                         /* Comms */
 463                         serial0 {
 464                                 pinctrl_serial0: serial0-0 {
 465                                         st,pins {
 466                                                 tx = <&pio17 0 ALT1 OUT>;
 467                                                 rx = <&pio17 1 ALT1 IN>;
 468                                         };
 469                                 };
 470                         };
 471
 472                         serial1 {
 473                                 pinctrl_serial1: serial1-0 {
 474                                         st,pins {
 475                                                 tx = <&pio16 0 ALT1 OUT>;
 476                                                 rx = <&pio16 1 ALT1 IN>;
 477                                         };
 478                                 };
 479                         };
 480
 481                         serial2 {
 482                                 pinctrl_serial2: serial2-0 {
 483                                         st,pins {
 484                                                 tx = <&pio15 0 ALT1 OUT>;
 485                                                 rx = <&pio15 1 ALT1 IN>;
 486                                         };
 487                                 };
 488                         };
 489
 490                         mmc1 {
 491                                 pinctrl_sd1: sd1-0 {
 492                                         st,pins {
 493                                                 sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>;
 494                                                 sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>;
 495                                                 sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>;
 496                                                 sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>;
 497                                                 sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>;
 498                                                 sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>;
 499                                                 sd_led = <&pio16 6 ALT6 OUT>;
 500                                                 sd_pwren = <&pio16 7 ALT6 OUT>;
 501                                                 sd_cd = <&pio19 0 ALT6 IN>;
 502                                                 sd_wp = <&pio19 1 ALT6 IN>;
 503                                         };
 504                                 };
 505                         };
 506
 507
 508                         i2c0 {
 509                                 pinctrl_i2c0_default: i2c0-default {
 510                                         st,pins {
 511                                                 sda = <&pio10 6 ALT2 BIDIR>;
 512                                                 scl = <&pio10 5 ALT2 BIDIR>;
 513                                         };
 514                                 };
 515                         };
 516
 517                         i2c1 {
 518                                 pinctrl_i2c1_default: i2c1-default {
 519                                         st,pins {
 520                                                 sda = <&pio11 1 ALT2 BIDIR>;
 521                                                 scl = <&pio11 0 ALT2 BIDIR>;
 522                                         };
 523                                 };
 524                         };
 525
 526                         i2c2 {
 527                                 pinctrl_i2c2_default: i2c2-default {
 528                                         st,pins {
 529                                                 sda = <&pio15 6 ALT2 BIDIR>;
 530                                                 scl = <&pio15 5 ALT2 BIDIR>;
 531                                         };
 532                                 };
 533
 534                                 pinctrl_i2c2_alt2_1: i2c2-alt2-1 {
 535                                         st,pins {
 536                                                 sda = <&pio12 6 ALT2 BIDIR>;
 537                                                 scl = <&pio12 5 ALT2 BIDIR>;
 538                                         };
 539                                 };
 540                         };
 541
 542                         i2c3 {
 543                                 pinctrl_i2c3_default: i2c3-alt1-0 {
 544                                         st,pins {
 545                                                 sda = <&pio18 6 ALT1 BIDIR>;
 546                                                 scl = <&pio18 5 ALT1 BIDIR>;
 547                                         };
 548                                 };
 549                                 pinctrl_i2c3_alt1_1: i2c3-alt1-1 {
 550                                         st,pins {
 551                                                 sda = <&pio17 7 ALT1 BIDIR>;
 552                                                 scl = <&pio17 6 ALT1 BIDIR>;
 553                                         };
 554                                 };
 555                                 pinctrl_i2c3_alt3_0: i2c3-alt3-0 {
 556                                         st,pins {
 557                                                 sda = <&pio13 6 ALT3 BIDIR>;
 558                                                 scl = <&pio13 5 ALT3 BIDIR>;
 559                                         };
 560                                 };
 561                         };
 562
 563                         spi0 {
 564                                 pinctrl_spi0_default: spi0-4w-alt2-0 {
 565                                         st,pins {
 566                                                 mtsr = <&pio10 6 ALT2 OUT>;
 567                                                 mrst = <&pio10 7 ALT2 IN>;
 568                                                 scl = <&pio10 5 ALT2 OUT>;
 569                                         };
 570                                 };
 571
 572                                 pinctrl_spi0_3w_alt2_0: spi0-3w-alt2-0 {
 573                                         st,pins {
 574                                                 mtsr = <&pio10 6 ALT2 BIDIR_PU>;
 575                                                 scl = <&pio10 5 ALT2 OUT>;
 576                                         };
 577                                 };
 578
 579                                 pinctrl_spi0_4w_alt1_0: spi0-4w-alt1-0 {
 580                                         st,pins {
 581                                                 mtsr = <&pio19 7 ALT1 OUT>;
 582                                                 mrst = <&pio19 5 ALT1 IN>;
 583                                                 scl = <&pio19 6 ALT1 OUT>;
 584                                         };
 585                                 };
 586
 587                                 pinctrl_spi0_3w_alt1_0: spi0-3w-alt1-0 {
 588                                         st,pins {
 589                                                 mtsr = <&pio19 7 ALT1 BIDIR_PU>;
 590                                                 scl = <&pio19 6 ALT1 OUT>;
 591                                         };
 592                                 };
 593                         };
 594
 595                         spi1 {
 596                                 pinctrl_spi1_default: spi1-4w-alt2-0 {
 597                                         st,pins {
 598                                                 mtsr = <&pio11 1 ALT2 OUT>;
 599                                                 mrst = <&pio11 2 ALT2 IN>;
 600                                                 scl = <&pio11 0 ALT2 OUT>;
 601                                         };
 602                                 };
 603
 604                                 pinctrl_spi1_3w_alt2_0: spi1-3w-alt2-0 {
 605                                         st,pins {
 606                                                 mtsr = <&pio11 1 ALT2 BIDIR_PU>;
 607                                                 scl = <&pio11 0 ALT2 OUT>;
 608                                         };
 609                                 };
 610
 611                                 pinctrl_spi1_4w_alt1_0: spi1-4w-alt1-0 {
 612                                         st,pins {
 613                                                 mtsr = <&pio14 3 ALT1 OUT>;
 614                                                 mrst = <&pio14 4 ALT1 IN>;
 615                                                 scl = <&pio14 2 ALT1 OUT>;
 616                                         };
 617                                 };
 618
 619                                 pinctrl_spi1_3w_alt1_0: spi1-3w-alt1-0 {
 620                                         st,pins {
 621                                                 mtsr = <&pio14 3 ALT1 BIDIR_PU>;
 622                                                 scl = <&pio14 2 ALT1 OUT>;
 623                                         };
 624                                 };
 625                         };
 626
 627                         spi2 {
 628                                 pinctrl_spi2_default: spi2-4w-alt2-0 {
 629                                         st,pins {
 630                                                 mtsr = <&pio12 6 ALT2 OUT>;
 631                                                 mrst = <&pio12 7 ALT2 IN>;
 632                                                 scl = <&pio12 5 ALT2 OUT>;
 633                                         };
 634                                 };
 635
 636                                 pinctrl_spi2_3w_alt2_0: spi2-3w-alt2-0 {
 637                                         st,pins {
 638                                                 mtsr = <&pio12 6 ALT2 BIDIR_PU>;
 639                                                 scl = <&pio12 5 ALT2 OUT>;
 640                                         };
 641                                 };
 642
 643                                 pinctrl_spi2_4w_alt1_0: spi2-4w-alt1-0 {
 644                                         st,pins {
 645                                                 mtsr = <&pio14 6 ALT1 OUT>;
 646                                                 mrst = <&pio14 7 ALT1 IN>;
 647                                                 scl = <&pio14 5 ALT1 OUT>;
 648                                         };
 649                                 };
 650
 651                                 pinctrl_spi2_3w_alt1_0: spi2-3w-alt1-0 {
 652                                         st,pins {
 653                                                 mtsr = <&pio14 6 ALT1 BIDIR_PU>;
 654                                                 scl = <&pio14 5 ALT1 OUT>;
 655                                         };
 656                                 };
 657
 658                                 pinctrl_spi2_4w_alt2_1: spi2-4w-alt2-1 {
 659                                         st,pins {
 660                                                 mtsr = <&pio15 6 ALT2 OUT>;
 661                                                 mrst = <&pio15 7 ALT2 IN>;
 662                                                 scl = <&pio15 5 ALT2 OUT>;
 663                                         };
 664                                 };
 665
 666                                 pinctrl_spi2_3w_alt2_1: spi2-3w-alt2-1 {
 667                                         st,pins {
 668                                                 mtsr = <&pio15 6 ALT2 BIDIR_PU>;
 669                                                 scl = <&pio15 5 ALT2 OUT>;
 670                                         };
 671                                 };
 672                         };
 673
 674                         spi3 {
 675                                 pinctrl_spi3_default: spi3-4w-alt3-0 {
 676                                         st,pins {
 677                                                 mtsr = <&pio13 6 ALT3 OUT>;
 678                                                 mrst = <&pio13 7 ALT3 IN>;
 679                                                 scl = <&pio13 5 ALT3 OUT>;
 680                                         };
 681                                 };
 682
 683                                 pinctrl_spi3_3w_alt3_0: spi3-3w-alt3-0 {
 684                                         st,pins {
 685                                                 mtsr = <&pio13 6 ALT3 BIDIR_PU>;
 686                                                 scl = <&pio13 5 ALT3 OUT>;
 687                                         };
 688                                 };
 689
 690                                 pinctrl_spi3_4w_alt1_0: spi3-4w-alt1-0 {
 691                                         st,pins {
 692                                                 mtsr = <&pio17 7 ALT1 OUT>;
 693                                                 mrst = <&pio17 5 ALT1 IN>;
 694                                                 scl = <&pio17 6 ALT1 OUT>;
 695                                         };
 696                                 };
 697
 698                                 pinctrl_spi3_3w_alt1_0: spi3-3w-alt1-0 {
 699                                         st,pins {
 700                                                 mtsr = <&pio17 7 ALT1 BIDIR_PU>;
 701                                                 scl = <&pio17 6 ALT1 OUT>;
 702                                         };
 703                                 };
 704
 705                                 pinctrl_spi3_4w_alt1_1: spi3-4w-alt1-1 {
 706                                         st,pins {
 707                                                 mtsr = <&pio18 6 ALT1 OUT>;
 708                                                 mrst = <&pio18 7 ALT1 IN>;
 709                                                 scl = <&pio18 5 ALT1 OUT>;
 710                                         };
 711                                 };
 712
 713                                 pinctrl_spi3_3w_alt1_1: spi3-3w-alt1-1 {
 714                                         st,pins {
 715                                                 mtsr = <&pio18 6 ALT1 BIDIR_PU>;
 716                                                 scl = <&pio18 5 ALT1 OUT>;
 717                                         };
 718                                 };
 719                         };
 720
 721                         tsin0 {
 722                                 pinctrl_tsin0_parallel: tsin0_parallel {
 723                                         st,pins {
 724                                                 DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 725                                                 DATA6 = <&pio10 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 726                                                 DATA5 = <&pio10 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 727                                                 DATA4 = <&pio10 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 728                                                 DATA3 = <&pio11 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 729                                                 DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 730                                                 DATA1 = <&pio11 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 731                                                 DATA0 = <&pio11 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 732                                                 CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
 733                                                 VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 734                                                 ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 735                                                 PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 736                                         };
 737                                 };
 738                                 pinctrl_tsin0_serial: tsin0_serial {
 739                                         st,pins {
 740                                                 DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 741                                                 CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
 742                                                 VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 743                                                 ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 744                                                 PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 745                                         };
 746                                 };
 747                         };
 748
 749                         tsin1 {
 750                                 pinctrl_tsin1_parallel: tsin1_parallel {
 751                                         st,pins {
 752                                                 DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 753                                                 DATA6 = <&pio12 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 754                                                 DATA5 = <&pio12 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 755                                                 DATA4 = <&pio12 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 756                                                 DATA3 = <&pio12 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 757                                                 DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 758                                                 DATA1 = <&pio12 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 759                                                 DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 760                                                 CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
 761                                                 VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 762                                                 ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 763                                                 PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 764                                         };
 765                                 };
 766                                 pinctrl_tsin1_serial: tsin1_serial {
 767                                         st,pins {
 768                                                 DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 769                                                 CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
 770                                                 VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 771                                                 ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 772                                                 PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 773                                         };
 774                                 };
 775                         };
 776
 777                         tsin2 {
 778                                 pinctrl_tsin2_parallel: tsin2_parallel {
 779                                         st,pins {
 780                                                 DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 781                                                 DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>;
 782                                                 DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>;
 783                                                 DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>;
 784                                                 DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 785                                                 DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>;
 786                                                 DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 787                                                 DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 788                                                 CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
 789                                                 VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 790                                                 ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 791                                                 PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 792                                         };
 793                                 };
 794                                 pinctrl_tsin2_serial: tsin2_serial {
 795                                         st,pins {
 796                                                 DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 797                                                 CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
 798                                                 VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 799                                                 ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 800                                                 PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 801                                         };
 802                                 };
 803                         };
 804
 805                         tsin3 {
 806                                 pinctrl_tsin3_serial: tsin3_serial {
 807                                         st,pins {
 808                                                 DATA7 = <&pio14 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 809                                                 CLKIN = <&pio14 0 ALT1 IN CLKNOTDATA 0 CLK_A>;
 810                                                 VALID = <&pio13 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 811                                                 ERROR = <&pio13 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 812                                                 PKCLK = <&pio13 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 813                                         };
 814                                 };
 815                         };
 816
 817                         tsin4 {
 818                                 pinctrl_tsin4_serial_alt3: tsin4_serial_alt3 {
 819                                         st,pins {
 820                                                 DATA7 = <&pio14 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 821                                                 CLKIN = <&pio14 5 ALT3 IN CLKNOTDATA 0 CLK_A>;
 822                                                 VALID = <&pio14 3 ALT3 IN SE_NICLK_IO 0 CLK_B>;
 823                                                 ERROR = <&pio14 2 ALT3 IN SE_NICLK_IO 0 CLK_B>;
 824                                                 PKCLK = <&pio14 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 825                                         };
 826                                 };
 827                         };
 828
 829                         tsin5 {
 830                                 pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 {
 831                                         st,pins {
 832                                                 DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 833                                                 CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
 834                                                 VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 835                                                 ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 836                                                 PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 837                                         };
 838                                 };
 839                                 pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 {
 840                                         st,pins {
 841                                                 DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 842                                                 CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>;
 843                                                 VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 844                                                 ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 845                                                 PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 846                                         };
 847                                 };
 848                         };
 849
 850                         tsout0 {
 851                                 pinctrl_tsout0_parallel: tsout0_parallel {
 852                                         st,pins {
 853                                                 DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 854                                                 DATA6 = <&pio12 1 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 855                                                 DATA5 = <&pio12 2 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 856                                                 DATA4 = <&pio12 3 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 857                                                 DATA3 = <&pio12 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 858                                                 DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 859                                                 DATA1 = <&pio12 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 860                                                 DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 861                                                 CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;
 862                                                 VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 863                                                 ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 864                                                 PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 865                                         };
 866                                 };
 867                                 pinctrl_tsout0_serial: tsout0_serial {
 868                                         st,pins {
 869                                                 DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 870                                                 CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;
 871                                                 VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 872                                                 ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 873                                                 PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 874                                         };
 875                                 };
 876                         };
 877
 878                         tsout1 {
 879                                 pinctrl_tsout1_serial: tsout1_serial {
 880                                         st,pins {
 881                                                 DATA7 = <&pio19 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 882                                                 CLKIN = <&pio19 3 ALT1 OUT NICLK 0 CLK_A>;
 883                                                 VALID = <&pio19 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 884                                                 ERROR = <&pio19 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 885                                                 PKCLK = <&pio19 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 886                                         };
 887                                 };
 888                         };
 889
 890                         mtsin0 {
 891                                 pinctrl_mtsin0_parallel: mtsin0_parallel {
 892                                         st,pins {
 893                                                 DATA7 = <&pio10 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 894                                                 DATA6 = <&pio10 5 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 895                                                 DATA5 = <&pio10 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 896                                                 DATA4 = <&pio10 7 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 897                                                 DATA3 = <&pio11 0 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 898                                                 DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 899                                                 DATA1 = <&pio11 2 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 900                                                 DATA0 = <&pio11 3 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 901                                                 CLKIN = <&pio10 3 ALT3 IN CLKNOTDATA 0 CLK_A>;
 902                                                 VALID = <&pio10 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 903                                                 ERROR = <&pio10 0 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 904                                                 PKCLK = <&pio10 2 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 905                                         };
 906                                 };
 907                         };
 908
 909                         systrace {
 910                                 pinctrl_systrace_default: systrace-default {
 911                                         st,pins {
 912                                                 trc_data0 = <&pio11 3 ALT5 OUT>;
 913                                                 trc_data1 = <&pio11 4 ALT5 OUT>;
 914                                                 trc_data2 = <&pio11 5 ALT5 OUT>;
 915                                                 trc_data3 = <&pio11 6 ALT5 OUT>;
 916                                                 trc_clk   = <&pio11 7 ALT5 OUT>;
 917                                         };
 918                                 };
 919                         };
 920                 };
 921
 922                 pin-controller-front1 {
 923                         #address-cells = <1>;
 924                         #size-cells = <1>;
 925                         compatible = "st,stih407-front-pinctrl";
 926                         st,syscfg = <&syscfg_front>;
 927                         reg = <0x0921f080 0x4>;
 928                         reg-names = "irqmux";
 929                         interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
 930                         interrupt-names = "irqmux";
 931                         ranges = <0 0x09210000 0x10000>;
 932
 933                         pio20: pio@09210000 {
 934                                 gpio-controller;
 935                                 #gpio-cells = <2>;
 936                                 interrupt-controller;
 937                                 #interrupt-cells = <2>;
 938                                 reg = <0x0 0x100>;
 939                                 st,bank-name = "PIO20";
 940                         };
 941
 942                         tsin4 {
 943                                 pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 {
 944                                         st,pins {
 945                                                 DATA7 = <&pio20 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 946                                                 CLKIN = <&pio20 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
 947                                                 VALID = <&pio20 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 948                                                 ERROR = <&pio20 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 949                                                 PKCLK = <&pio20 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 950                                         };
 951                                 };
 952                         };
 953                 };
 954
 955                 pin-controller-rear {
 956                         #address-cells = <1>;
 957                         #size-cells = <1>;
 958                         compatible = "st,stih407-rear-pinctrl";
 959                         st,syscfg = <&syscfg_rear>;
 960                         reg = <0x0922f080 0x4>;
 961                         reg-names = "irqmux";
 962                         interrupts = <GIC_SPI 191 IRQ_TYPE_NONE>;
 963                         interrupt-names = "irqmux";
 964                         ranges = <0 0x09220000 0x6000>;
 965
 966                         pio30: gpio@09220000 {
 967                                 gpio-controller;
 968                                 #gpio-cells = <2>;
 969                                 interrupt-controller;
 970                                 #interrupt-cells = <2>;
 971                                 reg = <0x0 0x100>;
 972                                 st,bank-name = "PIO30";
 973                         };
 974                         pio31: gpio@09221000 {
 975                                 gpio-controller;
 976                                 #gpio-cells = <2>;
 977                                 interrupt-controller;
 978                                 #interrupt-cells = <2>;
 979                                 reg = <0x1000 0x100>;
 980                                 st,bank-name = "PIO31";
 981                         };
 982                         pio32: gpio@09222000 {
 983                                 gpio-controller;
 984                                 #gpio-cells = <2>;
 985                                 interrupt-controller;
 986                                 #interrupt-cells = <2>;
 987                                 reg = <0x2000 0x100>;
 988                                 st,bank-name = "PIO32";
 989                         };
 990                         pio33: gpio@09223000 {
 991                                 gpio-controller;
 992                                 #gpio-cells = <2>;
 993                                 interrupt-controller;
 994                                 #interrupt-cells = <2>;
 995                                 reg = <0x3000 0x100>;
 996                                 st,bank-name = "PIO33";
 997                         };
 998                         pio34: gpio@09224000 {
 999                                 gpio-controller;
1000                                 #gpio-cells = <2>;
1001                                 interrupt-controller;
1002                                 #interrupt-cells = <2>;
1003                                 reg = <0x4000 0x100>;
1004                                 st,bank-name = "PIO34";
1005                         };
1006                         pio35: gpio@09225000 {
1007                                 gpio-controller;
1008                                 #gpio-cells = <2>;
1009                                 interrupt-controller;
1010                                 #interrupt-cells = <2>;
1011                                 reg = <0x5000 0x100>;
1012                                 st,bank-name = "PIO35";
1013                                 st,retime-pin-mask = <0x7f>;
1014                         };
1015
1016                         i2c4 {
1017                                 pinctrl_i2c4_default: i2c4-default {
1018                                         st,pins {
1019                                                 sda = <&pio30 1 ALT1 BIDIR>;
1020                                                 scl = <&pio30 0 ALT1 BIDIR>;
1021                                         };
1022                                 };
1023                         };
1024
1025                         i2c5 {
1026                                 pinctrl_i2c5_default: i2c5-default {
1027                                         st,pins {
1028                                                 sda = <&pio34 4 ALT1 BIDIR>;
1029                                                 scl = <&pio34 3 ALT1 BIDIR>;
1030                                         };
1031                                 };
1032                         };
1033
1034                         usb3 {
1035                                 pinctrl_usb3: usb3-2 {
1036                                         st,pins {
1037                                                 usb-oc-detect = <&pio35 4 ALT1 IN>;
1038                                                 usb-pwr-enable = <&pio35 5 ALT1 OUT>;
1039                                                 usb-vbus-valid = <&pio35 6 ALT1 IN>;
1040                                         };
1041                                 };
1042                         };
1043
1044                         pwm0 {
1045                                 pinctrl_pwm0_chan0_default: pwm0-0-default {
1046                                         st,pins {
1047                                                 pwm-out = <&pio31 1 ALT1 OUT>;
1048                                         };
1049                                 };
1050                         };
1051
1052                         spi4 {
1053                                 pinctrl_spi4_default: spi4-4w-alt1-0 {
1054                                         st,pins {
1055                                                 mtsr = <&pio30 1 ALT1 OUT>;
1056                                                 mrst = <&pio30 2 ALT1 IN>;
1057                                                 scl = <&pio30 0 ALT1 OUT>;
1058                                         };
1059                                 };
1060
1061                                 pinctrl_spi4_3w_alt1_0: spi4-3w-alt1-0 {
1062                                         st,pins {
1063                                                 mtsr = <&pio30 1 ALT1 BIDIR_PU>;
1064                                                 scl = <&pio30 0 ALT1 OUT>;
1065                                         };
1066                                 };
1067
1068                                 pinctrl_spi4_4w_alt3_0: spi4-4w-alt3-0 {
1069                                         st,pins {
1070                                                 mtsr = <&pio34 1 ALT3 OUT>;
1071                                                 mrst = <&pio34 2 ALT3 IN>;
1072                                                 scl = <&pio34 0 ALT3 OUT>;
1073                                         };
1074                                 };
1075
1076                                 pinctrl_spi4_3w_alt3_0: spi4-3w-alt3-0 {
1077                                         st,pins {
1078                                                 mtsr = <&pio34 1 ALT3 BIDIR_PU>;
1079                                                 scl = <&pio34 0 ALT3 OUT>;
1080                                         };
1081                                 };
1082                         };
1083
1084                         serial3 {
1085                                 pinctrl_serial3: serial3-0 {
1086                                         st,pins {
1087                                                 tx = <&pio31 3 ALT1 OUT>;
1088                                                 rx = <&pio31 4 ALT1 IN>;
1089                                         };
1090                                 };
1091                         };
1092                 };
1093
1094                 pin-controller-flash {
1095                         #address-cells = <1>;
1096                         #size-cells = <1>;
1097                         compatible = "st,stih407-flash-pinctrl";
1098                         st,syscfg = <&syscfg_flash>;
1099                         reg = <0x0923f080 0x4>;
1100                         reg-names = "irqmux";
1101                         interrupts = <GIC_SPI 192 IRQ_TYPE_NONE>;
1102                         interrupts-names = "irqmux";
1103                         ranges = <0 0x09230000 0x3000>;
1104
1105                         pio40: gpio@09230000 {
1106                                 gpio-controller;
1107                                 #gpio-cells = <2>;
1108                                 interrupt-controller;
1109                                 #interrupt-cells = <2>;
1110                                 reg = <0 0x100>;
1111                                 st,bank-name = "PIO40";
1112                         };
1113                         pio41: gpio@09231000 {
1114                                 gpio-controller;
1115                                 #gpio-cells = <2>;
1116                                 interrupt-controller;
1117                                 #interrupt-cells = <2>;
1118                                 reg = <0x1000 0x100>;
1119                                 st,bank-name = "PIO41";
1120                         };
1121                         pio42: gpio@09232000 {
1122                                 gpio-controller;
1123                                 #gpio-cells = <2>;
1124                                 interrupt-controller;
1125                                 #interrupt-cells = <2>;
1126                                 reg = <0x2000 0x100>;
1127                                 st,bank-name = "PIO42";
1128                         };
1129
1130                         mmc0 {
1131                                 pinctrl_mmc0: mmc0-0 {
1132                                         st,pins {
1133                                                 emmc_clk = <&pio40 6 ALT1 BIDIR>;
1134                                                 emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>;
1135                                                 emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>;
1136                                                 emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>;
1137                                                 emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>;
1138                                                 emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>;
1139                                                 emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>;
1140                                                 emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>;
1141                                                 emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>;
1142                                                 emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>;
1143                                         };
1144                                 };
1145                                 pinctrl_sd0: sd0-0 {
1146                                         st,pins {
1147                                                 sd_clk = <&pio40 6 ALT1 BIDIR>;
1148                                                 sd_cmd = <&pio40 7 ALT1 BIDIR_PU>;
1149                                                 sd_dat0 = <&pio41 0 ALT1 BIDIR_PU>;
1150                                                 sd_dat1 = <&pio41 1 ALT1 BIDIR_PU>;
1151                                                 sd_dat2 = <&pio41 2 ALT1 BIDIR_PU>;
1152                                                 sd_dat3 = <&pio41 3 ALT1 BIDIR_PU>;
1153                                                 sd_led = <&pio42 0 ALT2 OUT>;
1154                                                 sd_pwren = <&pio42 2 ALT2 OUT>;
1155                                                 sd_vsel = <&pio42 3 ALT2 OUT>;
1156                                                 sd_cd = <&pio42 4 ALT2 IN>;
1157                                                 sd_wp = <&pio42 5 ALT2 IN>;
1158                                         };
1159                                 };
1160                         };
1161
1162                         fsm {
1163                                 pinctrl_fsm: fsm {
1164                                         st,pins {
1165                                                 spi-fsm-clk = <&pio40 1 ALT1 OUT>;
1166                                                 spi-fsm-cs = <&pio40 0 ALT1 OUT>;
1167                                                 spi-fsm-mosi = <&pio40 2 ALT1 OUT>;
1168                                                 spi-fsm-miso = <&pio40 3 ALT1 IN>;
1169                                                 spi-fsm-hol = <&pio40 5 ALT1 OUT>;
1170                                                 spi-fsm-wp = <&pio40 4 ALT1 OUT>;
1171                                         };
1172                                 };
1173                         };
1174
1175                         nand {
1176                                 pinctrl_nand: nand {
1177                                         st,pins {
1178                                                 nand_cs1 = <&pio40 6 ALT3 OUT>;
1179                                                 nand_cs0 = <&pio40 7 ALT3 OUT>;
1180                                                 nand_d0 = <&pio41 0 ALT3 BIDIR>;
1181                                                 nand_d1 = <&pio41 1 ALT3 BIDIR>;
1182                                                 nand_d2 = <&pio41 2 ALT3 BIDIR>;
1183                                                 nand_d3 = <&pio41 3 ALT3 BIDIR>;
1184                                                 nand_d4 = <&pio41 4 ALT3 BIDIR>;
1185                                                 nand_d5 = <&pio41 5 ALT3 BIDIR>;
1186                                                 nand_d6 = <&pio41 6 ALT3 BIDIR>;
1187                                                 nand_d7 = <&pio41 7 ALT3 BIDIR>;
1188                                                 nand_we = <&pio42 0 ALT3 OUT>;
1189                                                 nand_dqs = <&pio42 1 ALT3 OUT>;
1190                                                 nand_ale = <&pio42 2 ALT3 OUT>;
1191                                                 nand_cle = <&pio42 3 ALT3 OUT>;
1192                                                 nand_rnb = <&pio42 4 ALT3 IN>;
1193                                                 nand_oe = <&pio42 5 ALT3 OUT>;
1194                                         };
1195                                 };
1196                         };
1197                 };
1198         };
1199 };