arch/arm/boot/dts/sun6i-a31.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&gic>;
  18
  19         aliases {
  20                 serial0 = &uart0;
  21                 serial1 = &uart1;
  22                 serial2 = &uart2;
  23                 serial3 = &uart3;
  24                 serial4 = &uart4;
  25                 serial5 = &uart5;
  26         };
  27
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu@0 {
  34                         compatible = "arm,cortex-a7";
  35                         device_type = "cpu";
  36                         reg = <0>;
  37                 };
  38
  39                 cpu@1 {
  40                         compatible = "arm,cortex-a7";
  41                         device_type = "cpu";
  42                         reg = <1>;
  43                 };
  44
  45                 cpu@2 {
  46                         compatible = "arm,cortex-a7";
  47                         device_type = "cpu";
  48                         reg = <2>;
  49                 };
  50
  51                 cpu@3 {
  52                         compatible = "arm,cortex-a7";
  53                         device_type = "cpu";
  54                         reg = <3>;
  55                 };
  56         };
  57
  58         memory {
  59                 reg = <0x40000000 0x80000000>;
  60         };
  61
  62         clocks {
  63                 #address-cells = <1>;
  64                 #size-cells = <1>;
  65                 ranges;
  66
  67                 osc24M: osc24M {
  68                         #clock-cells = <0>;
  69                         compatible = "fixed-clock";
  70                         clock-frequency = <24000000>;
  71                 };
  72
  73                 osc32k: osc32k {
  74                         #clock-cells = <0>;
  75                         compatible = "fixed-clock";
  76                         clock-frequency = <32768>;
  77                 };
  78
  79                 pll1: pll1@01c20000 {
  80                         #clock-cells = <0>;
  81                         compatible = "allwinner,sun6i-a31-pll1-clk";
  82                         reg = <0x01c20000 0x4>;
  83                         clocks = <&osc24M>;
  84                 };
  85
  86                 /*
  87                  * This is a dummy clock, to be used as placeholder on
  88                  * other mux clocks when a specific parent clock is not
  89                  * yet implemented. It should be dropped when the driver
  90                  * is complete.
  91                  */
  92                 pll6: pll6 {
  93                         #clock-cells = <0>;
  94                         compatible = "fixed-clock";
  95                         clock-frequency = <0>;
  96                 };
  97
  98                 cpu: cpu@01c20050 {
  99                         #clock-cells = <0>;
 100                         compatible = "allwinner,sun4i-cpu-clk";
 101                         reg = <0x01c20050 0x4>;
 102
 103                         /*
 104                          * PLL1 is listed twice here.
 105                          * While it looks suspicious, it's actually documented
 106                          * that way both in the datasheet and in the code from
 107                          * Allwinner.
 108                          */
 109                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 110                 };
 111
 112                 axi: axi@01c20050 {
 113                         #clock-cells = <0>;
 114                         compatible = "allwinner,sun4i-axi-clk";
 115                         reg = <0x01c20050 0x4>;
 116                         clocks = <&cpu>;
 117                 };
 118
 119                 ahb1_mux: ahb1_mux@01c20054 {
 120                         #clock-cells = <0>;
 121                         compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
 122                         reg = <0x01c20054 0x4>;
 123                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
 124                 };
 125
 126                 ahb1: ahb1@01c20054 {
 127                         #clock-cells = <0>;
 128                         compatible = "allwinner,sun4i-ahb-clk";
 129                         reg = <0x01c20054 0x4>;
 130                         clocks = <&ahb1_mux>;
 131                 };
 132
 133                 ahb1_gates: ahb1_gates@01c20060 {
 134                         #clock-cells = <1>;
 135                         compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
 136                         reg = <0x01c20060 0x8>;
 137                         clocks = <&ahb1>;
 138                         clock-output-names = "ahb1_mipidsi", "ahb1_ss",
 139                                         "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
 140                                         "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
 141                                         "ahb1_nand0", "ahb1_sdram",
 142                                         "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
 143                                         "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
 144                                         "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
 145                                         "ahb1_ehci1", "ahb1_ohci0",
 146                                         "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
 147                                         "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
 148                                         "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
 149                                         "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
 150                                         "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
 151                                         "ahb1_drc0", "ahb1_drc1";
 152                 };
 153
 154                 apb1: apb1@01c20054 {
 155                         #clock-cells = <0>;
 156                         compatible = "allwinner,sun4i-apb0-clk";
 157                         reg = <0x01c20054 0x4>;
 158                         clocks = <&ahb1>;
 159                 };
 160
 161                 apb1_gates: apb1_gates@01c20060 {
 162                         #clock-cells = <1>;
 163                         compatible = "allwinner,sun6i-a31-apb1-gates-clk";
 164                         reg = <0x01c20068 0x4>;
 165                         clocks = <&apb1>;
 166                         clock-output-names = "apb1_codec", "apb1_digital_mic",
 167                                         "apb1_pio", "apb1_daudio0",
 168                                         "apb1_daudio1";
 169                 };
 170
 171                 apb2_mux: apb2_mux@01c20058 {
 172                         #clock-cells = <0>;
 173                         compatible = "allwinner,sun4i-apb1-mux-clk";
 174                         reg = <0x01c20058 0x4>;
 175                         clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
 176                 };
 177
 178                 apb2: apb2@01c20058 {
 179                         #clock-cells = <0>;
 180                         compatible = "allwinner,sun6i-a31-apb2-div-clk";
 181                         reg = <0x01c20058 0x4>;
 182                         clocks = <&apb2_mux>;
 183                 };
 184
 185                 apb2_gates: apb2_gates@01c2006c {
 186                         #clock-cells = <1>;
 187                         compatible = "allwinner,sun6i-a31-apb2-gates-clk";
 188                         reg = <0x01c2006c 0x4>;
 189                         clocks = <&apb2>;
 190                         clock-output-names = "apb2_i2c0", "apb2_i2c1",
 191                                         "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
 192                                         "apb2_uart1", "apb2_uart2", "apb2_uart3",
 193                                         "apb2_uart4", "apb2_uart5";
 194                 };
 195         };
 196
 197         soc@01c00000 {
 198                 compatible = "simple-bus";
 199                 #address-cells = <1>;
 200                 #size-cells = <1>;
 201                 ranges;
 202
 203                 pio: pinctrl@01c20800 {
 204                         compatible = "allwinner,sun6i-a31-pinctrl";
 205                         reg = <0x01c20800 0x400>;
 206                         interrupts = <0 11 4>,
 207                                      <0 15 4>,
 208                                      <0 16 4>,
 209                                      <0 17 4>;
 210                         clocks = <&apb1_gates 5>;
 211                         gpio-controller;
 212                         interrupt-controller;
 213                         #address-cells = <1>;
 214                         #size-cells = <0>;
 215                         #gpio-cells = <3>;
 216
 217                         uart0_pins_a: uart0@0 {
 218                                 allwinner,pins = "PH20", "PH21";
 219                                 allwinner,function = "uart0";
 220                                 allwinner,drive = <0>;
 221                                 allwinner,pull = <0>;
 222                         };
 223                 };
 224
 225                 ahb1_rst: reset@01c202c0 {
 226                         #reset-cells = <1>;
 227                         compatible = "allwinner,sun6i-a31-ahb1-reset";
 228                         reg = <0x01c202c0 0xc>;
 229                 };
 230
 231                 apb1_rst: reset@01c202d0 {
 232                         #reset-cells = <1>;
 233                         compatible = "allwinner,sun6i-a31-clock-reset";
 234                         reg = <0x01c202d0 0x4>;
 235                 };
 236
 237                 apb2_rst: reset@01c202d8 {
 238                         #reset-cells = <1>;
 239                         compatible = "allwinner,sun6i-a31-clock-reset";
 240                         reg = <0x01c202d8 0x4>;
 241                 };
 242
 243                 timer@01c20c00 {
 244                         compatible = "allwinner,sun4i-timer";
 245                         reg = <0x01c20c00 0xa0>;
 246                         interrupts = <0 18 4>,
 247                                      <0 19 4>,
 248                                      <0 20 4>,
 249                                      <0 21 4>,
 250                                      <0 22 4>;
 251                         clocks = <&osc24M>;
 252                 };
 253
 254                 wdt1: watchdog@01c20ca0 {
 255                         compatible = "allwinner,sun6i-wdt";
 256                         reg = <0x01c20ca0 0x20>;
 257                 };
 258
 259                 uart0: serial@01c28000 {
 260                         compatible = "snps,dw-apb-uart";
 261                         reg = <0x01c28000 0x400>;
 262                         interrupts = <0 0 4>;
 263                         reg-shift = <2>;
 264                         reg-io-width = <4>;
 265                         clocks = <&apb2_gates 16>;
 266                         resets = <&apb2_rst 16>;
 267                         status = "disabled";
 268                 };
 269
 270                 uart1: serial@01c28400 {
 271                         compatible = "snps,dw-apb-uart";
 272                         reg = <0x01c28400 0x400>;
 273                         interrupts = <0 1 4>;
 274                         reg-shift = <2>;
 275                         reg-io-width = <4>;
 276                         clocks = <&apb2_gates 17>;
 277                         resets = <&apb2_rst 17>;
 278                         status = "disabled";
 279                 };
 280
 281                 uart2: serial@01c28800 {
 282                         compatible = "snps,dw-apb-uart";
 283                         reg = <0x01c28800 0x400>;
 284                         interrupts = <0 2 4>;
 285                         reg-shift = <2>;
 286                         reg-io-width = <4>;
 287                         clocks = <&apb2_gates 18>;
 288                         resets = <&apb2_rst 18>;
 289                         status = "disabled";
 290                 };
 291
 292                 uart3: serial@01c28c00 {
 293                         compatible = "snps,dw-apb-uart";
 294                         reg = <0x01c28c00 0x400>;
 295                         interrupts = <0 3 4>;
 296                         reg-shift = <2>;
 297                         reg-io-width = <4>;
 298                         clocks = <&apb2_gates 19>;
 299                         resets = <&apb2_rst 19>;
 300                         status = "disabled";
 301                 };
 302
 303                 uart4: serial@01c29000 {
 304                         compatible = "snps,dw-apb-uart";
 305                         reg = <0x01c29000 0x400>;
 306                         interrupts = <0 4 4>;
 307                         reg-shift = <2>;
 308                         reg-io-width = <4>;
 309                         clocks = <&apb2_gates 20>;
 310                         resets = <&apb2_rst 20>;
 311                         status = "disabled";
 312                 };
 313
 314                 uart5: serial@01c29400 {
 315                         compatible = "snps,dw-apb-uart";
 316                         reg = <0x01c29400 0x400>;
 317                         interrupts = <0 5 4>;
 318                         reg-shift = <2>;
 319                         reg-io-width = <4>;
 320                         clocks = <&apb2_gates 21>;
 321                         resets = <&apb2_rst 21>;
 322                         status = "disabled";
 323                 };
 324
 325                 gic: interrupt-controller@01c81000 {
 326                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 327                         reg = <0x01c81000 0x1000>,
 328                               <0x01c82000 0x1000>,
 329                               <0x01c84000 0x2000>,
 330                               <0x01c86000 0x2000>;
 331                         interrupt-controller;
 332                         #interrupt-cells = <3>;
 333                         interrupts = <1 9 0xf04>;
 334                 };
 335
 336                 cpucfg@01f01c00 {
 337                         compatible = "allwinner,sun6i-a31-cpuconfig";
 338                         reg = <0x01f01c00 0x300>;
 339                 };
 340
 341                 prcm@01f01c00 {
 342                         compatible = "allwinner,sun6i-a31-prcm";
 343                         reg = <0x01f01400 0x200>;
 344                 };
 345         };
 346 };