arch/arm/boot/dts/sun6i-a31.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&gic>;
  18
  19         aliases {
  20                 serial0 = &uart0;
  21                 serial1 = &uart1;
  22                 serial2 = &uart2;
  23                 serial3 = &uart3;
  24                 serial4 = &uart4;
  25                 serial5 = &uart5;
  26         };
  27
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu@0 {
  34                         compatible = "arm,cortex-a7";
  35                         device_type = "cpu";
  36                         reg = <0>;
  37                 };
  38
  39                 cpu@1 {
  40                         compatible = "arm,cortex-a7";
  41                         device_type = "cpu";
  42                         reg = <1>;
  43                 };
  44
  45                 cpu@2 {
  46                         compatible = "arm,cortex-a7";
  47                         device_type = "cpu";
  48                         reg = <2>;
  49                 };
  50
  51                 cpu@3 {
  52                         compatible = "arm,cortex-a7";
  53                         device_type = "cpu";
  54                         reg = <3>;
  55                 };
  56         };
  57
  58         memory {
  59                 reg = <0x40000000 0x80000000>;
  60         };
  61
  62         clocks {
  63                 #address-cells = <1>;
  64                 #size-cells = <1>;
  65                 ranges;
  66
  67                 osc24M: osc24M {
  68                         #clock-cells = <0>;
  69                         compatible = "fixed-clock";
  70                         clock-frequency = <24000000>;
  71                 };
  72
  73                 osc32k: osc32k {
  74                         #clock-cells = <0>;
  75                         compatible = "fixed-clock";
  76                         clock-frequency = <32768>;
  77                 };
  78
  79                 pll1: pll1@01c20000 {
  80                         #clock-cells = <0>;
  81                         compatible = "allwinner,sun6i-a31-pll1-clk";
  82                         reg = <0x01c20000 0x4>;
  83                         clocks = <&osc24M>;
  84                 };
  85
  86                 pll6: clk@01c20028 {
  87                         #clock-cells = <0>;
  88                         compatible = "allwinner,sun6i-a31-pll6-clk";
  89                         reg = <0x01c20028 0x4>;
  90                         clocks = <&osc24M>;
  91                         clock-output-names = "pll6";
  92                 };
  93
  94                 cpu: cpu@01c20050 {
  95                         #clock-cells = <0>;
  96                         compatible = "allwinner,sun4i-cpu-clk";
  97                         reg = <0x01c20050 0x4>;
  98
  99                         /*
 100                          * PLL1 is listed twice here.
 101                          * While it looks suspicious, it's actually documented
 102                          * that way both in the datasheet and in the code from
 103                          * Allwinner.
 104                          */
 105                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 106                 };
 107
 108                 axi: axi@01c20050 {
 109                         #clock-cells = <0>;
 110                         compatible = "allwinner,sun4i-axi-clk";
 111                         reg = <0x01c20050 0x4>;
 112                         clocks = <&cpu>;
 113                 };
 114
 115                 ahb1_mux: ahb1_mux@01c20054 {
 116                         #clock-cells = <0>;
 117                         compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
 118                         reg = <0x01c20054 0x4>;
 119                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
 120                 };
 121
 122                 ahb1: ahb1@01c20054 {
 123                         #clock-cells = <0>;
 124                         compatible = "allwinner,sun4i-ahb-clk";
 125                         reg = <0x01c20054 0x4>;
 126                         clocks = <&ahb1_mux>;
 127                 };
 128
 129                 ahb1_gates: ahb1_gates@01c20060 {
 130                         #clock-cells = <1>;
 131                         compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
 132                         reg = <0x01c20060 0x8>;
 133                         clocks = <&ahb1>;
 134                         clock-output-names = "ahb1_mipidsi", "ahb1_ss",
 135                                         "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
 136                                         "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
 137                                         "ahb1_nand0", "ahb1_sdram",
 138                                         "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
 139                                         "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
 140                                         "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
 141                                         "ahb1_ehci1", "ahb1_ohci0",
 142                                         "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
 143                                         "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
 144                                         "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
 145                                         "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
 146                                         "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
 147                                         "ahb1_drc0", "ahb1_drc1";
 148                 };
 149
 150                 apb1: apb1@01c20054 {
 151                         #clock-cells = <0>;
 152                         compatible = "allwinner,sun4i-apb0-clk";
 153                         reg = <0x01c20054 0x4>;
 154                         clocks = <&ahb1>;
 155                 };
 156
 157                 apb1_gates: apb1_gates@01c20060 {
 158                         #clock-cells = <1>;
 159                         compatible = "allwinner,sun6i-a31-apb1-gates-clk";
 160                         reg = <0x01c20068 0x4>;
 161                         clocks = <&apb1>;
 162                         clock-output-names = "apb1_codec", "apb1_digital_mic",
 163                                         "apb1_pio", "apb1_daudio0",
 164                                         "apb1_daudio1";
 165                 };
 166
 167                 apb2_mux: apb2_mux@01c20058 {
 168                         #clock-cells = <0>;
 169                         compatible = "allwinner,sun4i-apb1-mux-clk";
 170                         reg = <0x01c20058 0x4>;
 171                         clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
 172                 };
 173
 174                 apb2: apb2@01c20058 {
 175                         #clock-cells = <0>;
 176                         compatible = "allwinner,sun6i-a31-apb2-div-clk";
 177                         reg = <0x01c20058 0x4>;
 178                         clocks = <&apb2_mux>;
 179                 };
 180
 181                 apb2_gates: apb2_gates@01c2006c {
 182                         #clock-cells = <1>;
 183                         compatible = "allwinner,sun6i-a31-apb2-gates-clk";
 184                         reg = <0x01c2006c 0x4>;
 185                         clocks = <&apb2>;
 186                         clock-output-names = "apb2_i2c0", "apb2_i2c1",
 187                                         "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
 188                                         "apb2_uart1", "apb2_uart2", "apb2_uart3",
 189                                         "apb2_uart4", "apb2_uart5";
 190                 };
 191
 192                 spi0_clk: clk@01c200a0 {
 193                         #clock-cells = <0>;
 194                         compatible = "allwinner,sun4i-mod0-clk";
 195                         reg = <0x01c200a0 0x4>;
 196                         clocks = <&osc24M>, <&pll6>;
 197                         clock-output-names = "spi0";
 198                 };
 199
 200                 spi1_clk: clk@01c200a4 {
 201                         #clock-cells = <0>;
 202                         compatible = "allwinner,sun4i-mod0-clk";
 203                         reg = <0x01c200a4 0x4>;
 204                         clocks = <&osc24M>, <&pll6>;
 205                         clock-output-names = "spi1";
 206                 };
 207
 208                 spi2_clk: clk@01c200a8 {
 209                         #clock-cells = <0>;
 210                         compatible = "allwinner,sun4i-mod0-clk";
 211                         reg = <0x01c200a8 0x4>;
 212                         clocks = <&osc24M>, <&pll6>;
 213                         clock-output-names = "spi2";
 214                 };
 215
 216                 spi3_clk: clk@01c200ac {
 217                         #clock-cells = <0>;
 218                         compatible = "allwinner,sun4i-mod0-clk";
 219                         reg = <0x01c200ac 0x4>;
 220                         clocks = <&osc24M>, <&pll6>;
 221                         clock-output-names = "spi3";
 222                 };
 223         };
 224
 225         soc@01c00000 {
 226                 compatible = "simple-bus";
 227                 #address-cells = <1>;
 228                 #size-cells = <1>;
 229                 ranges;
 230
 231                 pio: pinctrl@01c20800 {
 232                         compatible = "allwinner,sun6i-a31-pinctrl";
 233                         reg = <0x01c20800 0x400>;
 234                         interrupts = <0 11 4>,
 235                                      <0 15 4>,
 236                                      <0 16 4>,
 237                                      <0 17 4>;
 238                         clocks = <&apb1_gates 5>;
 239                         gpio-controller;
 240                         interrupt-controller;
 241                         #address-cells = <1>;
 242                         #size-cells = <0>;
 243                         #gpio-cells = <3>;
 244
 245                         uart0_pins_a: uart0@0 {
 246                                 allwinner,pins = "PH20", "PH21";
 247                                 allwinner,function = "uart0";
 248                                 allwinner,drive = <0>;
 249                                 allwinner,pull = <0>;
 250                         };
 251                 };
 252
 253                 ahb1_rst: reset@01c202c0 {
 254                         #reset-cells = <1>;
 255                         compatible = "allwinner,sun6i-a31-ahb1-reset";
 256                         reg = <0x01c202c0 0xc>;
 257                 };
 258
 259                 apb1_rst: reset@01c202d0 {
 260                         #reset-cells = <1>;
 261                         compatible = "allwinner,sun6i-a31-clock-reset";
 262                         reg = <0x01c202d0 0x4>;
 263                 };
 264
 265                 apb2_rst: reset@01c202d8 {
 266                         #reset-cells = <1>;
 267                         compatible = "allwinner,sun6i-a31-clock-reset";
 268                         reg = <0x01c202d8 0x4>;
 269                 };
 270
 271                 timer@01c20c00 {
 272                         compatible = "allwinner,sun4i-timer";
 273                         reg = <0x01c20c00 0xa0>;
 274                         interrupts = <0 18 4>,
 275                                      <0 19 4>,
 276                                      <0 20 4>,
 277                                      <0 21 4>,
 278                                      <0 22 4>;
 279                         clocks = <&osc24M>;
 280                 };
 281
 282                 wdt1: watchdog@01c20ca0 {
 283                         compatible = "allwinner,sun6i-wdt";
 284                         reg = <0x01c20ca0 0x20>;
 285                 };
 286
 287                 uart0: serial@01c28000 {
 288                         compatible = "snps,dw-apb-uart";
 289                         reg = <0x01c28000 0x400>;
 290                         interrupts = <0 0 4>;
 291                         reg-shift = <2>;
 292                         reg-io-width = <4>;
 293                         clocks = <&apb2_gates 16>;
 294                         resets = <&apb2_rst 16>;
 295                         status = "disabled";
 296                 };
 297
 298                 uart1: serial@01c28400 {
 299                         compatible = "snps,dw-apb-uart";
 300                         reg = <0x01c28400 0x400>;
 301                         interrupts = <0 1 4>;
 302                         reg-shift = <2>;
 303                         reg-io-width = <4>;
 304                         clocks = <&apb2_gates 17>;
 305                         resets = <&apb2_rst 17>;
 306                         status = "disabled";
 307                 };
 308
 309                 uart2: serial@01c28800 {
 310                         compatible = "snps,dw-apb-uart";
 311                         reg = <0x01c28800 0x400>;
 312                         interrupts = <0 2 4>;
 313                         reg-shift = <2>;
 314                         reg-io-width = <4>;
 315                         clocks = <&apb2_gates 18>;
 316                         resets = <&apb2_rst 18>;
 317                         status = "disabled";
 318                 };
 319
 320                 uart3: serial@01c28c00 {
 321                         compatible = "snps,dw-apb-uart";
 322                         reg = <0x01c28c00 0x400>;
 323                         interrupts = <0 3 4>;
 324                         reg-shift = <2>;
 325                         reg-io-width = <4>;
 326                         clocks = <&apb2_gates 19>;
 327                         resets = <&apb2_rst 19>;
 328                         status = "disabled";
 329                 };
 330
 331                 uart4: serial@01c29000 {
 332                         compatible = "snps,dw-apb-uart";
 333                         reg = <0x01c29000 0x400>;
 334                         interrupts = <0 4 4>;
 335                         reg-shift = <2>;
 336                         reg-io-width = <4>;
 337                         clocks = <&apb2_gates 20>;
 338                         resets = <&apb2_rst 20>;
 339                         status = "disabled";
 340                 };
 341
 342                 uart5: serial@01c29400 {
 343                         compatible = "snps,dw-apb-uart";
 344                         reg = <0x01c29400 0x400>;
 345                         interrupts = <0 5 4>;
 346                         reg-shift = <2>;
 347                         reg-io-width = <4>;
 348                         clocks = <&apb2_gates 21>;
 349                         resets = <&apb2_rst 21>;
 350                         status = "disabled";
 351                 };
 352
 353                 gic: interrupt-controller@01c81000 {
 354                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 355                         reg = <0x01c81000 0x1000>,
 356                               <0x01c82000 0x1000>,
 357                               <0x01c84000 0x2000>,
 358                               <0x01c86000 0x2000>;
 359                         interrupt-controller;
 360                         #interrupt-cells = <3>;
 361                         interrupts = <1 9 0xf04>;
 362                 };
 363
 364                 cpucfg@01f01c00 {
 365                         compatible = "allwinner,sun6i-a31-cpuconfig";
 366                         reg = <0x01f01c00 0x300>;
 367                 };
 368
 369                 prcm@01f01c00 {
 370                         compatible = "allwinner,sun6i-a31-prcm";
 371                         reg = <0x01f01400 0x200>;
 372                 };
 373         };
 374 };