arch/arm/boot/dts/sun7i-a20.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&gic>;
  18
  19         aliases {
  20                 ethernet0 = &gmac;
  21                 serial0 = &uart0;
  22                 serial1 = &uart1;
  23                 serial2 = &uart2;
  24                 serial3 = &uart3;
  25                 serial4 = &uart4;
  26                 serial5 = &uart5;
  27                 serial6 = &uart6;
  28                 serial7 = &uart7;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 cpu@0 {
  36                         compatible = "arm,cortex-a7";
  37                         device_type = "cpu";
  38                         reg = <0>;
  39                 };
  40
  41                 cpu@1 {
  42                         compatible = "arm,cortex-a7";
  43                         device_type = "cpu";
  44                         reg = <1>;
  45                 };
  46         };
  47
  48         memory {
  49                 reg = <0x40000000 0x80000000>;
  50         };
  51
  52         timer {
  53                 compatible = "arm,armv7-timer";
  54                 interrupts = <1 13 0xf08>,
  55                              <1 14 0xf08>,
  56                              <1 11 0xf08>,
  57                              <1 10 0xf08>;
  58         };
  59
  60         clocks {
  61                 #address-cells = <1>;
  62                 #size-cells = <1>;
  63                 ranges;
  64
  65                 osc24M: clk@01c20050 {
  66                         #clock-cells = <0>;
  67                         compatible = "allwinner,sun4i-a10-osc-clk";
  68                         reg = <0x01c20050 0x4>;
  69                         clock-frequency = <24000000>;
  70                         clock-output-names = "osc24M";
  71                 };
  72
  73                 osc32k: clk@0 {
  74                         #clock-cells = <0>;
  75                         compatible = "fixed-clock";
  76                         clock-frequency = <32768>;
  77                         clock-output-names = "osc32k";
  78                 };
  79
  80                 pll1: clk@01c20000 {
  81                         #clock-cells = <0>;
  82                         compatible = "allwinner,sun4i-a10-pll1-clk";
  83                         reg = <0x01c20000 0x4>;
  84                         clocks = <&osc24M>;
  85                         clock-output-names = "pll1";
  86                 };
  87
  88                 pll4: clk@01c20018 {
  89                         #clock-cells = <0>;
  90                         compatible = "allwinner,sun7i-a20-pll4-clk";
  91                         reg = <0x01c20018 0x4>;
  92                         clocks = <&osc24M>;
  93                         clock-output-names = "pll4";
  94                 };
  95
  96                 pll5: clk@01c20020 {
  97                         #clock-cells = <1>;
  98                         compatible = "allwinner,sun4i-a10-pll5-clk";
  99                         reg = <0x01c20020 0x4>;
 100                         clocks = <&osc24M>;
 101                         clock-output-names = "pll5_ddr", "pll5_other";
 102                 };
 103
 104                 pll6: clk@01c20028 {
 105                         #clock-cells = <1>;
 106                         compatible = "allwinner,sun4i-a10-pll6-clk";
 107                         reg = <0x01c20028 0x4>;
 108                         clocks = <&osc24M>;
 109                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 110                 };
 111
 112                 pll8: clk@01c20040 {
 113                         #clock-cells = <0>;
 114                         compatible = "allwinner,sun7i-a20-pll4-clk";
 115                         reg = <0x01c20040 0x4>;
 116                         clocks = <&osc24M>;
 117                         clock-output-names = "pll8";
 118                 };
 119
 120                 cpu: cpu@01c20054 {
 121                         #clock-cells = <0>;
 122                         compatible = "allwinner,sun4i-a10-cpu-clk";
 123                         reg = <0x01c20054 0x4>;
 124                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
 125                         clock-output-names = "cpu";
 126                 };
 127
 128                 axi: axi@01c20054 {
 129                         #clock-cells = <0>;
 130                         compatible = "allwinner,sun4i-a10-axi-clk";
 131                         reg = <0x01c20054 0x4>;
 132                         clocks = <&cpu>;
 133                         clock-output-names = "axi";
 134                 };
 135
 136                 ahb: ahb@01c20054 {
 137                         #clock-cells = <0>;
 138                         compatible = "allwinner,sun4i-a10-ahb-clk";
 139                         reg = <0x01c20054 0x4>;
 140                         clocks = <&axi>;
 141                         clock-output-names = "ahb";
 142                 };
 143
 144                 ahb_gates: clk@01c20060 {
 145                         #clock-cells = <1>;
 146                         compatible = "allwinner,sun7i-a20-ahb-gates-clk";
 147                         reg = <0x01c20060 0x8>;
 148                         clocks = <&ahb>;
 149                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 150                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
 151                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 152                                 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
 153                                 "ahb_nand", "ahb_sdram", "ahb_ace",
 154                                 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
 155                                 "ahb_spi2", "ahb_spi3", "ahb_sata",
 156                                 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
 157                                 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
 158                                 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
 159                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 160                                 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
 161                                 "ahb_mali";
 162                 };
 163
 164                 apb0: apb0@01c20054 {
 165                         #clock-cells = <0>;
 166                         compatible = "allwinner,sun4i-a10-apb0-clk";
 167                         reg = <0x01c20054 0x4>;
 168                         clocks = <&ahb>;
 169                         clock-output-names = "apb0";
 170                 };
 171
 172                 apb0_gates: clk@01c20068 {
 173                         #clock-cells = <1>;
 174                         compatible = "allwinner,sun7i-a20-apb0-gates-clk";
 175                         reg = <0x01c20068 0x4>;
 176                         clocks = <&apb0>;
 177                         clock-output-names = "apb0_codec", "apb0_spdif",
 178                                 "apb0_ac97", "apb0_iis0", "apb0_iis1",
 179                                 "apb0_pio", "apb0_ir0", "apb0_ir1",
 180                                 "apb0_iis2", "apb0_keypad";
 181                 };
 182
 183                 apb1_mux: apb1_mux@01c20058 {
 184                         #clock-cells = <0>;
 185                         compatible = "allwinner,sun4i-a10-apb1-mux-clk";
 186                         reg = <0x01c20058 0x4>;
 187                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 188                         clock-output-names = "apb1_mux";
 189                 };
 190
 191                 apb1: apb1@01c20058 {
 192                         #clock-cells = <0>;
 193                         compatible = "allwinner,sun4i-a10-apb1-clk";
 194                         reg = <0x01c20058 0x4>;
 195                         clocks = <&apb1_mux>;
 196                         clock-output-names = "apb1";
 197                 };
 198
 199                 apb1_gates: clk@01c2006c {
 200                         #clock-cells = <1>;
 201                         compatible = "allwinner,sun7i-a20-apb1-gates-clk";
 202                         reg = <0x01c2006c 0x4>;
 203                         clocks = <&apb1>;
 204                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 205                                 "apb1_i2c2", "apb1_i2c3", "apb1_can",
 206                                 "apb1_scr", "apb1_ps20", "apb1_ps21",
 207                                 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
 208                                 "apb1_uart2", "apb1_uart3", "apb1_uart4",
 209                                 "apb1_uart5", "apb1_uart6", "apb1_uart7";
 210                 };
 211
 212                 nand_clk: clk@01c20080 {
 213                         #clock-cells = <0>;
 214                         compatible = "allwinner,sun4i-a10-mod0-clk";
 215                         reg = <0x01c20080 0x4>;
 216                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 217                         clock-output-names = "nand";
 218                 };
 219
 220                 ms_clk: clk@01c20084 {
 221                         #clock-cells = <0>;
 222                         compatible = "allwinner,sun4i-a10-mod0-clk";
 223                         reg = <0x01c20084 0x4>;
 224                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 225                         clock-output-names = "ms";
 226                 };
 227
 228                 mmc0_clk: clk@01c20088 {
 229                         #clock-cells = <0>;
 230                         compatible = "allwinner,sun4i-a10-mod0-clk";
 231                         reg = <0x01c20088 0x4>;
 232                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 233                         clock-output-names = "mmc0";
 234                 };
 235
 236                 mmc1_clk: clk@01c2008c {
 237                         #clock-cells = <0>;
 238                         compatible = "allwinner,sun4i-a10-mod0-clk";
 239                         reg = <0x01c2008c 0x4>;
 240                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 241                         clock-output-names = "mmc1";
 242                 };
 243
 244                 mmc2_clk: clk@01c20090 {
 245                         #clock-cells = <0>;
 246                         compatible = "allwinner,sun4i-a10-mod0-clk";
 247                         reg = <0x01c20090 0x4>;
 248                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 249                         clock-output-names = "mmc2";
 250                 };
 251
 252                 mmc3_clk: clk@01c20094 {
 253                         #clock-cells = <0>;
 254                         compatible = "allwinner,sun4i-a10-mod0-clk";
 255                         reg = <0x01c20094 0x4>;
 256                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 257                         clock-output-names = "mmc3";
 258                 };
 259
 260                 ts_clk: clk@01c20098 {
 261                         #clock-cells = <0>;
 262                         compatible = "allwinner,sun4i-a10-mod0-clk";
 263                         reg = <0x01c20098 0x4>;
 264                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 265                         clock-output-names = "ts";
 266                 };
 267
 268                 ss_clk: clk@01c2009c {
 269                         #clock-cells = <0>;
 270                         compatible = "allwinner,sun4i-a10-mod0-clk";
 271                         reg = <0x01c2009c 0x4>;
 272                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 273                         clock-output-names = "ss";
 274                 };
 275
 276                 spi0_clk: clk@01c200a0 {
 277                         #clock-cells = <0>;
 278                         compatible = "allwinner,sun4i-a10-mod0-clk";
 279                         reg = <0x01c200a0 0x4>;
 280                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 281                         clock-output-names = "spi0";
 282                 };
 283
 284                 spi1_clk: clk@01c200a4 {
 285                         #clock-cells = <0>;
 286                         compatible = "allwinner,sun4i-a10-mod0-clk";
 287                         reg = <0x01c200a4 0x4>;
 288                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 289                         clock-output-names = "spi1";
 290                 };
 291
 292                 spi2_clk: clk@01c200a8 {
 293                         #clock-cells = <0>;
 294                         compatible = "allwinner,sun4i-a10-mod0-clk";
 295                         reg = <0x01c200a8 0x4>;
 296                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 297                         clock-output-names = "spi2";
 298                 };
 299
 300                 pata_clk: clk@01c200ac {
 301                         #clock-cells = <0>;
 302                         compatible = "allwinner,sun4i-a10-mod0-clk";
 303                         reg = <0x01c200ac 0x4>;
 304                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 305                         clock-output-names = "pata";
 306                 };
 307
 308                 ir0_clk: clk@01c200b0 {
 309                         #clock-cells = <0>;
 310                         compatible = "allwinner,sun4i-a10-mod0-clk";
 311                         reg = <0x01c200b0 0x4>;
 312                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 313                         clock-output-names = "ir0";
 314                 };
 315
 316                 ir1_clk: clk@01c200b4 {
 317                         #clock-cells = <0>;
 318                         compatible = "allwinner,sun4i-a10-mod0-clk";
 319                         reg = <0x01c200b4 0x4>;
 320                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 321                         clock-output-names = "ir1";
 322                 };
 323
 324                 usb_clk: clk@01c200cc {
 325                         #clock-cells = <1>;
 326                         #reset-cells = <1>;
 327                         compatible = "allwinner,sun4i-a10-usb-clk";
 328                         reg = <0x01c200cc 0x4>;
 329                         clocks = <&pll6 1>;
 330                         clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
 331                 };
 332
 333                 spi3_clk: clk@01c200d4 {
 334                         #clock-cells = <0>;
 335                         compatible = "allwinner,sun4i-a10-mod0-clk";
 336                         reg = <0x01c200d4 0x4>;
 337                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 338                         clock-output-names = "spi3";
 339                 };
 340
 341                 mbus_clk: clk@01c2015c {
 342                         #clock-cells = <0>;
 343                         compatible = "allwinner,sun4i-a10-mod0-clk";
 344                         reg = <0x01c2015c 0x4>;
 345                         clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
 346                         clock-output-names = "mbus";
 347                 };
 348
 349                 /*
 350                  * The following two are dummy clocks, placeholders used in the gmac_tx
 351                  * clock. The gmac driver will choose one parent depending on the PHY
 352                  * interface mode, using clk_set_rate auto-reparenting.
 353                  * The actual TX clock rate is not controlled by the gmac_tx clock.
 354                  */
 355                 mii_phy_tx_clk: clk@2 {
 356                         #clock-cells = <0>;
 357                         compatible = "fixed-clock";
 358                         clock-frequency = <25000000>;
 359                         clock-output-names = "mii_phy_tx";
 360                 };
 361
 362                 gmac_int_tx_clk: clk@3 {
 363                         #clock-cells = <0>;
 364                         compatible = "fixed-clock";
 365                         clock-frequency = <125000000>;
 366                         clock-output-names = "gmac_int_tx";
 367                 };
 368
 369                 gmac_tx_clk: clk@01c20164 {
 370                         #clock-cells = <0>;
 371                         compatible = "allwinner,sun7i-a20-gmac-clk";
 372                         reg = <0x01c20164 0x4>;
 373                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 374                         clock-output-names = "gmac_tx";
 375                 };
 376
 377                 /*
 378                  * Dummy clock used by output clocks
 379                  */
 380                 osc24M_32k: clk@1 {
 381                         #clock-cells = <0>;
 382                         compatible = "fixed-factor-clock";
 383                         clock-div = <750>;
 384                         clock-mult = <1>;
 385                         clocks = <&osc24M>;
 386                         clock-output-names = "osc24M_32k";
 387                 };
 388
 389                 clk_out_a: clk@01c201f0 {
 390                         #clock-cells = <0>;
 391                         compatible = "allwinner,sun7i-a20-out-clk";
 392                         reg = <0x01c201f0 0x4>;
 393                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 394                         clock-output-names = "clk_out_a";
 395                 };
 396
 397                 clk_out_b: clk@01c201f4 {
 398                         #clock-cells = <0>;
 399                         compatible = "allwinner,sun7i-a20-out-clk";
 400                         reg = <0x01c201f4 0x4>;
 401                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 402                         clock-output-names = "clk_out_b";
 403                 };
 404         };
 405
 406         soc@01c00000 {
 407                 compatible = "simple-bus";
 408                 #address-cells = <1>;
 409                 #size-cells = <1>;
 410                 ranges;
 411
 412                 nmi_intc: interrupt-controller@01c00030 {
 413                         compatible = "allwinner,sun7i-a20-sc-nmi";
 414                         interrupt-controller;
 415                         #interrupt-cells = <2>;
 416                         reg = <0x01c00030 0x0c>;
 417                         interrupts = <0 0 4>;
 418                 };
 419
 420                 spi0: spi@01c05000 {
 421                         compatible = "allwinner,sun4i-a10-spi";
 422                         reg = <0x01c05000 0x1000>;
 423                         interrupts = <0 10 4>;
 424                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 425                         clock-names = "ahb", "mod";
 426                         status = "disabled";
 427                         #address-cells = <1>;
 428                         #size-cells = <0>;
 429                 };
 430
 431                 spi1: spi@01c06000 {
 432                         compatible = "allwinner,sun4i-a10-spi";
 433                         reg = <0x01c06000 0x1000>;
 434                         interrupts = <0 11 4>;
 435                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 436                         clock-names = "ahb", "mod";
 437                         status = "disabled";
 438                         #address-cells = <1>;
 439                         #size-cells = <0>;
 440                 };
 441
 442                 emac: ethernet@01c0b000 {
 443                         compatible = "allwinner,sun4i-a10-emac";
 444                         reg = <0x01c0b000 0x1000>;
 445                         interrupts = <0 55 4>;
 446                         clocks = <&ahb_gates 17>;
 447                         status = "disabled";
 448                 };
 449
 450                 mdio@01c0b080 {
 451                         compatible = "allwinner,sun4i-a10-mdio";
 452                         reg = <0x01c0b080 0x14>;
 453                         status = "disabled";
 454                         #address-cells = <1>;
 455                         #size-cells = <0>;
 456                 };
 457
 458                 usbphy: phy@01c13400 {
 459                         #phy-cells = <1>;
 460                         compatible = "allwinner,sun7i-a20-usb-phy";
 461                         reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
 462                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 463                         clocks = <&usb_clk 8>;
 464                         clock-names = "usb_phy";
 465                         resets = <&usb_clk 1>, <&usb_clk 2>;
 466                         reset-names = "usb1_reset", "usb2_reset";
 467                         status = "disabled";
 468                 };
 469
 470                 ehci0: usb@01c14000 {
 471                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 472                         reg = <0x01c14000 0x100>;
 473                         interrupts = <0 39 4>;
 474                         clocks = <&ahb_gates 1>;
 475                         phys = <&usbphy 1>;
 476                         phy-names = "usb";
 477                         status = "disabled";
 478                 };
 479
 480                 ohci0: usb@01c14400 {
 481                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 482                         reg = <0x01c14400 0x100>;
 483                         interrupts = <0 64 4>;
 484                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 485                         phys = <&usbphy 1>;
 486                         phy-names = "usb";
 487                         status = "disabled";
 488                 };
 489
 490                 spi2: spi@01c17000 {
 491                         compatible = "allwinner,sun4i-a10-spi";
 492                         reg = <0x01c17000 0x1000>;
 493                         interrupts = <0 12 4>;
 494                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 495                         clock-names = "ahb", "mod";
 496                         status = "disabled";
 497                         #address-cells = <1>;
 498                         #size-cells = <0>;
 499                 };
 500
 501                 ahci: sata@01c18000 {
 502                         compatible = "allwinner,sun4i-a10-ahci";
 503                         reg = <0x01c18000 0x1000>;
 504                         interrupts = <0 56 4>;
 505                         clocks = <&pll6 0>, <&ahb_gates 25>;
 506                         status = "disabled";
 507                 };
 508
 509                 ehci1: usb@01c1c000 {
 510                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 511                         reg = <0x01c1c000 0x100>;
 512                         interrupts = <0 40 4>;
 513                         clocks = <&ahb_gates 3>;
 514                         phys = <&usbphy 2>;
 515                         phy-names = "usb";
 516                         status = "disabled";
 517                 };
 518
 519                 ohci1: usb@01c1c400 {
 520                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 521                         reg = <0x01c1c400 0x100>;
 522                         interrupts = <0 65 4>;
 523                         clocks = <&usb_clk 7>, <&ahb_gates 4>;
 524                         phys = <&usbphy 2>;
 525                         phy-names = "usb";
 526                         status = "disabled";
 527                 };
 528
 529                 spi3: spi@01c1f000 {
 530                         compatible = "allwinner,sun4i-a10-spi";
 531                         reg = <0x01c1f000 0x1000>;
 532                         interrupts = <0 50 4>;
 533                         clocks = <&ahb_gates 23>, <&spi3_clk>;
 534                         clock-names = "ahb", "mod";
 535                         status = "disabled";
 536                         #address-cells = <1>;
 537                         #size-cells = <0>;
 538                 };
 539
 540                 pio: pinctrl@01c20800 {
 541                         compatible = "allwinner,sun7i-a20-pinctrl";
 542                         reg = <0x01c20800 0x400>;
 543                         interrupts = <0 28 4>;
 544                         clocks = <&apb0_gates 5>;
 545                         gpio-controller;
 546                         interrupt-controller;
 547                         #address-cells = <1>;
 548                         #size-cells = <0>;
 549                         #gpio-cells = <3>;
 550
 551                         uart0_pins_a: uart0@0 {
 552                                 allwinner,pins = "PB22", "PB23";
 553                                 allwinner,function = "uart0";
 554                                 allwinner,drive = <0>;
 555                                 allwinner,pull = <0>;
 556                         };
 557
 558                         uart2_pins_a: uart2@0 {
 559                                 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
 560                                 allwinner,function = "uart2";
 561                                 allwinner,drive = <0>;
 562                                 allwinner,pull = <0>;
 563                         };
 564
 565                         uart6_pins_a: uart6@0 {
 566                                 allwinner,pins = "PI12", "PI13";
 567                                 allwinner,function = "uart6";
 568                                 allwinner,drive = <0>;
 569                                 allwinner,pull = <0>;
 570                         };
 571
 572                         uart7_pins_a: uart7@0 {
 573                                 allwinner,pins = "PI20", "PI21";
 574                                 allwinner,function = "uart7";
 575                                 allwinner,drive = <0>;
 576                                 allwinner,pull = <0>;
 577                         };
 578
 579                         i2c0_pins_a: i2c0@0 {
 580                                 allwinner,pins = "PB0", "PB1";
 581                                 allwinner,function = "i2c0";
 582                                 allwinner,drive = <0>;
 583                                 allwinner,pull = <0>;
 584                         };
 585
 586                         i2c1_pins_a: i2c1@0 {
 587                                 allwinner,pins = "PB18", "PB19";
 588                                 allwinner,function = "i2c1";
 589                                 allwinner,drive = <0>;
 590                                 allwinner,pull = <0>;
 591                         };
 592
 593                         i2c2_pins_a: i2c2@0 {
 594                                 allwinner,pins = "PB20", "PB21";
 595                                 allwinner,function = "i2c2";
 596                                 allwinner,drive = <0>;
 597                                 allwinner,pull = <0>;
 598                         };
 599
 600                         emac_pins_a: emac0@0 {
 601                                 allwinner,pins = "PA0", "PA1", "PA2",
 602                                                 "PA3", "PA4", "PA5", "PA6",
 603                                                 "PA7", "PA8", "PA9", "PA10",
 604                                                 "PA11", "PA12", "PA13", "PA14",
 605                                                 "PA15", "PA16";
 606                                 allwinner,function = "emac";
 607                                 allwinner,drive = <0>;
 608                                 allwinner,pull = <0>;
 609                         };
 610
 611                         clk_out_a_pins_a: clk_out_a@0 {
 612                                 allwinner,pins = "PI12";
 613                                 allwinner,function = "clk_out_a";
 614                                 allwinner,drive = <0>;
 615                                 allwinner,pull = <0>;
 616                         };
 617
 618                         clk_out_b_pins_a: clk_out_b@0 {
 619                                 allwinner,pins = "PI13";
 620                                 allwinner,function = "clk_out_b";
 621                                 allwinner,drive = <0>;
 622                                 allwinner,pull = <0>;
 623                         };
 624
 625                         gmac_pins_mii_a: gmac_mii@0 {
 626                                 allwinner,pins = "PA0", "PA1", "PA2",
 627                                                 "PA3", "PA4", "PA5", "PA6",
 628                                                 "PA7", "PA8", "PA9", "PA10",
 629                                                 "PA11", "PA12", "PA13", "PA14",
 630                                                 "PA15", "PA16";
 631                                 allwinner,function = "gmac";
 632                                 allwinner,drive = <0>;
 633                                 allwinner,pull = <0>;
 634                         };
 635
 636                         gmac_pins_rgmii_a: gmac_rgmii@0 {
 637                                 allwinner,pins = "PA0", "PA1", "PA2",
 638                                                 "PA3", "PA4", "PA5", "PA6",
 639                                                 "PA7", "PA8", "PA10",
 640                                                 "PA11", "PA12", "PA13",
 641                                                 "PA15", "PA16";
 642                                 allwinner,function = "gmac";
 643                                 /*
 644                                  * data lines in RGMII mode use DDR mode
 645                                  * and need a higher signal drive strength
 646                                  */
 647                                 allwinner,drive = <3>;
 648                                 allwinner,pull = <0>;
 649                         };
 650
 651                         spi1_pins_a: spi1@0 {
 652                                 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
 653                                 allwinner,function = "spi1";
 654                                 allwinner,drive = <0>;
 655                                 allwinner,pull = <0>;
 656                         };
 657
 658                         spi2_pins_a: spi2@0 {
 659                                 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
 660                                 allwinner,function = "spi2";
 661                                 allwinner,drive = <0>;
 662                                 allwinner,pull = <0>;
 663                         };
 664                 };
 665
 666                 timer@01c20c00 {
 667                         compatible = "allwinner,sun4i-a10-timer";
 668                         reg = <0x01c20c00 0x90>;
 669                         interrupts = <0 22 4>,
 670                                      <0 23 4>,
 671                                      <0 24 4>,
 672                                      <0 25 4>,
 673                                      <0 67 4>,
 674                                      <0 68 4>;
 675                         clocks = <&osc24M>;
 676                 };
 677
 678                 wdt: watchdog@01c20c90 {
 679                         compatible = "allwinner,sun4i-a10-wdt";
 680                         reg = <0x01c20c90 0x10>;
 681                 };
 682
 683                 rtc: rtc@01c20d00 {
 684                         compatible = "allwinner,sun7i-a20-rtc";
 685                         reg = <0x01c20d00 0x20>;
 686                         interrupts = <0 24 4>;
 687                 };
 688
 689                 sid: eeprom@01c23800 {
 690                         compatible = "allwinner,sun7i-a20-sid";
 691                         reg = <0x01c23800 0x200>;
 692                 };
 693
 694                 rtp: rtp@01c25000 {
 695                         compatible = "allwinner,sun4i-a10-ts";
 696                         reg = <0x01c25000 0x100>;
 697                         interrupts = <0 29 4>;
 698                 };
 699
 700                 uart0: serial@01c28000 {
 701                         compatible = "snps,dw-apb-uart";
 702                         reg = <0x01c28000 0x400>;
 703                         interrupts = <0 1 4>;
 704                         reg-shift = <2>;
 705                         reg-io-width = <4>;
 706                         clocks = <&apb1_gates 16>;
 707                         status = "disabled";
 708                 };
 709
 710                 uart1: serial@01c28400 {
 711                         compatible = "snps,dw-apb-uart";
 712                         reg = <0x01c28400 0x400>;
 713                         interrupts = <0 2 4>;
 714                         reg-shift = <2>;
 715                         reg-io-width = <4>;
 716                         clocks = <&apb1_gates 17>;
 717                         status = "disabled";
 718                 };
 719
 720                 uart2: serial@01c28800 {
 721                         compatible = "snps,dw-apb-uart";
 722                         reg = <0x01c28800 0x400>;
 723                         interrupts = <0 3 4>;
 724                         reg-shift = <2>;
 725                         reg-io-width = <4>;
 726                         clocks = <&apb1_gates 18>;
 727                         status = "disabled";
 728                 };
 729
 730                 uart3: serial@01c28c00 {
 731                         compatible = "snps,dw-apb-uart";
 732                         reg = <0x01c28c00 0x400>;
 733                         interrupts = <0 4 4>;
 734                         reg-shift = <2>;
 735                         reg-io-width = <4>;
 736                         clocks = <&apb1_gates 19>;
 737                         status = "disabled";
 738                 };
 739
 740                 uart4: serial@01c29000 {
 741                         compatible = "snps,dw-apb-uart";
 742                         reg = <0x01c29000 0x400>;
 743                         interrupts = <0 17 4>;
 744                         reg-shift = <2>;
 745                         reg-io-width = <4>;
 746                         clocks = <&apb1_gates 20>;
 747                         status = "disabled";
 748                 };
 749
 750                 uart5: serial@01c29400 {
 751                         compatible = "snps,dw-apb-uart";
 752                         reg = <0x01c29400 0x400>;
 753                         interrupts = <0 18 4>;
 754                         reg-shift = <2>;
 755                         reg-io-width = <4>;
 756                         clocks = <&apb1_gates 21>;
 757                         status = "disabled";
 758                 };
 759
 760                 uart6: serial@01c29800 {
 761                         compatible = "snps,dw-apb-uart";
 762                         reg = <0x01c29800 0x400>;
 763                         interrupts = <0 19 4>;
 764                         reg-shift = <2>;
 765                         reg-io-width = <4>;
 766                         clocks = <&apb1_gates 22>;
 767                         status = "disabled";
 768                 };
 769
 770                 uart7: serial@01c29c00 {
 771                         compatible = "snps,dw-apb-uart";
 772                         reg = <0x01c29c00 0x400>;
 773                         interrupts = <0 20 4>;
 774                         reg-shift = <2>;
 775                         reg-io-width = <4>;
 776                         clocks = <&apb1_gates 23>;
 777                         status = "disabled";
 778                 };
 779
 780                 i2c0: i2c@01c2ac00 {
 781                         compatible = "allwinner,sun4i-i2c";
 782                         reg = <0x01c2ac00 0x400>;
 783                         interrupts = <0 7 4>;
 784                         clocks = <&apb1_gates 0>;
 785                         clock-frequency = <100000>;
 786                         status = "disabled";
 787                 };
 788
 789                 i2c1: i2c@01c2b000 {
 790                         compatible = "allwinner,sun4i-i2c";
 791                         reg = <0x01c2b000 0x400>;
 792                         interrupts = <0 8 4>;
 793                         clocks = <&apb1_gates 1>;
 794                         clock-frequency = <100000>;
 795                         status = "disabled";
 796                 };
 797
 798                 i2c2: i2c@01c2b400 {
 799                         compatible = "allwinner,sun4i-i2c";
 800                         reg = <0x01c2b400 0x400>;
 801                         interrupts = <0 9 4>;
 802                         clocks = <&apb1_gates 2>;
 803                         clock-frequency = <100000>;
 804                         status = "disabled";
 805                 };
 806
 807                 i2c3: i2c@01c2b800 {
 808                         compatible = "allwinner,sun4i-i2c";
 809                         reg = <0x01c2b800 0x400>;
 810                         interrupts = <0 88 4>;
 811                         clocks = <&apb1_gates 3>;
 812                         clock-frequency = <100000>;
 813                         status = "disabled";
 814                 };
 815
 816                 i2c4: i2c@01c2c000 {
 817                         compatible = "allwinner,sun4i-i2c";
 818                         reg = <0x01c2c000 0x400>;
 819                         interrupts = <0 89 4>;
 820                         clocks = <&apb1_gates 15>;
 821                         clock-frequency = <100000>;
 822                         status = "disabled";
 823                 };
 824
 825                 gmac: ethernet@01c50000 {
 826                         compatible = "allwinner,sun7i-a20-gmac";
 827                         reg = <0x01c50000 0x10000>;
 828                         interrupts = <0 85 4>;
 829                         interrupt-names = "macirq";
 830                         clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
 831                         clock-names = "stmmaceth", "allwinner_gmac_tx";
 832                         snps,pbl = <2>;
 833                         snps,fixed-burst;
 834                         snps,force_sf_dma_mode;
 835                         status = "disabled";
 836                         #address-cells = <1>;
 837                         #size-cells = <0>;
 838                 };
 839
 840                 hstimer@01c60000 {
 841                         compatible = "allwinner,sun7i-a20-hstimer";
 842                         reg = <0x01c60000 0x1000>;
 843                         interrupts = <0 81 4>,
 844                                      <0 82 4>,
 845                                      <0 83 4>,
 846                                      <0 84 4>;
 847                         clocks = <&ahb_gates 28>;
 848                 };
 849
 850                 gic: interrupt-controller@01c81000 {
 851                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 852                         reg = <0x01c81000 0x1000>,
 853                               <0x01c82000 0x1000>,
 854                               <0x01c84000 0x2000>,
 855                               <0x01c86000 0x2000>;
 856                         interrupt-controller;
 857                         #interrupt-cells = <3>;
 858                         interrupts = <1 9 0xf04>;
 859                 };
 860         };
 861 };