arch/arm/boot/dts/sun7i-a20.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&gic>;
  18
  19         aliases {
  20                 ethernet0 = &gmac;
  21                 serial0 = &uart0;
  22                 serial1 = &uart1;
  23                 serial2 = &uart2;
  24                 serial3 = &uart3;
  25                 serial4 = &uart4;
  26                 serial5 = &uart5;
  27                 serial6 = &uart6;
  28                 serial7 = &uart7;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 cpu@0 {
  36                         compatible = "arm,cortex-a7";
  37                         device_type = "cpu";
  38                         reg = <0>;
  39                 };
  40
  41                 cpu@1 {
  42                         compatible = "arm,cortex-a7";
  43                         device_type = "cpu";
  44                         reg = <1>;
  45                 };
  46         };
  47
  48         memory {
  49                 reg = <0x40000000 0x80000000>;
  50         };
  51
  52         timer {
  53                 compatible = "arm,armv7-timer";
  54                 interrupts = <1 13 0xf08>,
  55                              <1 14 0xf08>,
  56                              <1 11 0xf08>,
  57                              <1 10 0xf08>;
  58         };
  59
  60         pmu {
  61                 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
  62                 interrupts = <0 120 4>,
  63                              <0 121 4>;
  64         };
  65
  66         clocks {
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69                 ranges;
  70
  71                 osc24M: clk@01c20050 {
  72                         #clock-cells = <0>;
  73                         compatible = "allwinner,sun4i-a10-osc-clk";
  74                         reg = <0x01c20050 0x4>;
  75                         clock-frequency = <24000000>;
  76                         clock-output-names = "osc24M";
  77                 };
  78
  79                 osc32k: clk@0 {
  80                         #clock-cells = <0>;
  81                         compatible = "fixed-clock";
  82                         clock-frequency = <32768>;
  83                         clock-output-names = "osc32k";
  84                 };
  85
  86                 pll1: clk@01c20000 {
  87                         #clock-cells = <0>;
  88                         compatible = "allwinner,sun4i-a10-pll1-clk";
  89                         reg = <0x01c20000 0x4>;
  90                         clocks = <&osc24M>;
  91                         clock-output-names = "pll1";
  92                 };
  93
  94                 pll4: clk@01c20018 {
  95                         #clock-cells = <0>;
  96                         compatible = "allwinner,sun4i-a10-pll1-clk";
  97                         reg = <0x01c20018 0x4>;
  98                         clocks = <&osc24M>;
  99                         clock-output-names = "pll4";
 100                 };
 101
 102                 pll5: clk@01c20020 {
 103                         #clock-cells = <1>;
 104                         compatible = "allwinner,sun4i-a10-pll5-clk";
 105                         reg = <0x01c20020 0x4>;
 106                         clocks = <&osc24M>;
 107                         clock-output-names = "pll5_ddr", "pll5_other";
 108                 };
 109
 110                 pll6: clk@01c20028 {
 111                         #clock-cells = <1>;
 112                         compatible = "allwinner,sun4i-a10-pll6-clk";
 113                         reg = <0x01c20028 0x4>;
 114                         clocks = <&osc24M>;
 115                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 116                 };
 117
 118                 cpu: cpu@01c20054 {
 119                         #clock-cells = <0>;
 120                         compatible = "allwinner,sun4i-a10-cpu-clk";
 121                         reg = <0x01c20054 0x4>;
 122                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
 123                         clock-output-names = "cpu";
 124                 };
 125
 126                 axi: axi@01c20054 {
 127                         #clock-cells = <0>;
 128                         compatible = "allwinner,sun4i-a10-axi-clk";
 129                         reg = <0x01c20054 0x4>;
 130                         clocks = <&cpu>;
 131                         clock-output-names = "axi";
 132                 };
 133
 134                 ahb: ahb@01c20054 {
 135                         #clock-cells = <0>;
 136                         compatible = "allwinner,sun4i-a10-ahb-clk";
 137                         reg = <0x01c20054 0x4>;
 138                         clocks = <&axi>;
 139                         clock-output-names = "ahb";
 140                 };
 141
 142                 ahb_gates: clk@01c20060 {
 143                         #clock-cells = <1>;
 144                         compatible = "allwinner,sun7i-a20-ahb-gates-clk";
 145                         reg = <0x01c20060 0x8>;
 146                         clocks = <&ahb>;
 147                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 148                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
 149                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 150                                 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
 151                                 "ahb_nand", "ahb_sdram", "ahb_ace",
 152                                 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
 153                                 "ahb_spi2", "ahb_spi3", "ahb_sata",
 154                                 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
 155                                 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
 156                                 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
 157                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 158                                 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
 159                                 "ahb_mali";
 160                 };
 161
 162                 apb0: apb0@01c20054 {
 163                         #clock-cells = <0>;
 164                         compatible = "allwinner,sun4i-a10-apb0-clk";
 165                         reg = <0x01c20054 0x4>;
 166                         clocks = <&ahb>;
 167                         clock-output-names = "apb0";
 168                 };
 169
 170                 apb0_gates: clk@01c20068 {
 171                         #clock-cells = <1>;
 172                         compatible = "allwinner,sun7i-a20-apb0-gates-clk";
 173                         reg = <0x01c20068 0x4>;
 174                         clocks = <&apb0>;
 175                         clock-output-names = "apb0_codec", "apb0_spdif",
 176                                 "apb0_ac97", "apb0_iis0", "apb0_iis1",
 177                                 "apb0_pio", "apb0_ir0", "apb0_ir1",
 178                                 "apb0_iis2", "apb0_keypad";
 179                 };
 180
 181                 apb1_mux: apb1_mux@01c20058 {
 182                         #clock-cells = <0>;
 183                         compatible = "allwinner,sun4i-a10-apb1-mux-clk";
 184                         reg = <0x01c20058 0x4>;
 185                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 186                         clock-output-names = "apb1_mux";
 187                 };
 188
 189                 apb1: apb1@01c20058 {
 190                         #clock-cells = <0>;
 191                         compatible = "allwinner,sun4i-a10-apb1-clk";
 192                         reg = <0x01c20058 0x4>;
 193                         clocks = <&apb1_mux>;
 194                         clock-output-names = "apb1";
 195                 };
 196
 197                 apb1_gates: clk@01c2006c {
 198                         #clock-cells = <1>;
 199                         compatible = "allwinner,sun7i-a20-apb1-gates-clk";
 200                         reg = <0x01c2006c 0x4>;
 201                         clocks = <&apb1>;
 202                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 203                                 "apb1_i2c2", "apb1_i2c3", "apb1_can",
 204                                 "apb1_scr", "apb1_ps20", "apb1_ps21",
 205                                 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
 206                                 "apb1_uart2", "apb1_uart3", "apb1_uart4",
 207                                 "apb1_uart5", "apb1_uart6", "apb1_uart7";
 208                 };
 209
 210                 nand_clk: clk@01c20080 {
 211                         #clock-cells = <0>;
 212                         compatible = "allwinner,sun4i-a10-mod0-clk";
 213                         reg = <0x01c20080 0x4>;
 214                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 215                         clock-output-names = "nand";
 216                 };
 217
 218                 ms_clk: clk@01c20084 {
 219                         #clock-cells = <0>;
 220                         compatible = "allwinner,sun4i-a10-mod0-clk";
 221                         reg = <0x01c20084 0x4>;
 222                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 223                         clock-output-names = "ms";
 224                 };
 225
 226                 mmc0_clk: clk@01c20088 {
 227                         #clock-cells = <0>;
 228                         compatible = "allwinner,sun4i-a10-mod0-clk";
 229                         reg = <0x01c20088 0x4>;
 230                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 231                         clock-output-names = "mmc0";
 232                 };
 233
 234                 mmc1_clk: clk@01c2008c {
 235                         #clock-cells = <0>;
 236                         compatible = "allwinner,sun4i-a10-mod0-clk";
 237                         reg = <0x01c2008c 0x4>;
 238                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 239                         clock-output-names = "mmc1";
 240                 };
 241
 242                 mmc2_clk: clk@01c20090 {
 243                         #clock-cells = <0>;
 244                         compatible = "allwinner,sun4i-a10-mod0-clk";
 245                         reg = <0x01c20090 0x4>;
 246                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 247                         clock-output-names = "mmc2";
 248                 };
 249
 250                 mmc3_clk: clk@01c20094 {
 251                         #clock-cells = <0>;
 252                         compatible = "allwinner,sun4i-a10-mod0-clk";
 253                         reg = <0x01c20094 0x4>;
 254                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 255                         clock-output-names = "mmc3";
 256                 };
 257
 258                 ts_clk: clk@01c20098 {
 259                         #clock-cells = <0>;
 260                         compatible = "allwinner,sun4i-a10-mod0-clk";
 261                         reg = <0x01c20098 0x4>;
 262                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 263                         clock-output-names = "ts";
 264                 };
 265
 266                 ss_clk: clk@01c2009c {
 267                         #clock-cells = <0>;
 268                         compatible = "allwinner,sun4i-a10-mod0-clk";
 269                         reg = <0x01c2009c 0x4>;
 270                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 271                         clock-output-names = "ss";
 272                 };
 273
 274                 spi0_clk: clk@01c200a0 {
 275                         #clock-cells = <0>;
 276                         compatible = "allwinner,sun4i-a10-mod0-clk";
 277                         reg = <0x01c200a0 0x4>;
 278                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 279                         clock-output-names = "spi0";
 280                 };
 281
 282                 spi1_clk: clk@01c200a4 {
 283                         #clock-cells = <0>;
 284                         compatible = "allwinner,sun4i-a10-mod0-clk";
 285                         reg = <0x01c200a4 0x4>;
 286                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 287                         clock-output-names = "spi1";
 288                 };
 289
 290                 spi2_clk: clk@01c200a8 {
 291                         #clock-cells = <0>;
 292                         compatible = "allwinner,sun4i-a10-mod0-clk";
 293                         reg = <0x01c200a8 0x4>;
 294                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 295                         clock-output-names = "spi2";
 296                 };
 297
 298                 pata_clk: clk@01c200ac {
 299                         #clock-cells = <0>;
 300                         compatible = "allwinner,sun4i-a10-mod0-clk";
 301                         reg = <0x01c200ac 0x4>;
 302                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 303                         clock-output-names = "pata";
 304                 };
 305
 306                 ir0_clk: clk@01c200b0 {
 307                         #clock-cells = <0>;
 308                         compatible = "allwinner,sun4i-a10-mod0-clk";
 309                         reg = <0x01c200b0 0x4>;
 310                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 311                         clock-output-names = "ir0";
 312                 };
 313
 314                 ir1_clk: clk@01c200b4 {
 315                         #clock-cells = <0>;
 316                         compatible = "allwinner,sun4i-a10-mod0-clk";
 317                         reg = <0x01c200b4 0x4>;
 318                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 319                         clock-output-names = "ir1";
 320                 };
 321
 322                 usb_clk: clk@01c200cc {
 323                         #clock-cells = <1>;
 324                         #reset-cells = <1>;
 325                         compatible = "allwinner,sun4i-a10-usb-clk";
 326                         reg = <0x01c200cc 0x4>;
 327                         clocks = <&pll6 1>;
 328                         clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
 329                 };
 330
 331                 spi3_clk: clk@01c200d4 {
 332                         #clock-cells = <0>;
 333                         compatible = "allwinner,sun4i-a10-mod0-clk";
 334                         reg = <0x01c200d4 0x4>;
 335                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 336                         clock-output-names = "spi3";
 337                 };
 338
 339                 mbus_clk: clk@01c2015c {
 340                         #clock-cells = <0>;
 341                         compatible = "allwinner,sun4i-a10-mod0-clk";
 342                         reg = <0x01c2015c 0x4>;
 343                         clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
 344                         clock-output-names = "mbus";
 345                 };
 346
 347                 /*
 348                  * The following two are dummy clocks, placeholders used in the gmac_tx
 349                  * clock. The gmac driver will choose one parent depending on the PHY
 350                  * interface mode, using clk_set_rate auto-reparenting.
 351                  * The actual TX clock rate is not controlled by the gmac_tx clock.
 352                  */
 353                 mii_phy_tx_clk: clk@2 {
 354                         #clock-cells = <0>;
 355                         compatible = "fixed-clock";
 356                         clock-frequency = <25000000>;
 357                         clock-output-names = "mii_phy_tx";
 358                 };
 359
 360                 gmac_int_tx_clk: clk@3 {
 361                         #clock-cells = <0>;
 362                         compatible = "fixed-clock";
 363                         clock-frequency = <125000000>;
 364                         clock-output-names = "gmac_int_tx";
 365                 };
 366
 367                 gmac_tx_clk: clk@01c20164 {
 368                         #clock-cells = <0>;
 369                         compatible = "allwinner,sun7i-a20-gmac-clk";
 370                         reg = <0x01c20164 0x4>;
 371                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 372                         clock-output-names = "gmac_tx";
 373                 };
 374
 375                 /*
 376                  * Dummy clock used by output clocks
 377                  */
 378                 osc24M_32k: clk@1 {
 379                         #clock-cells = <0>;
 380                         compatible = "fixed-factor-clock";
 381                         clock-div = <750>;
 382                         clock-mult = <1>;
 383                         clocks = <&osc24M>;
 384                         clock-output-names = "osc24M_32k";
 385                 };
 386
 387                 clk_out_a: clk@01c201f0 {
 388                         #clock-cells = <0>;
 389                         compatible = "allwinner,sun7i-a20-out-clk";
 390                         reg = <0x01c201f0 0x4>;
 391                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 392                         clock-output-names = "clk_out_a";
 393                 };
 394
 395                 clk_out_b: clk@01c201f4 {
 396                         #clock-cells = <0>;
 397                         compatible = "allwinner,sun7i-a20-out-clk";
 398                         reg = <0x01c201f4 0x4>;
 399                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 400                         clock-output-names = "clk_out_b";
 401                 };
 402         };
 403
 404         soc@01c00000 {
 405                 compatible = "simple-bus";
 406                 #address-cells = <1>;
 407                 #size-cells = <1>;
 408                 ranges;
 409
 410                 nmi_intc: interrupt-controller@01c00030 {
 411                         compatible = "allwinner,sun7i-a20-sc-nmi";
 412                         interrupt-controller;
 413                         #interrupt-cells = <2>;
 414                         reg = <0x01c00030 0x0c>;
 415                         interrupts = <0 0 4>;
 416                 };
 417
 418                 spi0: spi@01c05000 {
 419                         compatible = "allwinner,sun4i-a10-spi";
 420                         reg = <0x01c05000 0x1000>;
 421                         interrupts = <0 10 4>;
 422                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 423                         clock-names = "ahb", "mod";
 424                         status = "disabled";
 425                         #address-cells = <1>;
 426                         #size-cells = <0>;
 427                 };
 428
 429                 spi1: spi@01c06000 {
 430                         compatible = "allwinner,sun4i-a10-spi";
 431                         reg = <0x01c06000 0x1000>;
 432                         interrupts = <0 11 4>;
 433                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 434                         clock-names = "ahb", "mod";
 435                         status = "disabled";
 436                         #address-cells = <1>;
 437                         #size-cells = <0>;
 438                 };
 439
 440                 emac: ethernet@01c0b000 {
 441                         compatible = "allwinner,sun4i-a10-emac";
 442                         reg = <0x01c0b000 0x1000>;
 443                         interrupts = <0 55 4>;
 444                         clocks = <&ahb_gates 17>;
 445                         status = "disabled";
 446                 };
 447
 448                 mdio@01c0b080 {
 449                         compatible = "allwinner,sun4i-a10-mdio";
 450                         reg = <0x01c0b080 0x14>;
 451                         status = "disabled";
 452                         #address-cells = <1>;
 453                         #size-cells = <0>;
 454                 };
 455
 456                 mmc0: mmc@01c0f000 {
 457                         compatible = "allwinner,sun5i-a13-mmc";
 458                         reg = <0x01c0f000 0x1000>;
 459                         clocks = <&ahb_gates 8>, <&mmc0_clk>;
 460                         clock-names = "ahb", "mmc";
 461                         interrupts = <0 32 4>;
 462                         status = "disabled";
 463                 };
 464
 465                 mmc1: mmc@01c10000 {
 466                         compatible = "allwinner,sun5i-a13-mmc";
 467                         reg = <0x01c10000 0x1000>;
 468                         clocks = <&ahb_gates 9>, <&mmc1_clk>;
 469                         clock-names = "ahb", "mmc";
 470                         interrupts = <0 33 4>;
 471                         status = "disabled";
 472                 };
 473
 474                 mmc2: mmc@01c11000 {
 475                         compatible = "allwinner,sun5i-a13-mmc";
 476                         reg = <0x01c11000 0x1000>;
 477                         clocks = <&ahb_gates 10>, <&mmc2_clk>;
 478                         clock-names = "ahb", "mmc";
 479                         interrupts = <0 34 4>;
 480                         status = "disabled";
 481                 };
 482
 483                 mmc3: mmc@01c12000 {
 484                         compatible = "allwinner,sun5i-a13-mmc";
 485                         reg = <0x01c12000 0x1000>;
 486                         clocks = <&ahb_gates 11>, <&mmc3_clk>;
 487                         clock-names = "ahb", "mmc";
 488                         interrupts = <0 35 4>;
 489                         status = "disabled";
 490                 };
 491
 492                 usbphy: phy@01c13400 {
 493                         #phy-cells = <1>;
 494                         compatible = "allwinner,sun7i-a20-usb-phy";
 495                         reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
 496                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 497                         clocks = <&usb_clk 8>;
 498                         clock-names = "usb_phy";
 499                         resets = <&usb_clk 1>, <&usb_clk 2>;
 500                         reset-names = "usb1_reset", "usb2_reset";
 501                         status = "disabled";
 502                 };
 503
 504                 ehci0: usb@01c14000 {
 505                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 506                         reg = <0x01c14000 0x100>;
 507                         interrupts = <0 39 4>;
 508                         clocks = <&ahb_gates 1>;
 509                         phys = <&usbphy 1>;
 510                         phy-names = "usb";
 511                         status = "disabled";
 512                 };
 513
 514                 ohci0: usb@01c14400 {
 515                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 516                         reg = <0x01c14400 0x100>;
 517                         interrupts = <0 64 4>;
 518                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 519                         phys = <&usbphy 1>;
 520                         phy-names = "usb";
 521                         status = "disabled";
 522                 };
 523
 524                 spi2: spi@01c17000 {
 525                         compatible = "allwinner,sun4i-a10-spi";
 526                         reg = <0x01c17000 0x1000>;
 527                         interrupts = <0 12 4>;
 528                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 529                         clock-names = "ahb", "mod";
 530                         status = "disabled";
 531                         #address-cells = <1>;
 532                         #size-cells = <0>;
 533                 };
 534
 535                 ahci: sata@01c18000 {
 536                         compatible = "allwinner,sun4i-a10-ahci";
 537                         reg = <0x01c18000 0x1000>;
 538                         interrupts = <0 56 4>;
 539                         clocks = <&pll6 0>, <&ahb_gates 25>;
 540                         status = "disabled";
 541                 };
 542
 543                 ehci1: usb@01c1c000 {
 544                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 545                         reg = <0x01c1c000 0x100>;
 546                         interrupts = <0 40 4>;
 547                         clocks = <&ahb_gates 3>;
 548                         phys = <&usbphy 2>;
 549                         phy-names = "usb";
 550                         status = "disabled";
 551                 };
 552
 553                 ohci1: usb@01c1c400 {
 554                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 555                         reg = <0x01c1c400 0x100>;
 556                         interrupts = <0 65 4>;
 557                         clocks = <&usb_clk 7>, <&ahb_gates 4>;
 558                         phys = <&usbphy 2>;
 559                         phy-names = "usb";
 560                         status = "disabled";
 561                 };
 562
 563                 spi3: spi@01c1f000 {
 564                         compatible = "allwinner,sun4i-a10-spi";
 565                         reg = <0x01c1f000 0x1000>;
 566                         interrupts = <0 50 4>;
 567                         clocks = <&ahb_gates 23>, <&spi3_clk>;
 568                         clock-names = "ahb", "mod";
 569                         status = "disabled";
 570                         #address-cells = <1>;
 571                         #size-cells = <0>;
 572                 };
 573
 574                 pio: pinctrl@01c20800 {
 575                         compatible = "allwinner,sun7i-a20-pinctrl";
 576                         reg = <0x01c20800 0x400>;
 577                         interrupts = <0 28 4>;
 578                         clocks = <&apb0_gates 5>;
 579                         gpio-controller;
 580                         interrupt-controller;
 581                         #address-cells = <1>;
 582                         #size-cells = <0>;
 583                         #gpio-cells = <3>;
 584
 585                         pwm0_pins_a: pwm0@0 {
 586                                 allwinner,pins = "PB2";
 587                                 allwinner,function = "pwm";
 588                                 allwinner,drive = <0>;
 589                                 allwinner,pull = <0>;
 590                         };
 591
 592                         pwm1_pins_a: pwm1@0 {
 593                                 allwinner,pins = "PI3";
 594                                 allwinner,function = "pwm";
 595                                 allwinner,drive = <0>;
 596                                 allwinner,pull = <0>;
 597                         };
 598
 599                         uart0_pins_a: uart0@0 {
 600                                 allwinner,pins = "PB22", "PB23";
 601                                 allwinner,function = "uart0";
 602                                 allwinner,drive = <0>;
 603                                 allwinner,pull = <0>;
 604                         };
 605
 606                         uart2_pins_a: uart2@0 {
 607                                 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
 608                                 allwinner,function = "uart2";
 609                                 allwinner,drive = <0>;
 610                                 allwinner,pull = <0>;
 611                         };
 612
 613                         uart6_pins_a: uart6@0 {
 614                                 allwinner,pins = "PI12", "PI13";
 615                                 allwinner,function = "uart6";
 616                                 allwinner,drive = <0>;
 617                                 allwinner,pull = <0>;
 618                         };
 619
 620                         uart7_pins_a: uart7@0 {
 621                                 allwinner,pins = "PI20", "PI21";
 622                                 allwinner,function = "uart7";
 623                                 allwinner,drive = <0>;
 624                                 allwinner,pull = <0>;
 625                         };
 626
 627                         i2c0_pins_a: i2c0@0 {
 628                                 allwinner,pins = "PB0", "PB1";
 629                                 allwinner,function = "i2c0";
 630                                 allwinner,drive = <0>;
 631                                 allwinner,pull = <0>;
 632                         };
 633
 634                         i2c1_pins_a: i2c1@0 {
 635                                 allwinner,pins = "PB18", "PB19";
 636                                 allwinner,function = "i2c1";
 637                                 allwinner,drive = <0>;
 638                                 allwinner,pull = <0>;
 639                         };
 640
 641                         i2c2_pins_a: i2c2@0 {
 642                                 allwinner,pins = "PB20", "PB21";
 643                                 allwinner,function = "i2c2";
 644                                 allwinner,drive = <0>;
 645                                 allwinner,pull = <0>;
 646                         };
 647
 648                         emac_pins_a: emac0@0 {
 649                                 allwinner,pins = "PA0", "PA1", "PA2",
 650                                                 "PA3", "PA4", "PA5", "PA6",
 651                                                 "PA7", "PA8", "PA9", "PA10",
 652                                                 "PA11", "PA12", "PA13", "PA14",
 653                                                 "PA15", "PA16";
 654                                 allwinner,function = "emac";
 655                                 allwinner,drive = <0>;
 656                                 allwinner,pull = <0>;
 657                         };
 658
 659                         clk_out_a_pins_a: clk_out_a@0 {
 660                                 allwinner,pins = "PI12";
 661                                 allwinner,function = "clk_out_a";
 662                                 allwinner,drive = <0>;
 663                                 allwinner,pull = <0>;
 664                         };
 665
 666                         clk_out_b_pins_a: clk_out_b@0 {
 667                                 allwinner,pins = "PI13";
 668                                 allwinner,function = "clk_out_b";
 669                                 allwinner,drive = <0>;
 670                                 allwinner,pull = <0>;
 671                         };
 672
 673                         gmac_pins_mii_a: gmac_mii@0 {
 674                                 allwinner,pins = "PA0", "PA1", "PA2",
 675                                                 "PA3", "PA4", "PA5", "PA6",
 676                                                 "PA7", "PA8", "PA9", "PA10",
 677                                                 "PA11", "PA12", "PA13", "PA14",
 678                                                 "PA15", "PA16";
 679                                 allwinner,function = "gmac";
 680                                 allwinner,drive = <0>;
 681                                 allwinner,pull = <0>;
 682                         };
 683
 684                         gmac_pins_rgmii_a: gmac_rgmii@0 {
 685                                 allwinner,pins = "PA0", "PA1", "PA2",
 686                                                 "PA3", "PA4", "PA5", "PA6",
 687                                                 "PA7", "PA8", "PA10",
 688                                                 "PA11", "PA12", "PA13",
 689                                                 "PA15", "PA16";
 690                                 allwinner,function = "gmac";
 691                                 /*
 692                                  * data lines in RGMII mode use DDR mode
 693                                  * and need a higher signal drive strength
 694                                  */
 695                                 allwinner,drive = <3>;
 696                                 allwinner,pull = <0>;
 697                         };
 698
 699                         spi1_pins_a: spi1@0 {
 700                                 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
 701                                 allwinner,function = "spi1";
 702                                 allwinner,drive = <0>;
 703                                 allwinner,pull = <0>;
 704                         };
 705
 706                         spi2_pins_a: spi2@0 {
 707                                 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
 708                                 allwinner,function = "spi2";
 709                                 allwinner,drive = <0>;
 710                                 allwinner,pull = <0>;
 711                         };
 712                 };
 713
 714                 timer@01c20c00 {
 715                         compatible = "allwinner,sun4i-a10-timer";
 716                         reg = <0x01c20c00 0x90>;
 717                         interrupts = <0 22 4>,
 718                                      <0 23 4>,
 719                                      <0 24 4>,
 720                                      <0 25 4>,
 721                                      <0 67 4>,
 722                                      <0 68 4>;
 723                         clocks = <&osc24M>;
 724                 };
 725
 726                 wdt: watchdog@01c20c90 {
 727                         compatible = "allwinner,sun4i-a10-wdt";
 728                         reg = <0x01c20c90 0x10>;
 729                 };
 730
 731                 rtc: rtc@01c20d00 {
 732                         compatible = "allwinner,sun7i-a20-rtc";
 733                         reg = <0x01c20d00 0x20>;
 734                         interrupts = <0 24 4>;
 735                 };
 736
 737                 pwm: pwm@01c20e00 {
 738                         compatible = "allwinner,sun7i-a20-pwm";
 739                         reg = <0x01c20e00 0xc>;
 740                         clocks = <&osc24M>;
 741                         #pwm-cells = <3>;
 742                         status = "disabled";
 743                 };
 744
 745                 sid: eeprom@01c23800 {
 746                         compatible = "allwinner,sun7i-a20-sid";
 747                         reg = <0x01c23800 0x200>;
 748                 };
 749
 750                 rtp: rtp@01c25000 {
 751                         compatible = "allwinner,sun4i-a10-ts";
 752                         reg = <0x01c25000 0x100>;
 753                         interrupts = <0 29 4>;
 754                 };
 755
 756                 uart0: serial@01c28000 {
 757                         compatible = "snps,dw-apb-uart";
 758                         reg = <0x01c28000 0x400>;
 759                         interrupts = <0 1 4>;
 760                         reg-shift = <2>;
 761                         reg-io-width = <4>;
 762                         clocks = <&apb1_gates 16>;
 763                         status = "disabled";
 764                 };
 765
 766                 uart1: serial@01c28400 {
 767                         compatible = "snps,dw-apb-uart";
 768                         reg = <0x01c28400 0x400>;
 769                         interrupts = <0 2 4>;
 770                         reg-shift = <2>;
 771                         reg-io-width = <4>;
 772                         clocks = <&apb1_gates 17>;
 773                         status = "disabled";
 774                 };
 775
 776                 uart2: serial@01c28800 {
 777                         compatible = "snps,dw-apb-uart";
 778                         reg = <0x01c28800 0x400>;
 779                         interrupts = <0 3 4>;
 780                         reg-shift = <2>;
 781                         reg-io-width = <4>;
 782                         clocks = <&apb1_gates 18>;
 783                         status = "disabled";
 784                 };
 785
 786                 uart3: serial@01c28c00 {
 787                         compatible = "snps,dw-apb-uart";
 788                         reg = <0x01c28c00 0x400>;
 789                         interrupts = <0 4 4>;
 790                         reg-shift = <2>;
 791                         reg-io-width = <4>;
 792                         clocks = <&apb1_gates 19>;
 793                         status = "disabled";
 794                 };
 795
 796                 uart4: serial@01c29000 {
 797                         compatible = "snps,dw-apb-uart";
 798                         reg = <0x01c29000 0x400>;
 799                         interrupts = <0 17 4>;
 800                         reg-shift = <2>;
 801                         reg-io-width = <4>;
 802                         clocks = <&apb1_gates 20>;
 803                         status = "disabled";
 804                 };
 805
 806                 uart5: serial@01c29400 {
 807                         compatible = "snps,dw-apb-uart";
 808                         reg = <0x01c29400 0x400>;
 809                         interrupts = <0 18 4>;
 810                         reg-shift = <2>;
 811                         reg-io-width = <4>;
 812                         clocks = <&apb1_gates 21>;
 813                         status = "disabled";
 814                 };
 815
 816                 uart6: serial@01c29800 {
 817                         compatible = "snps,dw-apb-uart";
 818                         reg = <0x01c29800 0x400>;
 819                         interrupts = <0 19 4>;
 820                         reg-shift = <2>;
 821                         reg-io-width = <4>;
 822                         clocks = <&apb1_gates 22>;
 823                         status = "disabled";
 824                 };
 825
 826                 uart7: serial@01c29c00 {
 827                         compatible = "snps,dw-apb-uart";
 828                         reg = <0x01c29c00 0x400>;
 829                         interrupts = <0 20 4>;
 830                         reg-shift = <2>;
 831                         reg-io-width = <4>;
 832                         clocks = <&apb1_gates 23>;
 833                         status = "disabled";
 834                 };
 835
 836                 i2c0: i2c@01c2ac00 {
 837                         compatible = "allwinner,sun4i-i2c";
 838                         reg = <0x01c2ac00 0x400>;
 839                         interrupts = <0 7 4>;
 840                         clocks = <&apb1_gates 0>;
 841                         clock-frequency = <100000>;
 842                         status = "disabled";
 843                         #address-cells = <1>;
 844                         #size-cells = <0>;
 845                 };
 846
 847                 i2c1: i2c@01c2b000 {
 848                         compatible = "allwinner,sun4i-i2c";
 849                         reg = <0x01c2b000 0x400>;
 850                         interrupts = <0 8 4>;
 851                         clocks = <&apb1_gates 1>;
 852                         clock-frequency = <100000>;
 853                         status = "disabled";
 854                         #address-cells = <1>;
 855                         #size-cells = <0>;
 856                 };
 857
 858                 i2c2: i2c@01c2b400 {
 859                         compatible = "allwinner,sun4i-i2c";
 860                         reg = <0x01c2b400 0x400>;
 861                         interrupts = <0 9 4>;
 862                         clocks = <&apb1_gates 2>;
 863                         clock-frequency = <100000>;
 864                         status = "disabled";
 865                         #address-cells = <1>;
 866                         #size-cells = <0>;
 867                 };
 868
 869                 i2c3: i2c@01c2b800 {
 870                         compatible = "allwinner,sun4i-i2c";
 871                         reg = <0x01c2b800 0x400>;
 872                         interrupts = <0 88 4>;
 873                         clocks = <&apb1_gates 3>;
 874                         clock-frequency = <100000>;
 875                         status = "disabled";
 876                         #address-cells = <1>;
 877                         #size-cells = <0>;
 878                 };
 879
 880                 i2c4: i2c@01c2bc00 {
 881                         compatible = "allwinner,sun4i-i2c";
 882                         reg = <0x01c2bc00 0x400>;
 883                         interrupts = <0 89 4>;
 884                         clocks = <&apb1_gates 15>;
 885                         clock-frequency = <100000>;
 886                         status = "disabled";
 887                         #address-cells = <1>;
 888                         #size-cells = <0>;
 889                 };
 890
 891                 gmac: ethernet@01c50000 {
 892                         compatible = "allwinner,sun7i-a20-gmac";
 893                         reg = <0x01c50000 0x10000>;
 894                         interrupts = <0 85 4>;
 895                         interrupt-names = "macirq";
 896                         clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
 897                         clock-names = "stmmaceth", "allwinner_gmac_tx";
 898                         snps,pbl = <2>;
 899                         snps,fixed-burst;
 900                         snps,force_sf_dma_mode;
 901                         status = "disabled";
 902                         #address-cells = <1>;
 903                         #size-cells = <0>;
 904                 };
 905
 906                 hstimer@01c60000 {
 907                         compatible = "allwinner,sun7i-a20-hstimer";
 908                         reg = <0x01c60000 0x1000>;
 909                         interrupts = <0 81 4>,
 910                                      <0 82 4>,
 911                                      <0 83 4>,
 912                                      <0 84 4>;
 913                         clocks = <&ahb_gates 28>;
 914                 };
 915
 916                 gic: interrupt-controller@01c81000 {
 917                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 918                         reg = <0x01c81000 0x1000>,
 919                               <0x01c82000 0x1000>,
 920                               <0x01c84000 0x2000>,
 921                               <0x01c86000 0x2000>;
 922                         interrupt-controller;
 923                         #interrupt-cells = <3>;
 924                         interrupts = <1 9 0xf04>;
 925                 };
 926         };
 927 };