arch/arm/boot/dts/sun7i-a20.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&gic>;
  18
  19         aliases {
  20                 ethernet0 = &emac;
  21                 serial0 = &uart0;
  22                 serial1 = &uart1;
  23                 serial2 = &uart2;
  24                 serial3 = &uart3;
  25                 serial4 = &uart4;
  26                 serial5 = &uart5;
  27                 serial6 = &uart6;
  28                 serial7 = &uart7;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 cpu@0 {
  36                         compatible = "arm,cortex-a7";
  37                         device_type = "cpu";
  38                         reg = <0>;
  39                 };
  40
  41                 cpu@1 {
  42                         compatible = "arm,cortex-a7";
  43                         device_type = "cpu";
  44                         reg = <1>;
  45                 };
  46         };
  47
  48         memory {
  49                 reg = <0x40000000 0x80000000>;
  50         };
  51
  52         clocks {
  53                 #address-cells = <1>;
  54                 #size-cells = <1>;
  55                 ranges;
  56
  57                 osc24M: clk@01c20050 {
  58                         #clock-cells = <0>;
  59                         compatible = "allwinner,sun4i-osc-clk";
  60                         reg = <0x01c20050 0x4>;
  61                         clock-frequency = <24000000>;
  62                         clock-output-names = "osc24M";
  63                 };
  64
  65                 osc32k: clk@0 {
  66                         #clock-cells = <0>;
  67                         compatible = "fixed-clock";
  68                         clock-frequency = <32768>;
  69                         clock-output-names = "osc32k";
  70                 };
  71
  72                 pll1: clk@01c20000 {
  73                         #clock-cells = <0>;
  74                         compatible = "allwinner,sun4i-pll1-clk";
  75                         reg = <0x01c20000 0x4>;
  76                         clocks = <&osc24M>;
  77                         clock-output-names = "pll1";
  78                 };
  79
  80                 pll4: clk@01c20018 {
  81                         #clock-cells = <0>;
  82                         compatible = "allwinner,sun4i-pll1-clk";
  83                         reg = <0x01c20018 0x4>;
  84                         clocks = <&osc24M>;
  85                         clock-output-names = "pll4";
  86                 };
  87
  88                 pll5: clk@01c20020 {
  89                         #clock-cells = <1>;
  90                         compatible = "allwinner,sun4i-pll5-clk";
  91                         reg = <0x01c20020 0x4>;
  92                         clocks = <&osc24M>;
  93                         clock-output-names = "pll5_ddr", "pll5_other";
  94                 };
  95
  96                 pll6: clk@01c20028 {
  97                         #clock-cells = <1>;
  98                         compatible = "allwinner,sun4i-pll6-clk";
  99                         reg = <0x01c20028 0x4>;
 100                         clocks = <&osc24M>;
 101                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 102                 };
 103
 104                 cpu: cpu@01c20054 {
 105                         #clock-cells = <0>;
 106                         compatible = "allwinner,sun4i-cpu-clk";
 107                         reg = <0x01c20054 0x4>;
 108                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
 109                         clock-output-names = "cpu";
 110                 };
 111
 112                 axi: axi@01c20054 {
 113                         #clock-cells = <0>;
 114                         compatible = "allwinner,sun4i-axi-clk";
 115                         reg = <0x01c20054 0x4>;
 116                         clocks = <&cpu>;
 117                         clock-output-names = "axi";
 118                 };
 119
 120                 ahb: ahb@01c20054 {
 121                         #clock-cells = <0>;
 122                         compatible = "allwinner,sun4i-ahb-clk";
 123                         reg = <0x01c20054 0x4>;
 124                         clocks = <&axi>;
 125                         clock-output-names = "ahb";
 126                 };
 127
 128                 ahb_gates: clk@01c20060 {
 129                         #clock-cells = <1>;
 130                         compatible = "allwinner,sun7i-a20-ahb-gates-clk";
 131                         reg = <0x01c20060 0x8>;
 132                         clocks = <&ahb>;
 133                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 134                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
 135                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 136                                 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
 137                                 "ahb_nand", "ahb_sdram", "ahb_ace",
 138                                 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
 139                                 "ahb_spi2", "ahb_spi3", "ahb_sata",
 140                                 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
 141                                 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
 142                                 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
 143                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 144                                 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
 145                                 "ahb_mali";
 146                 };
 147
 148                 apb0: apb0@01c20054 {
 149                         #clock-cells = <0>;
 150                         compatible = "allwinner,sun4i-apb0-clk";
 151                         reg = <0x01c20054 0x4>;
 152                         clocks = <&ahb>;
 153                         clock-output-names = "apb0";
 154                 };
 155
 156                 apb0_gates: clk@01c20068 {
 157                         #clock-cells = <1>;
 158                         compatible = "allwinner,sun7i-a20-apb0-gates-clk";
 159                         reg = <0x01c20068 0x4>;
 160                         clocks = <&apb0>;
 161                         clock-output-names = "apb0_codec", "apb0_spdif",
 162                                 "apb0_ac97", "apb0_iis0", "apb0_iis1",
 163                                 "apb0_pio", "apb0_ir0", "apb0_ir1",
 164                                 "apb0_iis2", "apb0_keypad";
 165                 };
 166
 167                 apb1_mux: apb1_mux@01c20058 {
 168                         #clock-cells = <0>;
 169                         compatible = "allwinner,sun4i-apb1-mux-clk";
 170                         reg = <0x01c20058 0x4>;
 171                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 172                         clock-output-names = "apb1_mux";
 173                 };
 174
 175                 apb1: apb1@01c20058 {
 176                         #clock-cells = <0>;
 177                         compatible = "allwinner,sun4i-apb1-clk";
 178                         reg = <0x01c20058 0x4>;
 179                         clocks = <&apb1_mux>;
 180                         clock-output-names = "apb1";
 181                 };
 182
 183                 apb1_gates: clk@01c2006c {
 184                         #clock-cells = <1>;
 185                         compatible = "allwinner,sun7i-a20-apb1-gates-clk";
 186                         reg = <0x01c2006c 0x4>;
 187                         clocks = <&apb1>;
 188                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 189                                 "apb1_i2c2", "apb1_i2c3", "apb1_can",
 190                                 "apb1_scr", "apb1_ps20", "apb1_ps21",
 191                                 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
 192                                 "apb1_uart2", "apb1_uart3", "apb1_uart4",
 193                                 "apb1_uart5", "apb1_uart6", "apb1_uart7";
 194                 };
 195
 196                 nand_clk: clk@01c20080 {
 197                         #clock-cells = <0>;
 198                         compatible = "allwinner,sun4i-mod0-clk";
 199                         reg = <0x01c20080 0x4>;
 200                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 201                         clock-output-names = "nand";
 202                 };
 203
 204                 ms_clk: clk@01c20084 {
 205                         #clock-cells = <0>;
 206                         compatible = "allwinner,sun4i-mod0-clk";
 207                         reg = <0x01c20084 0x4>;
 208                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 209                         clock-output-names = "ms";
 210                 };
 211
 212                 mmc0_clk: clk@01c20088 {
 213                         #clock-cells = <0>;
 214                         compatible = "allwinner,sun4i-mod0-clk";
 215                         reg = <0x01c20088 0x4>;
 216                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 217                         clock-output-names = "mmc0";
 218                 };
 219
 220                 mmc1_clk: clk@01c2008c {
 221                         #clock-cells = <0>;
 222                         compatible = "allwinner,sun4i-mod0-clk";
 223                         reg = <0x01c2008c 0x4>;
 224                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 225                         clock-output-names = "mmc1";
 226                 };
 227
 228                 mmc2_clk: clk@01c20090 {
 229                         #clock-cells = <0>;
 230                         compatible = "allwinner,sun4i-mod0-clk";
 231                         reg = <0x01c20090 0x4>;
 232                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 233                         clock-output-names = "mmc2";
 234                 };
 235
 236                 mmc3_clk: clk@01c20094 {
 237                         #clock-cells = <0>;
 238                         compatible = "allwinner,sun4i-mod0-clk";
 239                         reg = <0x01c20094 0x4>;
 240                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 241                         clock-output-names = "mmc3";
 242                 };
 243
 244                 ts_clk: clk@01c20098 {
 245                         #clock-cells = <0>;
 246                         compatible = "allwinner,sun4i-mod0-clk";
 247                         reg = <0x01c20098 0x4>;
 248                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 249                         clock-output-names = "ts";
 250                 };
 251
 252                 ss_clk: clk@01c2009c {
 253                         #clock-cells = <0>;
 254                         compatible = "allwinner,sun4i-mod0-clk";
 255                         reg = <0x01c2009c 0x4>;
 256                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 257                         clock-output-names = "ss";
 258                 };
 259
 260                 spi0_clk: clk@01c200a0 {
 261                         #clock-cells = <0>;
 262                         compatible = "allwinner,sun4i-mod0-clk";
 263                         reg = <0x01c200a0 0x4>;
 264                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 265                         clock-output-names = "spi0";
 266                 };
 267
 268                 spi1_clk: clk@01c200a4 {
 269                         #clock-cells = <0>;
 270                         compatible = "allwinner,sun4i-mod0-clk";
 271                         reg = <0x01c200a4 0x4>;
 272                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 273                         clock-output-names = "spi1";
 274                 };
 275
 276                 spi2_clk: clk@01c200a8 {
 277                         #clock-cells = <0>;
 278                         compatible = "allwinner,sun4i-mod0-clk";
 279                         reg = <0x01c200a8 0x4>;
 280                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 281                         clock-output-names = "spi2";
 282                 };
 283
 284                 pata_clk: clk@01c200ac {
 285                         #clock-cells = <0>;
 286                         compatible = "allwinner,sun4i-mod0-clk";
 287                         reg = <0x01c200ac 0x4>;
 288                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 289                         clock-output-names = "pata";
 290                 };
 291
 292                 ir0_clk: clk@01c200b0 {
 293                         #clock-cells = <0>;
 294                         compatible = "allwinner,sun4i-mod0-clk";
 295                         reg = <0x01c200b0 0x4>;
 296                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 297                         clock-output-names = "ir0";
 298                 };
 299
 300                 ir1_clk: clk@01c200b4 {
 301                         #clock-cells = <0>;
 302                         compatible = "allwinner,sun4i-mod0-clk";
 303                         reg = <0x01c200b4 0x4>;
 304                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 305                         clock-output-names = "ir1";
 306                 };
 307
 308                 spi3_clk: clk@01c200d4 {
 309                         #clock-cells = <0>;
 310                         compatible = "allwinner,sun4i-mod0-clk";
 311                         reg = <0x01c200d4 0x4>;
 312                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 313                         clock-output-names = "spi3";
 314                 };
 315
 316                 mbus_clk: clk@01c2015c {
 317                         #clock-cells = <0>;
 318                         compatible = "allwinner,sun4i-mod0-clk";
 319                         reg = <0x01c2015c 0x4>;
 320                         clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
 321                         clock-output-names = "mbus";
 322                 };
 323
 324                 /*
 325                  * The following two are dummy clocks, placeholders used in the gmac_tx
 326                  * clock. The gmac driver will choose one parent depending on the PHY
 327                  * interface mode, using clk_set_rate auto-reparenting.
 328                  * The actual TX clock rate is not controlled by the gmac_tx clock.
 329                  */
 330                 mii_phy_tx_clk: clk@2 {
 331                         #clock-cells = <0>;
 332                         compatible = "fixed-clock";
 333                         clock-frequency = <25000000>;
 334                         clock-output-names = "mii_phy_tx";
 335                 };
 336
 337                 gmac_int_tx_clk: clk@3 {
 338                         #clock-cells = <0>;
 339                         compatible = "fixed-clock";
 340                         clock-frequency = <125000000>;
 341                         clock-output-names = "gmac_int_tx";
 342                 };
 343
 344                 gmac_tx_clk: clk@01c20164 {
 345                         #clock-cells = <0>;
 346                         compatible = "allwinner,sun7i-a20-gmac-clk";
 347                         reg = <0x01c20164 0x4>;
 348                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 349                         clock-output-names = "gmac_tx";
 350                 };
 351
 352                 /*
 353                  * Dummy clock used by output clocks
 354                  */
 355                 osc24M_32k: clk@1 {
 356                         #clock-cells = <0>;
 357                         compatible = "fixed-factor-clock";
 358                         clock-div = <750>;
 359                         clock-mult = <1>;
 360                         clocks = <&osc24M>;
 361                         clock-output-names = "osc24M_32k";
 362                 };
 363
 364                 clk_out_a: clk@01c201f0 {
 365                         #clock-cells = <0>;
 366                         compatible = "allwinner,sun7i-a20-out-clk";
 367                         reg = <0x01c201f0 0x4>;
 368                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 369                         clock-output-names = "clk_out_a";
 370                 };
 371
 372                 clk_out_b: clk@01c201f4 {
 373                         #clock-cells = <0>;
 374                         compatible = "allwinner,sun7i-a20-out-clk";
 375                         reg = <0x01c201f4 0x4>;
 376                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 377                         clock-output-names = "clk_out_b";
 378                 };
 379         };
 380
 381         soc@01c00000 {
 382                 compatible = "simple-bus";
 383                 #address-cells = <1>;
 384                 #size-cells = <1>;
 385                 ranges;
 386
 387                 emac: ethernet@01c0b000 {
 388                         compatible = "allwinner,sun4i-emac";
 389                         reg = <0x01c0b000 0x1000>;
 390                         interrupts = <0 55 4>;
 391                         clocks = <&ahb_gates 17>;
 392                         status = "disabled";
 393                 };
 394
 395                 mdio@01c0b080 {
 396                         compatible = "allwinner,sun4i-mdio";
 397                         reg = <0x01c0b080 0x14>;
 398                         status = "disabled";
 399                         #address-cells = <1>;
 400                         #size-cells = <0>;
 401                 };
 402
 403                 pio: pinctrl@01c20800 {
 404                         compatible = "allwinner,sun7i-a20-pinctrl";
 405                         reg = <0x01c20800 0x400>;
 406                         interrupts = <0 28 4>;
 407                         clocks = <&apb0_gates 5>;
 408                         gpio-controller;
 409                         interrupt-controller;
 410                         #address-cells = <1>;
 411                         #size-cells = <0>;
 412                         #gpio-cells = <3>;
 413
 414                         uart0_pins_a: uart0@0 {
 415                                 allwinner,pins = "PB22", "PB23";
 416                                 allwinner,function = "uart0";
 417                                 allwinner,drive = <0>;
 418                                 allwinner,pull = <0>;
 419                         };
 420
 421                         uart2_pins_a: uart2@0 {
 422                                 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
 423                                 allwinner,function = "uart2";
 424                                 allwinner,drive = <0>;
 425                                 allwinner,pull = <0>;
 426                         };
 427
 428                         uart6_pins_a: uart6@0 {
 429                                 allwinner,pins = "PI12", "PI13";
 430                                 allwinner,function = "uart6";
 431                                 allwinner,drive = <0>;
 432                                 allwinner,pull = <0>;
 433                         };
 434
 435                         uart7_pins_a: uart7@0 {
 436                                 allwinner,pins = "PI20", "PI21";
 437                                 allwinner,function = "uart7";
 438                                 allwinner,drive = <0>;
 439                                 allwinner,pull = <0>;
 440                         };
 441
 442                         i2c0_pins_a: i2c0@0 {
 443                                 allwinner,pins = "PB0", "PB1";
 444                                 allwinner,function = "i2c0";
 445                                 allwinner,drive = <0>;
 446                                 allwinner,pull = <0>;
 447                         };
 448
 449                         i2c1_pins_a: i2c1@0 {
 450                                 allwinner,pins = "PB18", "PB19";
 451                                 allwinner,function = "i2c1";
 452                                 allwinner,drive = <0>;
 453                                 allwinner,pull = <0>;
 454                         };
 455
 456                         i2c2_pins_a: i2c2@0 {
 457                                 allwinner,pins = "PB20", "PB21";
 458                                 allwinner,function = "i2c2";
 459                                 allwinner,drive = <0>;
 460                                 allwinner,pull = <0>;
 461                         };
 462
 463                         emac_pins_a: emac0@0 {
 464                                 allwinner,pins = "PA0", "PA1", "PA2",
 465                                                 "PA3", "PA4", "PA5", "PA6",
 466                                                 "PA7", "PA8", "PA9", "PA10",
 467                                                 "PA11", "PA12", "PA13", "PA14",
 468                                                 "PA15", "PA16";
 469                                 allwinner,function = "emac";
 470                                 allwinner,drive = <0>;
 471                                 allwinner,pull = <0>;
 472                         };
 473
 474                         clk_out_a_pins_a: clk_out_a@0 {
 475                                 allwinner,pins = "PI12";
 476                                 allwinner,function = "clk_out_a";
 477                                 allwinner,drive = <0>;
 478                                 allwinner,pull = <0>;
 479                         };
 480
 481                         clk_out_b_pins_a: clk_out_b@0 {
 482                                 allwinner,pins = "PI13";
 483                                 allwinner,function = "clk_out_b";
 484                                 allwinner,drive = <0>;
 485                                 allwinner,pull = <0>;
 486                         };
 487                 };
 488
 489                 timer@01c20c00 {
 490                         compatible = "allwinner,sun4i-timer";
 491                         reg = <0x01c20c00 0x90>;
 492                         interrupts = <0 22 4>,
 493                                      <0 23 4>,
 494                                      <0 24 4>,
 495                                      <0 25 4>,
 496                                      <0 67 4>,
 497                                      <0 68 4>;
 498                         clocks = <&osc24M>;
 499                 };
 500
 501                 wdt: watchdog@01c20c90 {
 502                         compatible = "allwinner,sun4i-wdt";
 503                         reg = <0x01c20c90 0x10>;
 504                 };
 505
 506                 rtc: rtc@01c20d00 {
 507                         compatible = "allwinner,sun7i-a20-rtc";
 508                         reg = <0x01c20d00 0x20>;
 509                         interrupts = <0 24 1>;
 510                 };
 511
 512                 sid: eeprom@01c23800 {
 513                         compatible = "allwinner,sun7i-a20-sid";
 514                         reg = <0x01c23800 0x200>;
 515                 };
 516
 517                 rtp: rtp@01c25000 {
 518                         compatible = "allwinner,sun4i-ts";
 519                         reg = <0x01c25000 0x100>;
 520                         interrupts = <0 29 4>;
 521                 };
 522
 523                 uart0: serial@01c28000 {
 524                         compatible = "snps,dw-apb-uart";
 525                         reg = <0x01c28000 0x400>;
 526                         interrupts = <0 1 4>;
 527                         reg-shift = <2>;
 528                         reg-io-width = <4>;
 529                         clocks = <&apb1_gates 16>;
 530                         status = "disabled";
 531                 };
 532
 533                 uart1: serial@01c28400 {
 534                         compatible = "snps,dw-apb-uart";
 535                         reg = <0x01c28400 0x400>;
 536                         interrupts = <0 2 4>;
 537                         reg-shift = <2>;
 538                         reg-io-width = <4>;
 539                         clocks = <&apb1_gates 17>;
 540                         status = "disabled";
 541                 };
 542
 543                 uart2: serial@01c28800 {
 544                         compatible = "snps,dw-apb-uart";
 545                         reg = <0x01c28800 0x400>;
 546                         interrupts = <0 3 4>;
 547                         reg-shift = <2>;
 548                         reg-io-width = <4>;
 549                         clocks = <&apb1_gates 18>;
 550                         status = "disabled";
 551                 };
 552
 553                 uart3: serial@01c28c00 {
 554                         compatible = "snps,dw-apb-uart";
 555                         reg = <0x01c28c00 0x400>;
 556                         interrupts = <0 4 4>;
 557                         reg-shift = <2>;
 558                         reg-io-width = <4>;
 559                         clocks = <&apb1_gates 19>;
 560                         status = "disabled";
 561                 };
 562
 563                 uart4: serial@01c29000 {
 564                         compatible = "snps,dw-apb-uart";
 565                         reg = <0x01c29000 0x400>;
 566                         interrupts = <0 17 4>;
 567                         reg-shift = <2>;
 568                         reg-io-width = <4>;
 569                         clocks = <&apb1_gates 20>;
 570                         status = "disabled";
 571                 };
 572
 573                 uart5: serial@01c29400 {
 574                         compatible = "snps,dw-apb-uart";
 575                         reg = <0x01c29400 0x400>;
 576                         interrupts = <0 18 4>;
 577                         reg-shift = <2>;
 578                         reg-io-width = <4>;
 579                         clocks = <&apb1_gates 21>;
 580                         status = "disabled";
 581                 };
 582
 583                 uart6: serial@01c29800 {
 584                         compatible = "snps,dw-apb-uart";
 585                         reg = <0x01c29800 0x400>;
 586                         interrupts = <0 19 4>;
 587                         reg-shift = <2>;
 588                         reg-io-width = <4>;
 589                         clocks = <&apb1_gates 22>;
 590                         status = "disabled";
 591                 };
 592
 593                 uart7: serial@01c29c00 {
 594                         compatible = "snps,dw-apb-uart";
 595                         reg = <0x01c29c00 0x400>;
 596                         interrupts = <0 20 4>;
 597                         reg-shift = <2>;
 598                         reg-io-width = <4>;
 599                         clocks = <&apb1_gates 23>;
 600                         status = "disabled";
 601                 };
 602
 603                 i2c0: i2c@01c2ac00 {
 604                         compatible = "allwinner,sun4i-i2c";
 605                         reg = <0x01c2ac00 0x400>;
 606                         interrupts = <0 7 4>;
 607                         clocks = <&apb1_gates 0>;
 608                         clock-frequency = <100000>;
 609                         status = "disabled";
 610                 };
 611
 612                 i2c1: i2c@01c2b000 {
 613                         compatible = "allwinner,sun4i-i2c";
 614                         reg = <0x01c2b000 0x400>;
 615                         interrupts = <0 8 4>;
 616                         clocks = <&apb1_gates 1>;
 617                         clock-frequency = <100000>;
 618                         status = "disabled";
 619                 };
 620
 621                 i2c2: i2c@01c2b400 {
 622                         compatible = "allwinner,sun4i-i2c";
 623                         reg = <0x01c2b400 0x400>;
 624                         interrupts = <0 9 4>;
 625                         clocks = <&apb1_gates 2>;
 626                         clock-frequency = <100000>;
 627                         status = "disabled";
 628                 };
 629
 630                 i2c3: i2c@01c2b800 {
 631                         compatible = "allwinner,sun4i-i2c";
 632                         reg = <0x01c2b800 0x400>;
 633                         interrupts = <0 88 4>;
 634                         clocks = <&apb1_gates 3>;
 635                         clock-frequency = <100000>;
 636                         status = "disabled";
 637                 };
 638
 639                 i2c4: i2c@01c2bc00 {
 640                         compatible = "allwinner,sun4i-i2c";
 641                         reg = <0x01c2bc00 0x400>;
 642                         interrupts = <0 89 4>;
 643                         clocks = <&apb1_gates 15>;
 644                         clock-frequency = <100000>;
 645                         status = "disabled";
 646                 };
 647
 648                 hstimer@01c60000 {
 649                         compatible = "allwinner,sun7i-a20-hstimer";
 650                         reg = <0x01c60000 0x1000>;
 651                         interrupts = <0 81 1>,
 652                                      <0 82 1>,
 653                                      <0 83 1>,
 654                                      <0 84 1>;
 655                         clocks = <&ahb_gates 28>;
 656                 };
 657
 658                 gic: interrupt-controller@01c81000 {
 659                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 660                         reg = <0x01c81000 0x1000>,
 661                               <0x01c82000 0x1000>,
 662                               <0x01c84000 0x2000>,
 663                               <0x01c86000 0x2000>;
 664                         interrupt-controller;
 665                         #interrupt-cells = <3>;
 666                         interrupts = <1 9 0xf04>;
 667                 };
 668         };
 669 };