arch/arm/boot/dts/sun8i-a23.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  *     You should have received a copy of the GNU General Public
  22  *     License along with this file; if not, write to the Free
  23  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  24  *     MA 02110-1301 USA
  25  *
  26  * Or, alternatively,
  27  *
  28  *  b) Permission is hereby granted, free of charge, to any person
  29  *     obtaining a copy of this software and associated documentation
  30  *     files (the "Software"), to deal in the Software without
  31  *     restriction, including without limitation the rights to use,
  32  *     copy, modify, merge, publish, distribute, sublicense, and/or
  33  *     sell copies of the Software, and to permit persons to whom the
  34  *     Software is furnished to do so, subject to the following
  35  *     conditions:
  36  *
  37  *     The above copyright notice and this permission notice shall be
  38  *     included in all copies or substantial portions of the Software.
  39  *
  40  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  47  *     OTHER DEALINGS IN THE SOFTWARE.
  48  */
  49
  50 #include "skeleton.dtsi"
  51
  52 #include <dt-bindings/interrupt-controller/arm-gic.h>
  53
  54 #include <dt-bindings/pinctrl/sun4i-a10.h>
  55
  56 / {
  57         interrupt-parent = <&gic>;
  58
  59         chosen {
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62                 ranges;
  63
  64                 framebuffer@0 {
  65                         compatible = "allwinner,simple-framebuffer",
  66                                      "simple-framebuffer";
  67                         allwinner,pipeline = "de_be0-lcd0";
  68                         clocks = <&pll6 0>;
  69                         status = "disabled";
  70                 };
  71         };
  72
  73         timer {
  74                 compatible = "arm,armv7-timer";
  75                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  76                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  77                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  78                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  79                 clock-frequency = <24000000>;
  80                 arm,cpu-registers-not-fw-configured;
  81         };
  82
  83         cpus {
  84                 #address-cells = <1>;
  85                 #size-cells = <0>;
  86
  87                 cpu@0 {
  88                         compatible = "arm,cortex-a7";
  89                         device_type = "cpu";
  90                         reg = <0>;
  91                 };
  92
  93                 cpu@1 {
  94                         compatible = "arm,cortex-a7";
  95                         device_type = "cpu";
  96                         reg = <1>;
  97                 };
  98         };
  99
 100         memory {
 101                 reg = <0x40000000 0x40000000>;
 102         };
 103
 104         clocks {
 105                 #address-cells = <1>;
 106                 #size-cells = <1>;
 107                 ranges;
 108
 109                 osc24M: osc24M_clk {
 110                         #clock-cells = <0>;
 111                         compatible = "fixed-clock";
 112                         clock-frequency = <24000000>;
 113                         clock-output-names = "osc24M";
 114                 };
 115
 116                 osc32k: osc32k_clk {
 117                         #clock-cells = <0>;
 118                         compatible = "fixed-clock";
 119                         clock-frequency = <32768>;
 120                         clock-output-names = "osc32k";
 121                 };
 122
 123                 pll1: clk@01c20000 {
 124                         #clock-cells = <0>;
 125                         compatible = "allwinner,sun8i-a23-pll1-clk";
 126                         reg = <0x01c20000 0x4>;
 127                         clocks = <&osc24M>;
 128                         clock-output-names = "pll1";
 129                 };
 130
 131                 /* dummy clock until actually implemented */
 132                 pll5: pll5_clk {
 133                         #clock-cells = <0>;
 134                         compatible = "fixed-clock";
 135                         clock-frequency = <0>;
 136                         clock-output-names = "pll5";
 137                 };
 138
 139                 pll6: clk@01c20028 {
 140                         #clock-cells = <1>;
 141                         compatible = "allwinner,sun6i-a31-pll6-clk";
 142                         reg = <0x01c20028 0x4>;
 143                         clocks = <&osc24M>;
 144                         clock-output-names = "pll6", "pll6x2";
 145                 };
 146
 147                 cpu: cpu_clk@01c20050 {
 148                         #clock-cells = <0>;
 149                         compatible = "allwinner,sun4i-a10-cpu-clk";
 150                         reg = <0x01c20050 0x4>;
 151
 152                         /*
 153                          * PLL1 is listed twice here.
 154                          * While it looks suspicious, it's actually documented
 155                          * that way both in the datasheet and in the code from
 156                          * Allwinner.
 157                          */
 158                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 159                         clock-output-names = "cpu";
 160                 };
 161
 162                 axi: axi_clk@01c20050 {
 163                         #clock-cells = <0>;
 164                         compatible = "allwinner,sun8i-a23-axi-clk";
 165                         reg = <0x01c20050 0x4>;
 166                         clocks = <&cpu>;
 167                         clock-output-names = "axi";
 168                 };
 169
 170                 ahb1: ahb1_clk@01c20054 {
 171                         #clock-cells = <0>;
 172                         compatible = "allwinner,sun6i-a31-ahb1-clk";
 173                         reg = <0x01c20054 0x4>;
 174                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
 175                         clock-output-names = "ahb1";
 176                 };
 177
 178                 apb1: apb1_clk@01c20054 {
 179                         #clock-cells = <0>;
 180                         compatible = "allwinner,sun4i-a10-apb0-clk";
 181                         reg = <0x01c20054 0x4>;
 182                         clocks = <&ahb1>;
 183                         clock-output-names = "apb1";
 184                 };
 185
 186                 ahb1_gates: clk@01c20060 {
 187                         #clock-cells = <1>;
 188                         compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
 189                         reg = <0x01c20060 0x8>;
 190                         clocks = <&ahb1>;
 191                         clock-output-names = "ahb1_mipidsi", "ahb1_dma",
 192                                         "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
 193                                         "ahb1_nand", "ahb1_sdram",
 194                                         "ahb1_hstimer", "ahb1_spi0",
 195                                         "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
 196                                         "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
 197                                         "ahb1_csi", "ahb1_be",  "ahb1_fe",
 198                                         "ahb1_gpu", "ahb1_spinlock",
 199                                         "ahb1_drc";
 200                 };
 201
 202                 apb1_gates: clk@01c20068 {
 203                         #clock-cells = <1>;
 204                         compatible = "allwinner,sun8i-a23-apb1-gates-clk";
 205                         reg = <0x01c20068 0x4>;
 206                         clocks = <&apb1>;
 207                         clock-output-names = "apb1_codec", "apb1_pio",
 208                                         "apb1_daudio0", "apb1_daudio1";
 209                 };
 210
 211                 apb2: clk@01c20058 {
 212                         #clock-cells = <0>;
 213                         compatible = "allwinner,sun4i-a10-apb1-clk";
 214                         reg = <0x01c20058 0x4>;
 215                         clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
 216                         clock-output-names = "apb2";
 217                 };
 218
 219                 apb2_gates: clk@01c2006c {
 220                         #clock-cells = <1>;
 221                         compatible = "allwinner,sun8i-a23-apb2-gates-clk";
 222                         reg = <0x01c2006c 0x4>;
 223                         clocks = <&apb2>;
 224                         clock-output-names = "apb2_i2c0", "apb2_i2c1",
 225                                         "apb2_i2c2", "apb2_uart0",
 226                                         "apb2_uart1", "apb2_uart2",
 227                                         "apb2_uart3", "apb2_uart4";
 228                 };
 229
 230                 mmc0_clk: clk@01c20088 {
 231                         #clock-cells = <1>;
 232                         compatible = "allwinner,sun4i-a10-mmc-clk";
 233                         reg = <0x01c20088 0x4>;
 234                         clocks = <&osc24M>, <&pll6 0>;
 235                         clock-output-names = "mmc0",
 236                                              "mmc0_output",
 237                                              "mmc0_sample";
 238                 };
 239
 240                 mmc1_clk: clk@01c2008c {
 241                         #clock-cells = <1>;
 242                         compatible = "allwinner,sun4i-a10-mmc-clk";
 243                         reg = <0x01c2008c 0x4>;
 244                         clocks = <&osc24M>, <&pll6 0>;
 245                         clock-output-names = "mmc1",
 246                                              "mmc1_output",
 247                                              "mmc1_sample";
 248                 };
 249
 250                 mmc2_clk: clk@01c20090 {
 251                         #clock-cells = <1>;
 252                         compatible = "allwinner,sun4i-a10-mmc-clk";
 253                         reg = <0x01c20090 0x4>;
 254                         clocks = <&osc24M>, <&pll6 0>;
 255                         clock-output-names = "mmc2",
 256                                              "mmc2_output",
 257                                              "mmc2_sample";
 258                 };
 259
 260                 mbus_clk: clk@01c2015c {
 261                         #clock-cells = <0>;
 262                         compatible = "allwinner,sun8i-a23-mbus-clk";
 263                         reg = <0x01c2015c 0x4>;
 264                         clocks = <&osc24M>, <&pll6 1>, <&pll5>;
 265                         clock-output-names = "mbus";
 266                 };
 267         };
 268
 269         soc@01c00000 {
 270                 compatible = "simple-bus";
 271                 #address-cells = <1>;
 272                 #size-cells = <1>;
 273                 ranges;
 274
 275                 dma: dma-controller@01c02000 {
 276                         compatible = "allwinner,sun8i-a23-dma";
 277                         reg = <0x01c02000 0x1000>;
 278                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 279                         clocks = <&ahb1_gates 6>;
 280                         resets = <&ahb1_rst 6>;
 281                         #dma-cells = <1>;
 282                 };
 283
 284                 mmc0: mmc@01c0f000 {
 285                         compatible = "allwinner,sun5i-a13-mmc";
 286                         reg = <0x01c0f000 0x1000>;
 287                         clocks = <&ahb1_gates 8>,
 288                                  <&mmc0_clk 0>,
 289                                  <&mmc0_clk 1>,
 290                                  <&mmc0_clk 2>;
 291                         clock-names = "ahb",
 292                                       "mmc",
 293                                       "output",
 294                                       "sample";
 295                         resets = <&ahb1_rst 8>;
 296                         reset-names = "ahb";
 297                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 298                         status = "disabled";
 299                         #address-cells = <1>;
 300                         #size-cells = <0>;
 301                 };
 302
 303                 mmc1: mmc@01c10000 {
 304                         compatible = "allwinner,sun5i-a13-mmc";
 305                         reg = <0x01c10000 0x1000>;
 306                         clocks = <&ahb1_gates 9>,
 307                                  <&mmc1_clk 0>,
 308                                  <&mmc1_clk 1>,
 309                                  <&mmc1_clk 2>;
 310                         clock-names = "ahb",
 311                                       "mmc",
 312                                       "output",
 313                                       "sample";
 314                         resets = <&ahb1_rst 9>;
 315                         reset-names = "ahb";
 316                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 317                         status = "disabled";
 318                         #address-cells = <1>;
 319                         #size-cells = <0>;
 320                 };
 321
 322                 mmc2: mmc@01c11000 {
 323                         compatible = "allwinner,sun5i-a13-mmc";
 324                         reg = <0x01c11000 0x1000>;
 325                         clocks = <&ahb1_gates 10>,
 326                                  <&mmc2_clk 0>,
 327                                  <&mmc2_clk 1>,
 328                                  <&mmc2_clk 2>;
 329                         clock-names = "ahb",
 330                                       "mmc",
 331                                       "output",
 332                                       "sample";
 333                         resets = <&ahb1_rst 10>;
 334                         reset-names = "ahb";
 335                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 336                         status = "disabled";
 337                         #address-cells = <1>;
 338                         #size-cells = <0>;
 339                 };
 340
 341                 pio: pinctrl@01c20800 {
 342                         compatible = "allwinner,sun8i-a23-pinctrl";
 343                         reg = <0x01c20800 0x400>;
 344                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 345                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 346                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 347                         clocks = <&apb1_gates 5>;
 348                         gpio-controller;
 349                         interrupt-controller;
 350                         #address-cells = <1>;
 351                         #size-cells = <0>;
 352                         #gpio-cells = <3>;
 353
 354                         uart0_pins_a: uart0@0 {
 355                                 allwinner,pins = "PF2", "PF4";
 356                                 allwinner,function = "uart0";
 357                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 358                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 359                         };
 360
 361                         mmc0_pins_a: mmc0@0 {
 362                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 363                                 allwinner,function = "mmc0";
 364                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 365                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 366                         };
 367
 368                         mmc1_pins_a: mmc1@0 {
 369                                 allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
 370                                 allwinner,function = "mmc1";
 371                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 372                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 373                         };
 374
 375                         i2c0_pins_a: i2c0@0 {
 376                                 allwinner,pins = "PH2", "PH3";
 377                                 allwinner,function = "i2c0";
 378                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 379                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 380                         };
 381
 382                         i2c1_pins_a: i2c1@0 {
 383                                 allwinner,pins = "PH4", "PH5";
 384                                 allwinner,function = "i2c1";
 385                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 386                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 387                         };
 388
 389                         i2c2_pins_a: i2c2@0 {
 390                                 allwinner,pins = "PE12", "PE13";
 391                                 allwinner,function = "i2c2";
 392                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 393                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 394                         };
 395                 };
 396
 397                 ahb1_rst: reset@01c202c0 {
 398                         #reset-cells = <1>;
 399                         compatible = "allwinner,sun6i-a31-clock-reset";
 400                         reg = <0x01c202c0 0xc>;
 401                 };
 402
 403                 apb1_rst: reset@01c202d0 {
 404                         #reset-cells = <1>;
 405                         compatible = "allwinner,sun6i-a31-clock-reset";
 406                         reg = <0x01c202d0 0x4>;
 407                 };
 408
 409                 apb2_rst: reset@01c202d8 {
 410                         #reset-cells = <1>;
 411                         compatible = "allwinner,sun6i-a31-clock-reset";
 412                         reg = <0x01c202d8 0x4>;
 413                 };
 414
 415                 timer@01c20c00 {
 416                         compatible = "allwinner,sun4i-a10-timer";
 417                         reg = <0x01c20c00 0xa0>;
 418                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 419                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 420                         clocks = <&osc24M>;
 421                 };
 422
 423                 wdt0: watchdog@01c20ca0 {
 424                         compatible = "allwinner,sun6i-a31-wdt";
 425                         reg = <0x01c20ca0 0x20>;
 426                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 427                 };
 428
 429                 lradc: lradc@01c22800 {
 430                         compatible = "allwinner,sun4i-a10-lradc-keys";
 431                         reg = <0x01c22800 0x100>;
 432                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 433                         status = "disabled";
 434                 };
 435
 436                 uart0: serial@01c28000 {
 437                         compatible = "snps,dw-apb-uart";
 438                         reg = <0x01c28000 0x400>;
 439                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 440                         reg-shift = <2>;
 441                         reg-io-width = <4>;
 442                         clocks = <&apb2_gates 16>;
 443                         resets = <&apb2_rst 16>;
 444                         dmas = <&dma 6>, <&dma 6>;
 445                         dma-names = "rx", "tx";
 446                         status = "disabled";
 447                 };
 448
 449                 uart1: serial@01c28400 {
 450                         compatible = "snps,dw-apb-uart";
 451                         reg = <0x01c28400 0x400>;
 452                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 453                         reg-shift = <2>;
 454                         reg-io-width = <4>;
 455                         clocks = <&apb2_gates 17>;
 456                         resets = <&apb2_rst 17>;
 457                         dmas = <&dma 7>, <&dma 7>;
 458                         dma-names = "rx", "tx";
 459                         status = "disabled";
 460                 };
 461
 462                 uart2: serial@01c28800 {
 463                         compatible = "snps,dw-apb-uart";
 464                         reg = <0x01c28800 0x400>;
 465                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 466                         reg-shift = <2>;
 467                         reg-io-width = <4>;
 468                         clocks = <&apb2_gates 18>;
 469                         resets = <&apb2_rst 18>;
 470                         dmas = <&dma 8>, <&dma 8>;
 471                         dma-names = "rx", "tx";
 472                         status = "disabled";
 473                 };
 474
 475                 uart3: serial@01c28c00 {
 476                         compatible = "snps,dw-apb-uart";
 477                         reg = <0x01c28c00 0x400>;
 478                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 479                         reg-shift = <2>;
 480                         reg-io-width = <4>;
 481                         clocks = <&apb2_gates 19>;
 482                         resets = <&apb2_rst 19>;
 483                         dmas = <&dma 9>, <&dma 9>;
 484                         dma-names = "rx", "tx";
 485                         status = "disabled";
 486                 };
 487
 488                 uart4: serial@01c29000 {
 489                         compatible = "snps,dw-apb-uart";
 490                         reg = <0x01c29000 0x400>;
 491                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 492                         reg-shift = <2>;
 493                         reg-io-width = <4>;
 494                         clocks = <&apb2_gates 20>;
 495                         resets = <&apb2_rst 20>;
 496                         dmas = <&dma 10>, <&dma 10>;
 497                         dma-names = "rx", "tx";
 498                         status = "disabled";
 499                 };
 500
 501                 i2c0: i2c@01c2ac00 {
 502                         compatible = "allwinner,sun6i-a31-i2c";
 503                         reg = <0x01c2ac00 0x400>;
 504                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 505                         clocks = <&apb2_gates 0>;
 506                         resets = <&apb2_rst 0>;
 507                         status = "disabled";
 508                         #address-cells = <1>;
 509                         #size-cells = <0>;
 510                 };
 511
 512                 i2c1: i2c@01c2b000 {
 513                         compatible = "allwinner,sun6i-a31-i2c";
 514                         reg = <0x01c2b000 0x400>;
 515                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 516                         clocks = <&apb2_gates 1>;
 517                         resets = <&apb2_rst 1>;
 518                         status = "disabled";
 519                         #address-cells = <1>;
 520                         #size-cells = <0>;
 521                 };
 522
 523                 i2c2: i2c@01c2b400 {
 524                         compatible = "allwinner,sun6i-a31-i2c";
 525                         reg = <0x01c2b400 0x400>;
 526                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 527                         clocks = <&apb2_gates 2>;
 528                         resets = <&apb2_rst 2>;
 529                         status = "disabled";
 530                         #address-cells = <1>;
 531                         #size-cells = <0>;
 532                 };
 533
 534                 gic: interrupt-controller@01c81000 {
 535                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 536                         reg = <0x01c81000 0x1000>,
 537                               <0x01c82000 0x1000>,
 538                               <0x01c84000 0x2000>,
 539                               <0x01c86000 0x2000>;
 540                         interrupt-controller;
 541                         #interrupt-cells = <3>;
 542                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 543                 };
 544
 545                 rtc: rtc@01f00000 {
 546                         compatible = "allwinner,sun6i-a31-rtc";
 547                         reg = <0x01f00000 0x54>;
 548                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 549                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 550                 };
 551
 552                 prcm@01f01400 {
 553                         compatible = "allwinner,sun8i-a23-prcm";
 554                         reg = <0x01f01400 0x200>;
 555
 556                         ar100: ar100_clk {
 557                                 compatible = "fixed-factor-clock";
 558                                 #clock-cells = <0>;
 559                                 clock-div = <1>;
 560                                 clock-mult = <1>;
 561                                 clocks = <&osc24M>;
 562                                 clock-output-names = "ar100";
 563                         };
 564
 565                         ahb0: ahb0_clk {
 566                                 compatible = "fixed-factor-clock";
 567                                 #clock-cells = <0>;
 568                                 clock-div = <1>;
 569                                 clock-mult = <1>;
 570                                 clocks = <&ar100>;
 571                                 clock-output-names = "ahb0";
 572                         };
 573
 574                         apb0: apb0_clk {
 575                                 compatible = "allwinner,sun8i-a23-apb0-clk";
 576                                 #clock-cells = <0>;
 577                                 clocks = <&ahb0>;
 578                                 clock-output-names = "apb0";
 579                         };
 580
 581                         apb0_gates: apb0_gates_clk {
 582                                 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
 583                                 #clock-cells = <1>;
 584                                 clocks = <&apb0>;
 585                                 clock-output-names = "apb0_pio", "apb0_timer",
 586                                                 "apb0_rsb", "apb0_uart",
 587                                                 "apb0_i2c";
 588                         };
 589
 590                         apb0_rst: apb0_rst {
 591                                 compatible = "allwinner,sun6i-a31-clock-reset";
 592                                 #reset-cells = <1>;
 593                         };
 594                 };
 595
 596                 r_uart: serial@01f02800 {
 597                         compatible = "snps,dw-apb-uart";
 598                         reg = <0x01f02800 0x400>;
 599                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 600                         reg-shift = <2>;
 601                         reg-io-width = <4>;
 602                         clocks = <&apb0_gates 4>;
 603                         resets = <&apb0_rst 4>;
 604                         status = "disabled";
 605                 };
 606
 607                 r_pio: pinctrl@01f02c00 {
 608                         compatible = "allwinner,sun8i-a23-r-pinctrl";
 609                         reg = <0x01f02c00 0x400>;
 610                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 611                         clocks = <&apb0_gates 0>;
 612                         resets = <&apb0_rst 0>;
 613                         gpio-controller;
 614                         interrupt-controller;
 615                         #address-cells = <1>;
 616                         #size-cells = <0>;
 617                         #gpio-cells = <3>;
 618
 619                         r_uart_pins_a: r_uart@0 {
 620                                 allwinner,pins = "PL2", "PL3";
 621                                 allwinner,function = "s_uart";
 622                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 623                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 624                         };
 625                 };
 626         };
 627 };