arch/arm/boot/dts/tegra20.dtsi

   1 /include/ "skeleton.dtsi"
   2
   3 / {
   4         compatible = "nvidia,tegra20";
   5         interrupt-parent = <&intc>;
   6
   7         aliases {
   8                 serial0 = &uarta;
   9                 serial1 = &uartb;
  10                 serial2 = &uartc;
  11                 serial3 = &uartd;
  12                 serial4 = &uarte;
  13         };
  14
  15         host1x {
  16                 compatible = "nvidia,tegra20-host1x", "simple-bus";
  17                 reg = <0x50000000 0x00024000>;
  18                 interrupts = <0 65 0x04   /* mpcore syncpt */
  19                               0 67 0x04>; /* mpcore general */
  20                 clocks = <&tegra_car 28>;
  21
  22                 #address-cells = <1>;
  23                 #size-cells = <1>;
  24
  25                 ranges = <0x54000000 0x54000000 0x04000000>;
  26
  27                 mpe {
  28                         compatible = "nvidia,tegra20-mpe";
  29                         reg = <0x54040000 0x00040000>;
  30                         interrupts = <0 68 0x04>;
  31                         clocks = <&tegra_car 60>;
  32                 };
  33
  34                 vi {
  35                         compatible = "nvidia,tegra20-vi";
  36                         reg = <0x54080000 0x00040000>;
  37                         interrupts = <0 69 0x04>;
  38                         clocks = <&tegra_car 100>;
  39                 };
  40
  41                 epp {
  42                         compatible = "nvidia,tegra20-epp";
  43                         reg = <0x540c0000 0x00040000>;
  44                         interrupts = <0 70 0x04>;
  45                         clocks = <&tegra_car 19>;
  46                 };
  47
  48                 isp {
  49                         compatible = "nvidia,tegra20-isp";
  50                         reg = <0x54100000 0x00040000>;
  51                         interrupts = <0 71 0x04>;
  52                         clocks = <&tegra_car 23>;
  53                 };
  54
  55                 gr2d {
  56                         compatible = "nvidia,tegra20-gr2d";
  57                         reg = <0x54140000 0x00040000>;
  58                         interrupts = <0 72 0x04>;
  59                         clocks = <&tegra_car 21>;
  60                 };
  61
  62                 gr3d {
  63                         compatible = "nvidia,tegra20-gr3d";
  64                         reg = <0x54180000 0x00040000>;
  65                         clocks = <&tegra_car 24>;
  66                 };
  67
  68                 dc@54200000 {
  69                         compatible = "nvidia,tegra20-dc";
  70                         reg = <0x54200000 0x00040000>;
  71                         interrupts = <0 73 0x04>;
  72                         clocks = <&tegra_car 27>, <&tegra_car 121>;
  73                         clock-names = "disp1", "parent";
  74
  75                         rgb {
  76                                 status = "disabled";
  77                         };
  78                 };
  79
  80                 dc@54240000 {
  81                         compatible = "nvidia,tegra20-dc";
  82                         reg = <0x54240000 0x00040000>;
  83                         interrupts = <0 74 0x04>;
  84                         clocks = <&tegra_car 26>, <&tegra_car 121>;
  85                         clock-names = "disp2", "parent";
  86
  87                         rgb {
  88                                 status = "disabled";
  89                         };
  90                 };
  91
  92                 hdmi {
  93                         compatible = "nvidia,tegra20-hdmi";
  94                         reg = <0x54280000 0x00040000>;
  95                         interrupts = <0 75 0x04>;
  96                         clocks = <&tegra_car 51>, <&tegra_car 117>;
  97                         clock-names = "hdmi", "parent";
  98                         status = "disabled";
  99                 };
 100
 101                 tvo {
 102                         compatible = "nvidia,tegra20-tvo";
 103                         reg = <0x542c0000 0x00040000>;
 104                         interrupts = <0 76 0x04>;
 105                         clocks = <&tegra_car 102>;
 106                         status = "disabled";
 107                 };
 108
 109                 dsi {
 110                         compatible = "nvidia,tegra20-dsi";
 111                         reg = <0x54300000 0x00040000>;
 112                         clocks = <&tegra_car 48>;
 113                         status = "disabled";
 114                 };
 115         };
 116
 117         timer@50004600 {
 118                 compatible = "arm,cortex-a9-twd-timer";
 119                 reg = <0x50040600 0x20>;
 120                 interrupts = <1 13 0x304>;
 121                 clocks = <&tegra_car 132>;
 122         };
 123
 124         intc: interrupt-controller {
 125                 compatible = "arm,cortex-a9-gic";
 126                 reg = <0x50041000 0x1000
 127                        0x50040100 0x0100>;
 128                 interrupt-controller;
 129                 #interrupt-cells = <3>;
 130         };
 131
 132         cache-controller {
 133                 compatible = "arm,pl310-cache";
 134                 reg = <0x50043000 0x1000>;
 135                 arm,data-latency = <5 5 2>;
 136                 arm,tag-latency = <4 4 2>;
 137                 cache-unified;
 138                 cache-level = <2>;
 139         };
 140
 141         timer@60005000 {
 142                 compatible = "nvidia,tegra20-timer";
 143                 reg = <0x60005000 0x60>;
 144                 interrupts = <0 0 0x04
 145                               0 1 0x04
 146                               0 41 0x04
 147                               0 42 0x04>;
 148                 clocks = <&tegra_car 5>;
 149         };
 150
 151         tegra_car: clock {
 152                 compatible = "nvidia,tegra20-car";
 153                 reg = <0x60006000 0x1000>;
 154                 #clock-cells = <1>;
 155         };
 156
 157         apbdma: dma {
 158                 compatible = "nvidia,tegra20-apbdma";
 159                 reg = <0x6000a000 0x1200>;
 160                 interrupts = <0 104 0x04
 161                               0 105 0x04
 162                               0 106 0x04
 163                               0 107 0x04
 164                               0 108 0x04
 165                               0 109 0x04
 166                               0 110 0x04
 167                               0 111 0x04
 168                               0 112 0x04
 169                               0 113 0x04
 170                               0 114 0x04
 171                               0 115 0x04
 172                               0 116 0x04
 173                               0 117 0x04
 174                               0 118 0x04
 175                               0 119 0x04>;
 176                 clocks = <&tegra_car 34>;
 177         };
 178
 179         ahb {
 180                 compatible = "nvidia,tegra20-ahb";
 181                 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
 182         };
 183
 184         gpio: gpio {
 185                 compatible = "nvidia,tegra20-gpio";
 186                 reg = <0x6000d000 0x1000>;
 187                 interrupts = <0 32 0x04
 188                               0 33 0x04
 189                               0 34 0x04
 190                               0 35 0x04
 191                               0 55 0x04
 192                               0 87 0x04
 193                               0 89 0x04>;
 194                 #gpio-cells = <2>;
 195                 gpio-controller;
 196                 #interrupt-cells = <2>;
 197                 interrupt-controller;
 198         };
 199
 200         pinmux: pinmux {
 201                 compatible = "nvidia,tegra20-pinmux";
 202                 reg = <0x70000014 0x10   /* Tri-state registers */
 203                        0x70000080 0x20   /* Mux registers */
 204                        0x700000a0 0x14   /* Pull-up/down registers */
 205                        0x70000868 0xa8>; /* Pad control registers */
 206         };
 207
 208         das {
 209                 compatible = "nvidia,tegra20-das";
 210                 reg = <0x70000c00 0x80>;
 211         };
 212
 213         tegra_ac97: ac97 {
 214                 compatible = "nvidia,tegra20-ac97";
 215                 reg = <0x70002000 0x200>;
 216                 interrupts = <0 81 0x04>;
 217                 nvidia,dma-request-selector = <&apbdma 12>;
 218                 clocks = <&tegra_car 3>;
 219                 status = "disabled";
 220         };
 221
 222         tegra_i2s1: i2s@70002800 {
 223                 compatible = "nvidia,tegra20-i2s";
 224                 reg = <0x70002800 0x200>;
 225                 interrupts = <0 13 0x04>;
 226                 nvidia,dma-request-selector = <&apbdma 2>;
 227                 clocks = <&tegra_car 11>;
 228                 status = "disabled";
 229         };
 230
 231         tegra_i2s2: i2s@70002a00 {
 232                 compatible = "nvidia,tegra20-i2s";
 233                 reg = <0x70002a00 0x200>;
 234                 interrupts = <0 3 0x04>;
 235                 nvidia,dma-request-selector = <&apbdma 1>;
 236                 clocks = <&tegra_car 18>;
 237                 status = "disabled";
 238         };
 239
 240         /*
 241          * There are two serial driver i.e. 8250 based simple serial
 242          * driver and APB DMA based serial driver for higher baudrate
 243          * and performace. To enable the 8250 based driver, the compatible
 244          * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
 245          * driver, the comptible is "nvidia,tegra20-hsuart".
 246          */
 247         uarta: serial@70006000 {
 248                 compatible = "nvidia,tegra20-uart";
 249                 reg = <0x70006000 0x40>;
 250                 reg-shift = <2>;
 251                 interrupts = <0 36 0x04>;
 252                 nvidia,dma-request-selector = <&apbdma 8>;
 253                 clocks = <&tegra_car 6>;
 254                 status = "disabled";
 255         };
 256
 257         uartb: serial@70006040 {
 258                 compatible = "nvidia,tegra20-uart";
 259                 reg = <0x70006040 0x40>;
 260                 reg-shift = <2>;
 261                 interrupts = <0 37 0x04>;
 262                 nvidia,dma-request-selector = <&apbdma 9>;
 263                 clocks = <&tegra_car 96>;
 264                 status = "disabled";
 265         };
 266
 267         uartc: serial@70006200 {
 268                 compatible = "nvidia,tegra20-uart";
 269                 reg = <0x70006200 0x100>;
 270                 reg-shift = <2>;
 271                 interrupts = <0 46 0x04>;
 272                 nvidia,dma-request-selector = <&apbdma 10>;
 273                 clocks = <&tegra_car 55>;
 274                 status = "disabled";
 275         };
 276
 277         uartd: serial@70006300 {
 278                 compatible = "nvidia,tegra20-uart";
 279                 reg = <0x70006300 0x100>;
 280                 reg-shift = <2>;
 281                 interrupts = <0 90 0x04>;
 282                 nvidia,dma-request-selector = <&apbdma 19>;
 283                 clocks = <&tegra_car 65>;
 284                 status = "disabled";
 285         };
 286
 287         uarte: serial@70006400 {
 288                 compatible = "nvidia,tegra20-uart";
 289                 reg = <0x70006400 0x100>;
 290                 reg-shift = <2>;
 291                 interrupts = <0 91 0x04>;
 292                 nvidia,dma-request-selector = <&apbdma 20>;
 293                 clocks = <&tegra_car 66>;
 294                 status = "disabled";
 295         };
 296
 297         pwm: pwm {
 298                 compatible = "nvidia,tegra20-pwm";
 299                 reg = <0x7000a000 0x100>;
 300                 #pwm-cells = <2>;
 301                 clocks = <&tegra_car 17>;
 302         };
 303
 304         rtc {
 305                 compatible = "nvidia,tegra20-rtc";
 306                 reg = <0x7000e000 0x100>;
 307                 interrupts = <0 2 0x04>;
 308                 clocks = <&tegra_car 4>;
 309         };
 310
 311         i2c@7000c000 {
 312                 compatible = "nvidia,tegra20-i2c";
 313                 reg = <0x7000c000 0x100>;
 314                 interrupts = <0 38 0x04>;
 315                 #address-cells = <1>;
 316                 #size-cells = <0>;
 317                 clocks = <&tegra_car 12>, <&tegra_car 124>;
 318                 clock-names = "div-clk", "fast-clk";
 319                 status = "disabled";
 320         };
 321
 322         spi@7000c380 {
 323                 compatible = "nvidia,tegra20-sflash";
 324                 reg = <0x7000c380 0x80>;
 325                 interrupts = <0 39 0x04>;
 326                 nvidia,dma-request-selector = <&apbdma 11>;
 327                 #address-cells = <1>;
 328                 #size-cells = <0>;
 329                 clocks = <&tegra_car 43>;
 330                 status = "disabled";
 331         };
 332
 333         i2c@7000c400 {
 334                 compatible = "nvidia,tegra20-i2c";
 335                 reg = <0x7000c400 0x100>;
 336                 interrupts = <0 84 0x04>;
 337                 #address-cells = <1>;
 338                 #size-cells = <0>;
 339                 clocks = <&tegra_car 54>, <&tegra_car 124>;
 340                 clock-names = "div-clk", "fast-clk";
 341                 status = "disabled";
 342         };
 343
 344         i2c@7000c500 {
 345                 compatible = "nvidia,tegra20-i2c";
 346                 reg = <0x7000c500 0x100>;
 347                 interrupts = <0 92 0x04>;
 348                 #address-cells = <1>;
 349                 #size-cells = <0>;
 350                 clocks = <&tegra_car 67>, <&tegra_car 124>;
 351                 clock-names = "div-clk", "fast-clk";
 352                 status = "disabled";
 353         };
 354
 355         i2c@7000d000 {
 356                 compatible = "nvidia,tegra20-i2c-dvc";
 357                 reg = <0x7000d000 0x200>;
 358                 interrupts = <0 53 0x04>;
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361                 clocks = <&tegra_car 47>, <&tegra_car 124>;
 362                 clock-names = "div-clk", "fast-clk";
 363                 status = "disabled";
 364         };
 365
 366         spi@7000d400 {
 367                 compatible = "nvidia,tegra20-slink";
 368                 reg = <0x7000d400 0x200>;
 369                 interrupts = <0 59 0x04>;
 370                 nvidia,dma-request-selector = <&apbdma 15>;
 371                 #address-cells = <1>;
 372                 #size-cells = <0>;
 373                 clocks = <&tegra_car 41>;
 374                 status = "disabled";
 375         };
 376
 377         spi@7000d600 {
 378                 compatible = "nvidia,tegra20-slink";
 379                 reg = <0x7000d600 0x200>;
 380                 interrupts = <0 82 0x04>;
 381                 nvidia,dma-request-selector = <&apbdma 16>;
 382                 #address-cells = <1>;
 383                 #size-cells = <0>;
 384                 clocks = <&tegra_car 44>;
 385                 status = "disabled";
 386         };
 387
 388         spi@7000d800 {
 389                 compatible = "nvidia,tegra20-slink";
 390                 reg = <0x7000d480 0x200>;
 391                 interrupts = <0 83 0x04>;
 392                 nvidia,dma-request-selector = <&apbdma 17>;
 393                 #address-cells = <1>;
 394                 #size-cells = <0>;
 395                 clocks = <&tegra_car 46>;
 396                 status = "disabled";
 397         };
 398
 399         spi@7000da00 {
 400                 compatible = "nvidia,tegra20-slink";
 401                 reg = <0x7000da00 0x200>;
 402                 interrupts = <0 93 0x04>;
 403                 nvidia,dma-request-selector = <&apbdma 18>;
 404                 #address-cells = <1>;
 405                 #size-cells = <0>;
 406                 clocks = <&tegra_car 68>;
 407                 status = "disabled";
 408         };
 409
 410         kbc {
 411                 compatible = "nvidia,tegra20-kbc";
 412                 reg = <0x7000e200 0x100>;
 413                 interrupts = <0 85 0x04>;
 414                 clocks = <&tegra_car 36>;
 415                 status = "disabled";
 416         };
 417
 418         pmc {
 419                 compatible = "nvidia,tegra20-pmc";
 420                 reg = <0x7000e400 0x400>;
 421         };
 422
 423         memory-controller@7000f000 {
 424                 compatible = "nvidia,tegra20-mc";
 425                 reg = <0x7000f000 0x024
 426                        0x7000f03c 0x3c4>;
 427                 interrupts = <0 77 0x04>;
 428         };
 429
 430         iommu {
 431                 compatible = "nvidia,tegra20-gart";
 432                 reg = <0x7000f024 0x00000018    /* controller registers */
 433                        0x58000000 0x02000000>;  /* GART aperture */
 434         };
 435
 436         memory-controller@7000f400 {
 437                 compatible = "nvidia,tegra20-emc";
 438                 reg = <0x7000f400 0x200>;
 439                 #address-cells = <1>;
 440                 #size-cells = <0>;
 441         };
 442
 443         phy1: usb-phy@c5000400 {
 444                 compatible = "nvidia,tegra20-usb-phy";
 445                 reg = <0xc5000400 0x3c00>;
 446                 phy_type = "utmi";
 447                 nvidia,has-legacy-mode;
 448                 clocks = <&tegra_car 22>, <&tegra_car 127>;
 449                 clock-names = "phy", "pll_u";
 450         };
 451
 452         phy2: usb-phy@c5004400 {
 453                 compatible = "nvidia,tegra20-usb-phy";
 454                 reg = <0xc5004400 0x3c00>;
 455                 phy_type = "ulpi";
 456                 clocks = <&tegra_car 94>, <&tegra_car 127>;
 457                 clock-names = "phy", "pll_u";
 458         };
 459
 460         phy3: usb-phy@c5008400 {
 461                 compatible = "nvidia,tegra20-usb-phy";
 462                 reg = <0xc5008400 0x3C00>;
 463                 phy_type = "utmi";
 464                 clocks = <&tegra_car 22>, <&tegra_car 127>;
 465                 clock-names = "phy", "pll_u";
 466         };
 467
 468         usb@c5000000 {
 469                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 470                 reg = <0xc5000000 0x4000>;
 471                 interrupts = <0 20 0x04>;
 472                 phy_type = "utmi";
 473                 nvidia,has-legacy-mode;
 474                 clocks = <&tegra_car 22>;
 475                 nvidia,needs-double-reset;
 476                 nvidia,phy = <&phy1>;
 477                 status = "disabled";
 478         };
 479
 480         usb@c5004000 {
 481                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 482                 reg = <0xc5004000 0x4000>;
 483                 interrupts = <0 21 0x04>;
 484                 phy_type = "ulpi";
 485                 clocks = <&tegra_car 58>;
 486                 nvidia,phy = <&phy2>;
 487                 status = "disabled";
 488         };
 489
 490         usb@c5008000 {
 491                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 492                 reg = <0xc5008000 0x4000>;
 493                 interrupts = <0 97 0x04>;
 494                 phy_type = "utmi";
 495                 clocks = <&tegra_car 59>;
 496                 nvidia,phy = <&phy3>;
 497                 status = "disabled";
 498         };
 499
 500         sdhci@c8000000 {
 501                 compatible = "nvidia,tegra20-sdhci";
 502                 reg = <0xc8000000 0x200>;
 503                 interrupts = <0 14 0x04>;
 504                 clocks = <&tegra_car 14>;
 505                 status = "disabled";
 506         };
 507
 508         sdhci@c8000200 {
 509                 compatible = "nvidia,tegra20-sdhci";
 510                 reg = <0xc8000200 0x200>;
 511                 interrupts = <0 15 0x04>;
 512                 clocks = <&tegra_car 9>;
 513                 status = "disabled";
 514         };
 515
 516         sdhci@c8000400 {
 517                 compatible = "nvidia,tegra20-sdhci";
 518                 reg = <0xc8000400 0x200>;
 519                 interrupts = <0 19 0x04>;
 520                 clocks = <&tegra_car 69>;
 521                 status = "disabled";
 522         };
 523
 524         sdhci@c8000600 {
 525                 compatible = "nvidia,tegra20-sdhci";
 526                 reg = <0xc8000600 0x200>;
 527                 interrupts = <0 31 0x04>;
 528                 clocks = <&tegra_car 15>;
 529                 status = "disabled";
 530         };
 531
 532         cpus {
 533                 #address-cells = <1>;
 534                 #size-cells = <0>;
 535
 536                 cpu@0 {
 537                         device_type = "cpu";
 538                         compatible = "arm,cortex-a9";
 539                         reg = <0>;
 540                 };
 541
 542                 cpu@1 {
 543                         device_type = "cpu";
 544                         compatible = "arm,cortex-a9";
 545                         reg = <1>;
 546                 };
 547         };
 548
 549         pmu {
 550                 compatible = "arm,cortex-a9-pmu";
 551                 interrupts = <0 56 0x04
 552                               0 57 0x04>;
 553         };
 554 };