1 #include <dt-bindings/clock/tegra30-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include "skeleton.dtsi"
9 compatible = "nvidia,tegra30";
10 interrupt-parent = <&intc>;
12 pcie-controller@00003000 {
13 compatible = "nvidia,tegra30-pcie";
15 reg = <0x00003000 0x00000800 /* PADS registers */
16 0x00003800 0x00000200 /* AFI registers */
17 0x10000000 0x10000000>; /* configuration space */
18 reg-names = "pads", "afi", "cs";
19 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
20 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
21 interrupt-names = "intr", "msi";
23 #interrupt-cells = <1>;
24 interrupt-map-mask = <0 0 0 0>;
25 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
27 bus-range = <0x00 0xff>;
31 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
32 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
33 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
34 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
35 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
36 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
38 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
39 <&tegra_car TEGRA30_CLK_AFI>,
40 <&tegra_car TEGRA30_CLK_PLL_E>,
41 <&tegra_car TEGRA30_CLK_CML0>;
42 clock-names = "pex", "afi", "pll_e", "cml";
43 resets = <&tegra_car 70>,
46 reset-names = "pex", "afi", "pcie_x";
51 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
52 reg = <0x000800 0 0 0 0>;
59 nvidia,num-lanes = <2>;
64 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
65 reg = <0x001000 0 0 0 0>;
72 nvidia,num-lanes = <2>;
77 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
78 reg = <0x001800 0 0 0 0>;
85 nvidia,num-lanes = <2>;
90 compatible = "nvidia,tegra30-host1x", "simple-bus";
91 reg = <0x50000000 0x00024000>;
92 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
93 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
94 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
95 resets = <&tegra_car 28>;
96 reset-names = "host1x";
101 ranges = <0x54000000 0x54000000 0x04000000>;
104 compatible = "nvidia,tegra30-mpe";
105 reg = <0x54040000 0x00040000>;
106 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
107 clocks = <&tegra_car TEGRA30_CLK_MPE>;
108 resets = <&tegra_car 60>;
113 compatible = "nvidia,tegra30-vi";
114 reg = <0x54080000 0x00040000>;
115 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&tegra_car TEGRA30_CLK_VI>;
117 resets = <&tegra_car 20>;
122 compatible = "nvidia,tegra30-epp";
123 reg = <0x540c0000 0x00040000>;
124 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
125 clocks = <&tegra_car TEGRA30_CLK_EPP>;
126 resets = <&tegra_car 19>;
131 compatible = "nvidia,tegra30-isp";
132 reg = <0x54100000 0x00040000>;
133 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&tegra_car TEGRA30_CLK_ISP>;
135 resets = <&tegra_car 23>;
140 compatible = "nvidia,tegra30-gr2d";
141 reg = <0x54140000 0x00040000>;
142 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
143 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
144 resets = <&tegra_car 21>;
149 compatible = "nvidia,tegra30-gr3d";
150 reg = <0x54180000 0x00040000>;
151 clocks = <&tegra_car TEGRA30_CLK_GR3D
152 &tegra_car TEGRA30_CLK_GR3D2>;
153 clock-names = "3d", "3d2";
154 resets = <&tegra_car 24>,
156 reset-names = "3d", "3d2";
160 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
161 reg = <0x54200000 0x00040000>;
162 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
164 <&tegra_car TEGRA30_CLK_PLL_P>;
165 clock-names = "dc", "parent";
166 resets = <&tegra_car 27>;
177 compatible = "nvidia,tegra30-dc";
178 reg = <0x54240000 0x00040000>;
179 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
181 <&tegra_car TEGRA30_CLK_PLL_P>;
182 clock-names = "dc", "parent";
183 resets = <&tegra_car 26>;
194 compatible = "nvidia,tegra30-hdmi";
195 reg = <0x54280000 0x00040000>;
196 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
198 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
199 clock-names = "hdmi", "parent";
200 resets = <&tegra_car 51>;
201 reset-names = "hdmi";
206 compatible = "nvidia,tegra30-tvo";
207 reg = <0x542c0000 0x00040000>;
208 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&tegra_car TEGRA30_CLK_TVO>;
214 compatible = "nvidia,tegra30-dsi";
215 reg = <0x54300000 0x00040000>;
216 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
217 resets = <&tegra_car 48>;
224 compatible = "arm,cortex-a9-twd-timer";
225 reg = <0x50040600 0x20>;
226 interrupts = <GIC_PPI 13
227 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
228 clocks = <&tegra_car TEGRA30_CLK_TWD>;
231 intc: interrupt-controller@50041000 {
232 compatible = "arm,cortex-a9-gic";
233 reg = <0x50041000 0x1000
235 interrupt-controller;
236 #interrupt-cells = <3>;
239 cache-controller@50043000 {
240 compatible = "arm,pl310-cache";
241 reg = <0x50043000 0x1000>;
242 arm,data-latency = <6 6 2>;
243 arm,tag-latency = <5 5 2>;
249 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
250 reg = <0x60005000 0x400>;
251 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
260 tegra_car: clock@60006000 {
261 compatible = "nvidia,tegra30-car";
262 reg = <0x60006000 0x1000>;
267 flow-controller@60007000 {
268 compatible = "nvidia,tegra30-flowctrl";
269 reg = <0x60007000 0x1000>;
272 apbdma: dma@6000a000 {
273 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
274 reg = <0x6000a000 0x1400>;
275 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
308 resets = <&tegra_car 34>;
314 compatible = "nvidia,tegra30-ahb";
315 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
318 gpio: gpio@6000d000 {
319 compatible = "nvidia,tegra30-gpio";
320 reg = <0x6000d000 0x1000>;
321 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
331 #interrupt-cells = <2>;
332 interrupt-controller;
336 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
337 reg = <0x70000800 0x64 /* Chip revision */
338 0x70000008 0x04>; /* Strapping options */
341 pinmux: pinmux@70000868 {
342 compatible = "nvidia,tegra30-pinmux";
343 reg = <0x70000868 0xd4 /* Pad control registers */
344 0x70003000 0x3e4>; /* Mux registers */
348 * There are two serial driver i.e. 8250 based simple serial
349 * driver and APB DMA based serial driver for higher baudrate
350 * and performace. To enable the 8250 based driver, the compatible
351 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
352 * the APB DMA based serial driver, the comptible is
353 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
355 uarta: serial@70006000 {
356 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
357 reg = <0x70006000 0x40>;
359 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
361 resets = <&tegra_car 6>;
362 reset-names = "serial";
363 dmas = <&apbdma 8>, <&apbdma 8>;
364 dma-names = "rx", "tx";
368 uartb: serial@70006040 {
369 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
370 reg = <0x70006040 0x40>;
372 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
374 resets = <&tegra_car 7>;
375 reset-names = "serial";
376 dmas = <&apbdma 9>, <&apbdma 9>;
377 dma-names = "rx", "tx";
381 uartc: serial@70006200 {
382 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
383 reg = <0x70006200 0x100>;
385 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
387 resets = <&tegra_car 55>;
388 reset-names = "serial";
389 dmas = <&apbdma 10>, <&apbdma 10>;
390 dma-names = "rx", "tx";
394 uartd: serial@70006300 {
395 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
396 reg = <0x70006300 0x100>;
398 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
399 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
400 resets = <&tegra_car 65>;
401 reset-names = "serial";
402 dmas = <&apbdma 19>, <&apbdma 19>;
403 dma-names = "rx", "tx";
407 uarte: serial@70006400 {
408 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
409 reg = <0x70006400 0x100>;
411 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
413 resets = <&tegra_car 66>;
414 reset-names = "serial";
415 dmas = <&apbdma 20>, <&apbdma 20>;
416 dma-names = "rx", "tx";
421 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
422 reg = <0x7000a000 0x100>;
424 clocks = <&tegra_car TEGRA30_CLK_PWM>;
425 resets = <&tegra_car 17>;
431 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
432 reg = <0x7000e000 0x100>;
433 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&tegra_car TEGRA30_CLK_RTC>;
438 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
439 reg = <0x7000c000 0x100>;
440 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
441 #address-cells = <1>;
443 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
444 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
445 clock-names = "div-clk", "fast-clk";
446 resets = <&tegra_car 12>;
448 dmas = <&apbdma 21>, <&apbdma 21>;
449 dma-names = "rx", "tx";
454 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
455 reg = <0x7000c400 0x100>;
456 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
457 #address-cells = <1>;
459 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
460 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
461 clock-names = "div-clk", "fast-clk";
462 resets = <&tegra_car 54>;
464 dmas = <&apbdma 22>, <&apbdma 22>;
465 dma-names = "rx", "tx";
470 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
471 reg = <0x7000c500 0x100>;
472 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
473 #address-cells = <1>;
475 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
476 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
477 clock-names = "div-clk", "fast-clk";
478 resets = <&tegra_car 67>;
480 dmas = <&apbdma 23>, <&apbdma 23>;
481 dma-names = "rx", "tx";
486 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
487 reg = <0x7000c700 0x100>;
488 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
489 #address-cells = <1>;
491 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
492 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
493 resets = <&tegra_car 103>;
495 clock-names = "div-clk", "fast-clk";
496 dmas = <&apbdma 26>, <&apbdma 26>;
497 dma-names = "rx", "tx";
502 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
503 reg = <0x7000d000 0x100>;
504 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
505 #address-cells = <1>;
507 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
508 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
509 clock-names = "div-clk", "fast-clk";
510 resets = <&tegra_car 47>;
512 dmas = <&apbdma 24>, <&apbdma 24>;
513 dma-names = "rx", "tx";
518 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
519 reg = <0x7000d400 0x200>;
520 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
521 #address-cells = <1>;
523 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
524 resets = <&tegra_car 41>;
526 dmas = <&apbdma 15>, <&apbdma 15>;
527 dma-names = "rx", "tx";
532 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
533 reg = <0x7000d600 0x200>;
534 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
535 #address-cells = <1>;
537 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
538 resets = <&tegra_car 44>;
540 dmas = <&apbdma 16>, <&apbdma 16>;
541 dma-names = "rx", "tx";
546 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
547 reg = <0x7000d800 0x200>;
548 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
549 #address-cells = <1>;
551 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
552 resets = <&tegra_car 46>;
554 dmas = <&apbdma 17>, <&apbdma 17>;
555 dma-names = "rx", "tx";
560 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
561 reg = <0x7000da00 0x200>;
562 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
563 #address-cells = <1>;
565 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
566 resets = <&tegra_car 68>;
568 dmas = <&apbdma 18>, <&apbdma 18>;
569 dma-names = "rx", "tx";
574 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
575 reg = <0x7000dc00 0x200>;
576 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
577 #address-cells = <1>;
579 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
580 resets = <&tegra_car 104>;
582 dmas = <&apbdma 27>, <&apbdma 27>;
583 dma-names = "rx", "tx";
588 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
589 reg = <0x7000de00 0x200>;
590 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
591 #address-cells = <1>;
593 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
594 resets = <&tegra_car 106>;
596 dmas = <&apbdma 28>, <&apbdma 28>;
597 dma-names = "rx", "tx";
602 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
603 reg = <0x7000e200 0x100>;
604 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
605 clocks = <&tegra_car TEGRA30_CLK_KBC>;
606 resets = <&tegra_car 36>;
612 compatible = "nvidia,tegra30-pmc";
613 reg = <0x7000e400 0x400>;
614 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
615 clock-names = "pclk", "clk32k_in";
618 memory-controller@7000f000 {
619 compatible = "nvidia,tegra30-mc";
620 reg = <0x7000f000 0x010
624 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
628 compatible = "nvidia,tegra30-smmu";
629 reg = <0x7000f010 0x02c
632 nvidia,#asids = <4>; /* # of ASIDs */
633 dma-window = <0 0x40000000>; /* IOVA start & length */
638 compatible = "nvidia,tegra30-efuse";
639 reg = <0x7000f800 0x400>;
640 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
641 clock-names = "fuse";
642 resets = <&tegra_car 39>;
643 reset-names = "fuse";
647 compatible = "nvidia,tegra30-ahub";
648 reg = <0x70080000 0x200
650 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
652 <&tegra_car TEGRA30_CLK_APBIF>;
653 clock-names = "d_audio", "apbif";
654 resets = <&tegra_car 106>, /* d_audio */
655 <&tegra_car 107>, /* apbif */
656 <&tegra_car 30>, /* i2s0 */
657 <&tegra_car 11>, /* i2s1 */
658 <&tegra_car 18>, /* i2s2 */
659 <&tegra_car 101>, /* i2s3 */
660 <&tegra_car 102>, /* i2s4 */
661 <&tegra_car 108>, /* dam0 */
662 <&tegra_car 109>, /* dam1 */
663 <&tegra_car 110>, /* dam2 */
664 <&tegra_car 10>; /* spdif */
665 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
666 "i2s3", "i2s4", "dam0", "dam1", "dam2",
668 dmas = <&apbdma 1>, <&apbdma 1>,
669 <&apbdma 2>, <&apbdma 2>,
670 <&apbdma 3>, <&apbdma 3>,
671 <&apbdma 4>, <&apbdma 4>;
672 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
675 #address-cells = <1>;
678 tegra_i2s0: i2s@70080300 {
679 compatible = "nvidia,tegra30-i2s";
680 reg = <0x70080300 0x100>;
681 nvidia,ahub-cif-ids = <4 4>;
682 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
683 resets = <&tegra_car 30>;
688 tegra_i2s1: i2s@70080400 {
689 compatible = "nvidia,tegra30-i2s";
690 reg = <0x70080400 0x100>;
691 nvidia,ahub-cif-ids = <5 5>;
692 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
693 resets = <&tegra_car 11>;
698 tegra_i2s2: i2s@70080500 {
699 compatible = "nvidia,tegra30-i2s";
700 reg = <0x70080500 0x100>;
701 nvidia,ahub-cif-ids = <6 6>;
702 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
703 resets = <&tegra_car 18>;
708 tegra_i2s3: i2s@70080600 {
709 compatible = "nvidia,tegra30-i2s";
710 reg = <0x70080600 0x100>;
711 nvidia,ahub-cif-ids = <7 7>;
712 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
713 resets = <&tegra_car 101>;
718 tegra_i2s4: i2s@70080700 {
719 compatible = "nvidia,tegra30-i2s";
720 reg = <0x70080700 0x100>;
721 nvidia,ahub-cif-ids = <8 8>;
722 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
723 resets = <&tegra_car 102>;
730 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
731 reg = <0x78000000 0x200>;
732 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
733 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
734 resets = <&tegra_car 14>;
735 reset-names = "sdhci";
740 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
741 reg = <0x78000200 0x200>;
742 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
744 resets = <&tegra_car 9>;
745 reset-names = "sdhci";
750 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
751 reg = <0x78000400 0x200>;
752 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
754 resets = <&tegra_car 69>;
755 reset-names = "sdhci";
760 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
761 reg = <0x78000600 0x200>;
762 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
764 resets = <&tegra_car 15>;
765 reset-names = "sdhci";
770 compatible = "nvidia,tegra30-ehci", "usb-ehci";
771 reg = <0x7d000000 0x4000>;
772 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&tegra_car TEGRA30_CLK_USBD>;
775 resets = <&tegra_car 22>;
777 nvidia,needs-double-reset;
778 nvidia,phy = <&phy1>;
782 phy1: usb-phy@7d000000 {
783 compatible = "nvidia,tegra30-usb-phy";
784 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
786 clocks = <&tegra_car TEGRA30_CLK_USBD>,
787 <&tegra_car TEGRA30_CLK_PLL_U>,
788 <&tegra_car TEGRA30_CLK_USBD>;
789 clock-names = "reg", "pll_u", "utmi-pads";
790 resets = <&tegra_car 22>, <&tegra_car 22>;
791 reset-names = "usb", "utmi-pads";
792 nvidia,hssync-start-delay = <9>;
793 nvidia,idle-wait-delay = <17>;
794 nvidia,elastic-limit = <16>;
795 nvidia,term-range-adj = <6>;
796 nvidia,xcvr-setup = <51>;
797 nvidia.xcvr-setup-use-fuses;
798 nvidia,xcvr-lsfslew = <1>;
799 nvidia,xcvr-lsrslew = <1>;
800 nvidia,xcvr-hsslew = <32>;
801 nvidia,hssquelch-level = <2>;
802 nvidia,hsdiscon-level = <5>;
803 nvidia,has-utmi-pad-registers;
808 compatible = "nvidia,tegra30-ehci", "usb-ehci";
809 reg = <0x7d004000 0x4000>;
810 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
812 clocks = <&tegra_car TEGRA30_CLK_USB2>;
813 resets = <&tegra_car 58>;
815 nvidia,phy = <&phy2>;
819 phy2: usb-phy@7d004000 {
820 compatible = "nvidia,tegra30-usb-phy";
821 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
823 clocks = <&tegra_car TEGRA30_CLK_USB2>,
824 <&tegra_car TEGRA30_CLK_PLL_U>,
825 <&tegra_car TEGRA30_CLK_USBD>;
826 clock-names = "reg", "pll_u", "utmi-pads";
827 resets = <&tegra_car 58>, <&tegra_car 22>;
828 reset-names = "usb", "utmi-pads";
829 nvidia,hssync-start-delay = <9>;
830 nvidia,idle-wait-delay = <17>;
831 nvidia,elastic-limit = <16>;
832 nvidia,term-range-adj = <6>;
833 nvidia,xcvr-setup = <51>;
834 nvidia.xcvr-setup-use-fuses;
835 nvidia,xcvr-lsfslew = <2>;
836 nvidia,xcvr-lsrslew = <2>;
837 nvidia,xcvr-hsslew = <32>;
838 nvidia,hssquelch-level = <2>;
839 nvidia,hsdiscon-level = <5>;
844 compatible = "nvidia,tegra30-ehci", "usb-ehci";
845 reg = <0x7d008000 0x4000>;
846 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&tegra_car TEGRA30_CLK_USB3>;
849 resets = <&tegra_car 59>;
851 nvidia,phy = <&phy3>;
855 phy3: usb-phy@7d008000 {
856 compatible = "nvidia,tegra30-usb-phy";
857 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
859 clocks = <&tegra_car TEGRA30_CLK_USB3>,
860 <&tegra_car TEGRA30_CLK_PLL_U>,
861 <&tegra_car TEGRA30_CLK_USBD>;
862 clock-names = "reg", "pll_u", "utmi-pads";
863 resets = <&tegra_car 59>, <&tegra_car 22>;
864 reset-names = "usb", "utmi-pads";
865 nvidia,hssync-start-delay = <0>;
866 nvidia,idle-wait-delay = <17>;
867 nvidia,elastic-limit = <16>;
868 nvidia,term-range-adj = <6>;
869 nvidia,xcvr-setup = <51>;
870 nvidia.xcvr-setup-use-fuses;
871 nvidia,xcvr-lsfslew = <2>;
872 nvidia,xcvr-lsrslew = <2>;
873 nvidia,xcvr-hsslew = <32>;
874 nvidia,hssquelch-level = <2>;
875 nvidia,hsdiscon-level = <5>;
880 #address-cells = <1>;
885 compatible = "arm,cortex-a9";
891 compatible = "arm,cortex-a9";
897 compatible = "arm,cortex-a9";
903 compatible = "arm,cortex-a9";
909 compatible = "arm,cortex-a9-pmu";
910 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
911 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
912 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
913 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;