arch/arm/boot/dts/versatile-ab.dts

   1 /dts-v1/;
   2 /include/ "skeleton.dtsi"
   3
   4 / {
   5         model = "ARM Versatile AB";
   6         compatible = "arm,versatile-ab";
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         interrupt-parent = <&vic>;
  10
  11         aliases {
  12                 serial0 = &uart0;
  13                 serial1 = &uart1;
  14                 serial2 = &uart2;
  15                 i2c0 = &i2c0;
  16         };
  17
  18         memory {
  19                 reg = <0x0 0x08000000>;
  20         };
  21
  22         xtal24mhz: xtal24mhz@24M {
  23                 #clock-cells = <0>;
  24                 compatible = "fixed-clock";
  25                 clock-frequency = <24000000>;
  26         };
  27
  28         core-module@10000000 {
  29                 compatible = "arm,core-module-versatile", "syscon";
  30                 reg = <0x10000000 0x200>;
  31
  32                 /* OSC1 on AB, OSC4 on PB */
  33                 osc1: cm_aux_osc@24M {
  34                         #clock-cells = <0>;
  35                         compatible = "arm,versatile-cm-auxosc";
  36                         clocks = <&xtal24mhz>;
  37                 };
  38
  39                 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
  40                 timclk: timclk@1M {
  41                         #clock-cells = <0>;
  42                         compatible = "fixed-factor-clock";
  43                         clock-div = <24>;
  44                         clock-mult = <1>;
  45                         clocks = <&xtal24mhz>;
  46                 };
  47
  48                 pclk: pclk@24M {
  49                         #clock-cells = <0>;
  50                         compatible = "fixed-factor-clock";
  51                         clock-div = <1>;
  52                         clock-mult = <1>;
  53                         clocks = <&xtal24mhz>;
  54                 };
  55         };
  56
  57         flash@34000000 {
  58                 compatible = "arm,versatile-flash";
  59                 reg = <0x34000000 0x4000000>;
  60                 bank-width = <4>;
  61         };
  62
  63         i2c0: i2c@10002000 {
  64                 #address-cells = <1>;
  65                 #size-cells = <0>;
  66                 compatible = "arm,versatile-i2c";
  67                 reg = <0x10002000 0x1000>;
  68
  69                 rtc@68 {
  70                         compatible = "dallas,ds1338";
  71                         reg = <0x68>;
  72                 };
  73         };
  74
  75         net@10010000 {
  76                 compatible = "smsc,lan91c111";
  77                 reg = <0x10010000 0x10000>;
  78                 interrupts = <25>;
  79         };
  80
  81         lcd@10008000 {
  82                 compatible = "arm,versatile-lcd";
  83                 reg = <0x10008000 0x1000>;
  84         };
  85
  86         amba {
  87                 compatible = "arm,amba-bus";
  88                 #address-cells = <1>;
  89                 #size-cells = <1>;
  90                 ranges;
  91
  92                 vic: intc@10140000 {
  93                         compatible = "arm,versatile-vic";
  94                         interrupt-controller;
  95                         #interrupt-cells = <1>;
  96                         reg = <0x10140000 0x1000>;
  97                         clear-mask = <0xffffffff>;
  98                         valid-mask = <0xffffffff>;
  99                 };
 100
 101                 sic: intc@10003000 {
 102                         compatible = "arm,versatile-sic";
 103                         interrupt-controller;
 104                         #interrupt-cells = <1>;
 105                         reg = <0x10003000 0x1000>;
 106                         interrupt-parent = <&vic>;
 107                         interrupts = <31>; /* Cascaded to vic */
 108                         clear-mask = <0xffffffff>;
 109                         valid-mask = <0xffc203f8>;
 110                 };
 111
 112                 dma@10130000 {
 113                         compatible = "arm,pl081", "arm,primecell";
 114                         reg = <0x10130000 0x1000>;
 115                         interrupts = <17>;
 116                         clocks = <&pclk>;
 117                         clock-names = "apb_pclk";
 118                 };
 119
 120                 uart0: uart@101f1000 {
 121                         compatible = "arm,pl011", "arm,primecell";
 122                         reg = <0x101f1000 0x1000>;
 123                         interrupts = <12>;
 124                         clocks = <&xtal24mhz>, <&pclk>;
 125                         clock-names = "uartclk", "apb_pclk";
 126                 };
 127
 128                 uart1: uart@101f2000 {
 129                         compatible = "arm,pl011", "arm,primecell";
 130                         reg = <0x101f2000 0x1000>;
 131                         interrupts = <13>;
 132                         clocks = <&xtal24mhz>, <&pclk>;
 133                         clock-names = "uartclk", "apb_pclk";
 134                 };
 135
 136                 uart2: uart@101f3000 {
 137                         compatible = "arm,pl011", "arm,primecell";
 138                         reg = <0x101f3000 0x1000>;
 139                         interrupts = <14>;
 140                         clocks = <&xtal24mhz>, <&pclk>;
 141                         clock-names = "uartclk", "apb_pclk";
 142                 };
 143
 144                 smc@10100000 {
 145                         compatible = "arm,primecell";
 146                         reg = <0x10100000 0x1000>;
 147                         clocks = <&pclk>;
 148                         clock-names = "apb_pclk";
 149                 };
 150
 151                 mpmc@10110000 {
 152                         compatible = "arm,primecell";
 153                         reg = <0x10110000 0x1000>;
 154                         clocks = <&pclk>;
 155                         clock-names = "apb_pclk";
 156                 };
 157
 158                 display@10120000 {
 159                         compatible = "arm,pl110", "arm,primecell";
 160                         reg = <0x10120000 0x1000>;
 161                         interrupts = <16>;
 162                         clocks = <&osc1>, <&pclk>;
 163                         clock-names = "clcd", "apb_pclk";
 164                 };
 165
 166                 sctl@101e0000 {
 167                         compatible = "arm,primecell";
 168                         reg = <0x101e0000 0x1000>;
 169                         clocks = <&pclk>;
 170                         clock-names = "apb_pclk";
 171                 };
 172
 173                 watchdog@101e1000 {
 174                         compatible = "arm,primecell";
 175                         reg = <0x101e1000 0x1000>;
 176                         interrupts = <0>;
 177                         clocks = <&pclk>;
 178                         clock-names = "apb_pclk";
 179                 };
 180
 181                 timer@101e2000 {
 182                         compatible = "arm,sp804", "arm,primecell";
 183                         reg = <0x101e2000 0x1000>;
 184                         interrupts = <4>;
 185                         clocks = <&timclk>, <&timclk>, <&pclk>;
 186                         clock-names = "timer0", "timer1", "apb_pclk";
 187                 };
 188
 189                 timer@101e3000 {
 190                         compatible = "arm,sp804", "arm,primecell";
 191                         reg = <0x101e3000 0x1000>;
 192                         interrupts = <5>;
 193                         clocks = <&timclk>, <&timclk>, <&pclk>;
 194                         clock-names = "timer0", "timer1", "apb_pclk";
 195                 };
 196
 197                 gpio0: gpio@101e4000 {
 198                         compatible = "arm,pl061", "arm,primecell";
 199                         reg = <0x101e4000 0x1000>;
 200                         gpio-controller;
 201                         interrupts = <6>;
 202                         #gpio-cells = <2>;
 203                         interrupt-controller;
 204                         #interrupt-cells = <2>;
 205                         clocks = <&pclk>;
 206                         clock-names = "apb_pclk";
 207                 };
 208
 209                 gpio1: gpio@101e5000 {
 210                         compatible = "arm,pl061", "arm,primecell";
 211                         reg = <0x101e5000 0x1000>;
 212                         interrupts = <7>;
 213                         gpio-controller;
 214                         #gpio-cells = <2>;
 215                         interrupt-controller;
 216                         #interrupt-cells = <2>;
 217                         clocks = <&pclk>;
 218                         clock-names = "apb_pclk";
 219                 };
 220
 221                 rtc@101e8000 {
 222                         compatible = "arm,pl030", "arm,primecell";
 223                         reg = <0x101e8000 0x1000>;
 224                         interrupts = <10>;
 225                         clocks = <&pclk>;
 226                         clock-names = "apb_pclk";
 227                 };
 228
 229                 sci@101f0000 {
 230                         compatible = "arm,primecell";
 231                         reg = <0x101f0000 0x1000>;
 232                         interrupts = <15>;
 233                         clocks = <&pclk>;
 234                         clock-names = "apb_pclk";
 235                 };
 236
 237                 ssp@101f4000 {
 238                         compatible = "arm,pl022", "arm,primecell";
 239                         reg = <0x101f4000 0x1000>;
 240                         interrupts = <11>;
 241                         clocks = <&xtal24mhz>, <&pclk>;
 242                         clock-names = "SSPCLK", "apb_pclk";
 243                 };
 244
 245                 fpga {
 246                         compatible = "arm,versatile-fpga", "simple-bus";
 247                         #address-cells = <1>;
 248                         #size-cells = <1>;
 249                         ranges = <0 0x10000000 0x10000>;
 250
 251                         aaci@4000 {
 252                                 compatible = "arm,primecell";
 253                                 reg = <0x4000 0x1000>;
 254                                 interrupts = <24>;
 255                                 clocks = <&pclk>;
 256                                 clock-names = "apb_pclk";
 257                         };
 258                         mmc@5000 {
 259                                 compatible = "arm,pl180", "arm,primecell";
 260                                 reg = < 0x5000 0x1000>;
 261                                 interrupts-extended = <&vic 22 &sic 2>;
 262                                 clocks = <&xtal24mhz>, <&pclk>;
 263                                 clock-names = "mclk", "apb_pclk";
 264                         };
 265                         kmi@6000 {
 266                                 compatible = "arm,pl050", "arm,primecell";
 267                                 reg = <0x6000 0x1000>;
 268                                 interrupt-parent = <&sic>;
 269                                 interrupts = <3>;
 270                                 clocks = <&xtal24mhz>, <&pclk>;
 271                                 clock-names = "KMIREFCLK", "apb_pclk";
 272                         };
 273                         kmi@7000 {
 274                                 compatible = "arm,pl050", "arm,primecell";
 275                                 reg = <0x7000 0x1000>;
 276                                 interrupt-parent = <&sic>;
 277                                 interrupts = <4>;
 278                                 clocks = <&xtal24mhz>, <&pclk>;
 279                                 clock-names = "KMIREFCLK", "apb_pclk";
 280                         };
 281                 };
 282         };
 283 };