arch/arm/boot/dts/vf610-zii-dev-rev-b.dts

   1 /*
   2  * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
   3  *
   4  * Based on an original 'vf610-twr.dts' which is Copyright 2015,
   5  * Freescale Semiconductor, Inc.
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License
  14  *     version 2 as published by the Free Software Foundation.
  15  *
  16  *     This file is distributed in the hope that it will be useful
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 /dts-v1/;
  46 #include "vf610.dtsi"
  47
  48 / {
  49         model = "ZII VF610 Development Board, Rev B";
  50         compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610";
  51
  52         chosen {
  53                 stdout-path = "serial0:115200n8";
  54         };
  55
  56         memory {
  57                 reg = <0x80000000 0x20000000>;
  58         };
  59
  60         gpio-leds {
  61                 compatible = "gpio-leds";
  62                 pinctrl-0 = <&pinctrl_leds_debug>;
  63                 pinctrl-names = "default";
  64
  65                 debug {
  66                         label = "zii:green:debug1";
  67                         gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
  68                         linux,default-trigger = "heartbeat";
  69                 };
  70         };
  71
  72         mdio-mux {
  73                 compatible = "mdio-mux-gpio";
  74                 pinctrl-0 = <&pinctrl_mdio_mux>;
  75                 pinctrl-names = "default";
  76                 gpios = <&gpio0 8  GPIO_ACTIVE_HIGH
  77                          &gpio0 9  GPIO_ACTIVE_HIGH
  78                          &gpio0 24 GPIO_ACTIVE_HIGH
  79                          &gpio0 25 GPIO_ACTIVE_HIGH>;
  80                 mdio-parent-bus = <&mdio1>;
  81                 #address-cells = <1>;
  82                 #size-cells = <0>;
  83
  84                 mdio_mux_1: mdio@1 {
  85                         reg = <1>;
  86                         #address-cells = <1>;
  87                         #size-cells = <0>;
  88                 };
  89
  90                 mdio_mux_2: mdio@2 {
  91                         reg = <2>;
  92                         #address-cells = <1>;
  93                         #size-cells = <0>;
  94                 };
  95
  96                 mdio_mux_4: mdio@4 {
  97                         reg = <4>;
  98                         #address-cells = <1>;
  99                         #size-cells = <0>;
 100                 };
 101
 102                 mdio_mux_8: mdio@8 {
 103                         reg = <8>;
 104                         #address-cells = <1>;
 105                         #size-cells = <0>;
 106                 };
 107         };
 108
 109         dsa {
 110                 compatible = "marvell,dsa";
 111                 #address-cells = <2>;
 112                 #size-cells = <0>;
 113                 dsa,ethernet = <&fec1>;
 114                 dsa,mii-bus = <&mdio_mux_1>;
 115
 116                 /* 6352 - Primary - 7 ports */
 117                 switch0: switch@0-0 {
 118                         #address-cells = <1>;
 119                         #size-cells = <0>;
 120                         reg = <0x00 0>;
 121                         eeprom-length = <512>;
 122
 123                         port@0 {
 124                                 reg = <0>;
 125                                 label = "lan0";
 126                         };
 127
 128                         port@1 {
 129                                 reg = <1>;
 130                                 label = "lan1";
 131                         };
 132
 133                         port@2 {
 134                                 reg = <2>;
 135                                 label = "lan2";
 136                         };
 137
 138                         switch0port5: port@5 {
 139                                 reg = <5>;
 140                                 label = "dsa";
 141                                 phy-mode = "rgmii-txid";
 142                                 link = <&switch1port6
 143                                         &switch2port9>;
 144
 145                                 fixed-link {
 146                                         speed = <1000>;
 147                                         full-duplex;
 148                                 };
 149                         };
 150
 151                         port@6 {
 152                                 reg = <6>;
 153                                 label = "cpu";
 154
 155                                 fixed-link {
 156                                         speed = <100>;
 157                                         full-duplex;
 158                                 };
 159                         };
 160
 161                 };
 162
 163                 /* 6352 - Secondary - 7 ports */
 164                 switch1: switch@0-1 {
 165                         #address-cells = <1>;
 166                         #size-cells = <0>;
 167                         reg = <0x00 1>;
 168                         eeprom-length = <512>;
 169                         mii-bus = <&mdio_mux_2>;
 170
 171                         port@0 {
 172                                 reg = <0>;
 173                                 label = "lan3";
 174                         };
 175
 176                         port@1 {
 177                                 reg = <1>;
 178                                 label = "lan4";
 179                         };
 180
 181                         port@2 {
 182                                 reg = <2>;
 183                                 label = "lan5";
 184                         };
 185
 186                         switch1port5: port@5 {
 187                                 reg = <5>;
 188                                 label = "dsa";
 189                                 link = <&switch2port9>;
 190                                 phy-mode = "rgmii-txid";
 191
 192                                 fixed-link {
 193                                         speed = <1000>;
 194                                         full-duplex;
 195                                 };
 196                         };
 197
 198                         switch1port6: port@6 {
 199                                 reg = <6>;
 200                                 label = "dsa";
 201                                 phy-mode = "rgmii-txid";
 202                                 link = <&switch0port5>;
 203
 204                                 fixed-link {
 205                                         speed = <1000>;
 206                                         full-duplex;
 207                                 };
 208                         };
 209                 };
 210
 211                 /* 6185 - 10 ports */
 212                 switch2: switch@0-2 {
 213                         #address-cells = <1>;
 214                         #size-cells = <0>;
 215                         reg = <0x00 2>;
 216                         mii-bus = <&mdio_mux_4>;
 217
 218                         port@0 {
 219                                 reg = <0>;
 220                                 label = "lan6";
 221                         };
 222
 223                         port@1 {
 224                                 reg = <1>;
 225                                 label = "lan7";
 226                         };
 227
 228                         port@2 {
 229                                 reg = <2>;
 230                                 label = "lan8";
 231                         };
 232
 233                         port@3 {
 234                                 reg = <3>;
 235                                 label = "optical3";
 236
 237                                 fixed-link {
 238                                         speed = <1000>;
 239                                         full-duplex;
 240                                         link-gpios = <&gpio6 2
 241                                                       GPIO_ACTIVE_HIGH>;
 242                                 };
 243                         };
 244
 245                         port@4 {
 246                                 reg = <4>;
 247                                 label = "optical4";
 248
 249                                 fixed-link {
 250                                         speed = <1000>;
 251                                         full-duplex;
 252                                         link-gpios = <&gpio6 3
 253                                                       GPIO_ACTIVE_HIGH>;
 254                                 };
 255                         };
 256
 257                         switch2port9: port@9 {
 258                                 reg = <9>;
 259                                 label = "dsa";
 260                                 phy-mode = "rgmii-txid";
 261                                 link = <&switch1port5
 262                                         &switch0port5>;
 263
 264                                 fixed-link {
 265                                         speed = <1000>;
 266                                         full-duplex;
 267                                 };
 268                         };
 269                 };
 270         };
 271
 272         reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
 273                 compatible = "regulator-fixed";
 274                 regulator-name = "vcc_3v3_mcu";
 275                 regulator-min-microvolt = <3300000>;
 276                 regulator-max-microvolt = <3300000>;
 277         };
 278
 279         usb0_vbus: regulator-usb0-vbus {
 280                 compatible = "regulator-fixed";
 281                 pinctrl-0 = <&pinctrl_usb_vbus>;
 282                 regulator-name = "usb_vbus";
 283                 regulator-min-microvolt = <5000000>;
 284                 regulator-max-microvolt = <5000000>;
 285                 enable-active-high;
 286                 regulator-always-on;
 287                 regulator-boot-on;
 288                 gpio = <&gpio0 6 0>;
 289         };
 290
 291         spi0 {
 292                 compatible = "spi-gpio";
 293                 pinctrl-0 = <&pinctrl_gpio_spi0>;
 294                 pinctrl-names = "default";
 295                 #address-cells = <1>;
 296                 #size-cells = <0>;
 297                 gpio-sck  = <&gpio1 12 GPIO_ACTIVE_HIGH>;
 298                 gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>;
 299                 gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>;
 300                 cs-gpios  = <&gpio1  9 GPIO_ACTIVE_HIGH
 301                              &gpio1  8 GPIO_ACTIVE_HIGH>;
 302                 num-chipselects = <2>;
 303
 304                 m25p128@0 {
 305                         compatible = "m25p128", "jedec,spi-nor";
 306                         #address-cells = <1>;
 307                         #size-cells = <1>;
 308                         reg = <0>;
 309                         spi-max-frequency = <1000000>;
 310                 };
 311
 312                 at93c46d@1 {
 313                         compatible = "atmel,at93c46d";
 314                         pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>;
 315                         pinctrl-names = "default";
 316                         #address-cells = <0>;
 317                         #size-cells = <0>;
 318                         reg = <1>;
 319                         spi-max-frequency = <500000>;
 320                         spi-cs-high;
 321                         data-size = <16>;
 322                         select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
 323                 };
 324         };
 325 };
 326
 327 &adc0 {
 328         pinctrl-names = "default";
 329         pinctrl-0 = <&pinctrl_adc0_ad5>;
 330         vref-supply = <&reg_vcc_3v3_mcu>;
 331         status = "okay";
 332 };
 333
 334 &edma0 {
 335         status = "okay";
 336 };
 337
 338 &esdhc1 {
 339         pinctrl-names = "default";
 340         pinctrl-0 = <&pinctrl_esdhc1>;
 341         bus-width = <4>;
 342         status = "okay";
 343 };
 344
 345 &fec0 {
 346         phy-mode = "rmii";
 347         pinctrl-names = "default";
 348         pinctrl-0 = <&pinctrl_fec0>;
 349         status = "okay";
 350 };
 351
 352 &fec1 {
 353         phy-mode = "rmii";
 354         pinctrl-names = "default";
 355         pinctrl-0 = <&pinctrl_fec1>;
 356         status = "okay";
 357
 358         fixed-link {
 359                    speed = <100>;
 360                    full-duplex;
 361         };
 362
 363         mdio1: mdio {
 364                 #address-cells = <1>;
 365                 #size-cells = <0>;
 366                 status = "okay";
 367         };
 368 };
 369
 370 &i2c0 {
 371         clock-frequency = <100000>;
 372         pinctrl-names = "default";
 373         pinctrl-0 = <&pinctrl_i2c0>;
 374         status = "okay";
 375
 376         gpio5: pca9554@20 {
 377                 compatible = "nxp,pca9554";
 378                 reg = <0x20>;
 379                 gpio-controller;
 380                 #gpio-cells = <2>;
 381
 382         };
 383
 384         gpio6: pca9554@22 {
 385                 compatible = "nxp,pca9554";
 386                 pinctrl-names = "default";
 387                 pinctrl-0 = <&pinctrl_pca9554_22>;
 388                 reg = <0x22>;
 389                 gpio-controller;
 390                 #gpio-cells = <2>;
 391                 interrupt-parent = <&gpio2>;
 392                 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
 393         };
 394
 395         lm75@48 {
 396                 compatible = "national,lm75";
 397                 reg = <0x48>;
 398         };
 399
 400         at24c04@50 {
 401                 compatible = "atmel,24c04";
 402                 reg = <0x50>;
 403         };
 404
 405         at24c04@52 {
 406                 compatible = "atmel,24c04";
 407                 reg = <0x52>;
 408         };
 409
 410         ds1682@6b {
 411                 compatible = "dallas,ds1682";
 412                 reg = <0x6b>;
 413         };
 414 };
 415
 416 &i2c1 {
 417         clock-frequency = <100000>;
 418         pinctrl-names = "default";
 419         pinctrl-0 = <&pinctrl_i2c1>;
 420         status = "okay";
 421 };
 422
 423 &i2c2 {
 424         clock-frequency = <100000>;
 425         pinctrl-names = "default";
 426         pinctrl-0 = <&pinctrl_i2c2>;
 427         status = "okay";
 428
 429         tca9548@70 {
 430                 compatible = "nxp,pca9548";
 431                 pinctrl-0 = <&pinctrl_i2c_mux_reset>;
 432                 pinctrl-names = "default";
 433                 #address-cells = <1>;
 434                 #size-cells = <0>;
 435                 reg = <0x70>;
 436                 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
 437
 438                 i2c@0 {
 439                         #address-cells = <1>;
 440                         #size-cells = <0>;
 441                         reg = <0>;
 442
 443                         sfp1: at24c04@50 {
 444                                 compatible = "atmel,24c02";
 445                                 reg = <0x50>;
 446                         };
 447                 };
 448
 449                 i2c@1 {
 450                         #address-cells = <1>;
 451                         #size-cells = <0>;
 452                         reg = <1>;
 453
 454                         sfp2: at24c04@50 {
 455                                 compatible = "atmel,24c02";
 456                                 reg = <0x50>;
 457                         };
 458                 };
 459
 460                 i2c@2 {
 461                         #address-cells = <1>;
 462                         #size-cells = <0>;
 463                         reg = <2>;
 464
 465                         sfp3: at24c04@50 {
 466                                 compatible = "atmel,24c02";
 467                                 reg = <0x50>;
 468                         };
 469                 };
 470
 471                 i2c@3 {
 472                         #address-cells = <1>;
 473                         #size-cells = <0>;
 474                         reg = <3>;
 475
 476                         sfp4: at24c04@50 {
 477                                 compatible = "atmel,24c02";
 478                                 reg = <0x50>;
 479                         };
 480                 };
 481
 482                 i2c@4 {
 483                         #address-cells = <1>;
 484                         #size-cells = <0>;
 485                         reg = <4>;
 486                 };
 487         };
 488 };
 489
 490 &i2c3 {
 491         clock-frequency = <100000>;
 492         pinctrl-names = "default";
 493         pinctrl-0 = <&pinctrl_i2c3>;
 494         status = "okay";
 495 };
 496
 497 &uart0 {
 498         pinctrl-names = "default";
 499         pinctrl-0 = <&pinctrl_uart0>;
 500         status = "okay";
 501 };
 502
 503 &uart1 {
 504         pinctrl-names = "default";
 505         pinctrl-0 = <&pinctrl_uart1>;
 506         status = "okay";
 507 };
 508
 509 &uart2 {
 510         pinctrl-names = "default";
 511         pinctrl-0 = <&pinctrl_uart2>;
 512         status = "okay";
 513 };
 514
 515 &usbdev0 {
 516         disable-over-current;
 517         vbus-supply = <&usb0_vbus>;
 518         dr_mode = "host";
 519         status = "okay";
 520 };
 521
 522 &usbh1 {
 523         disable-over-current;
 524         status = "okay";
 525 };
 526
 527 &usbmisc0 {
 528         status = "okay";
 529 };
 530
 531 &usbmisc1 {
 532         status = "okay";
 533 };
 534
 535 &usbphy0 {
 536         status = "okay";
 537 };
 538
 539 &usbphy1 {
 540         status = "okay";
 541 };
 542
 543 &iomuxc {
 544         pinctrl_adc0_ad5: adc0ad5grp {
 545                 fsl,pins = <
 546                         VF610_PAD_PTC30__ADC0_SE5       0x00a1
 547                 >;
 548         };
 549
 550         pinctrl_dspi0: dspi0grp {
 551                 fsl,pins = <
 552                         VF610_PAD_PTB18__DSPI0_CS1      0x1182
 553                         VF610_PAD_PTB19__DSPI0_CS0      0x1182
 554                         VF610_PAD_PTB20__DSPI0_SIN      0x1181
 555                         VF610_PAD_PTB21__DSPI0_SOUT     0x1182
 556                         VF610_PAD_PTB22__DSPI0_SCK      0x1182
 557                 >;
 558         };
 559
 560         pinctrl_dspi2: dspi2grp {
 561                 fsl,pins = <
 562                         VF610_PAD_PTD31__DSPI2_CS1      0x1182
 563                         VF610_PAD_PTD30__DSPI2_CS0      0x1182
 564                         VF610_PAD_PTD29__DSPI2_SIN      0x1181
 565                         VF610_PAD_PTD28__DSPI2_SOUT     0x1182
 566                         VF610_PAD_PTD27__DSPI2_SCK      0x1182
 567                 >;
 568         };
 569
 570         pinctrl_esdhc1: esdhc1grp {
 571                 fsl,pins = <
 572                         VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
 573                         VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
 574                         VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
 575                         VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
 576                         VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
 577                         VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
 578                         VF610_PAD_PTA7__GPIO_134        0x219d
 579                 >;
 580         };
 581
 582         pinctrl_fec0: fec0grp {
 583                 fsl,pins = <
 584                         VF610_PAD_PTC0__ENET_RMII0_MDC  0x30d2
 585                         VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d3
 586                         VF610_PAD_PTC2__ENET_RMII0_CRS  0x30d1
 587                         VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
 588                         VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
 589                         VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
 590                         VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
 591                         VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
 592                         VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
 593                 >;
 594         };
 595
 596         pinctrl_fec1: fec1grp {
 597                 fsl,pins = <
 598                         VF610_PAD_PTA6__RMII_CLKIN              0x30d1
 599                         VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
 600                         VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 601                         VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 602                         VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
 603                         VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 604                         VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 605                         VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 606                         VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 607                         VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 608                 >;
 609         };
 610
 611         pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 {
 612                 fsl,pins = <
 613                         VF610_PAD_PTE27__GPIO_132       0x33e2
 614                 >;
 615         };
 616
 617         pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
 618                 fsl,pins = <
 619                         VF610_PAD_PTB22__GPIO_44        0x33e2
 620                         VF610_PAD_PTB21__GPIO_43        0x33e2
 621                         VF610_PAD_PTB20__GPIO_42        0x33e1
 622                         VF610_PAD_PTB19__GPIO_41        0x33e2
 623                         VF610_PAD_PTB18__GPIO_40        0x33e2
 624                 >;
 625         };
 626
 627         pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset {
 628                 fsl,pins = <
 629                          VF610_PAD_PTE14__GPIO_119      0x31c2
 630                          >;
 631         };
 632
 633         pinctrl_i2c0: i2c0grp {
 634                 fsl,pins = <
 635                         VF610_PAD_PTB14__I2C0_SCL       0x37ff
 636                         VF610_PAD_PTB15__I2C0_SDA       0x37ff
 637                 >;
 638         };
 639
 640         pinctrl_i2c1: i2c1grp {
 641                 fsl,pins = <
 642                         VF610_PAD_PTB16__I2C1_SCL       0x37ff
 643                         VF610_PAD_PTB17__I2C1_SDA       0x37ff
 644                 >;
 645         };
 646
 647         pinctrl_i2c2: i2c2grp {
 648                 fsl,pins = <
 649                         VF610_PAD_PTA22__I2C2_SCL       0x37ff
 650                         VF610_PAD_PTA23__I2C2_SDA       0x37ff
 651                 >;
 652         };
 653
 654         pinctrl_i2c3: i2c3grp {
 655                 fsl,pins = <
 656                         VF610_PAD_PTA30__I2C3_SCL       0x37ff
 657                         VF610_PAD_PTA31__I2C3_SDA       0x37ff
 658                 >;
 659         };
 660
 661         pinctrl_leds_debug: pinctrl-leds-debug {
 662                 fsl,pins = <
 663                          VF610_PAD_PTD20__GPIO_74       0x31c2
 664                          >;
 665         };
 666
 667         pinctrl_mdio_mux: pinctrl-mdio-mux {
 668                 fsl,pins = <
 669                         VF610_PAD_PTA18__GPIO_8         0x31c2
 670                         VF610_PAD_PTA19__GPIO_9         0x31c2
 671                         VF610_PAD_PTB2__GPIO_24         0x31c2
 672                         VF610_PAD_PTB3__GPIO_25         0x31c2
 673                 >;
 674         };
 675
 676         pinctrl_pca9554_22: pinctrl-pca95540-22 {
 677                 fsl,pins = <
 678                         VF610_PAD_PTB28__GPIO_98        0x219d
 679                 >;
 680         };
 681
 682         pinctrl_pwm0: pwm0grp {
 683                 fsl,pins = <
 684                         VF610_PAD_PTB0__FTM0_CH0        0x1582
 685                         VF610_PAD_PTB1__FTM0_CH1        0x1582
 686                         VF610_PAD_PTB2__FTM0_CH2        0x1582
 687                         VF610_PAD_PTB3__FTM0_CH3        0x1582
 688                 >;
 689         };
 690
 691         pinctrl_qspi0: qspi0grp {
 692                 fsl,pins = <
 693                         VF610_PAD_PTD7__QSPI0_B_QSCK    0x31c3
 694                         VF610_PAD_PTD8__QSPI0_B_CS0     0x31ff
 695                         VF610_PAD_PTD9__QSPI0_B_DATA3   0x31c3
 696                         VF610_PAD_PTD10__QSPI0_B_DATA2  0x31c3
 697                         VF610_PAD_PTD11__QSPI0_B_DATA1  0x31c3
 698                         VF610_PAD_PTD12__QSPI0_B_DATA0  0x31c3
 699                 >;
 700         };
 701
 702         pinctrl_uart0: uart0grp {
 703                 fsl,pins = <
 704                         VF610_PAD_PTB10__UART0_TX       0x21a2
 705                         VF610_PAD_PTB11__UART0_RX       0x21a1
 706                 >;
 707         };
 708
 709         pinctrl_uart1: uart1grp {
 710                 fsl,pins = <
 711                         VF610_PAD_PTB23__UART1_TX       0x21a2
 712                         VF610_PAD_PTB24__UART1_RX       0x21a1
 713                 >;
 714         };
 715
 716         pinctrl_uart2: uart2grp {
 717                 fsl,pins = <
 718                         VF610_PAD_PTD0__UART2_TX        0x21a2
 719                         VF610_PAD_PTD1__UART2_RX        0x21a1
 720                 >;
 721         };
 722
 723         pinctrl_usb_vbus: pinctrl-usb-vbus {
 724                 fsl,pins = <
 725                         VF610_PAD_PTA16__GPIO_6 0x31c2
 726                 >;
 727         };
 728
 729         pinctrl_usb0_host: usb0-host-grp {
 730                 fsl,pins = <
 731                         VF610_PAD_PTD6__GPIO_85         0x0062
 732                 >;
 733         };
 734 };