2 * arch/arm/include/asm/atomic.h
4 * Copyright (C) 1996 Russell King.
5 * Copyright (C) 2002 Deep Blue Solutions Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #ifndef __ASM_ARM_ATOMIC_H
12 #define __ASM_ARM_ATOMIC_H
14 #include <linux/compiler.h>
15 #include <linux/prefetch.h>
16 #include <linux/types.h>
17 #include <linux/irqflags.h>
18 #include <asm/barrier.h>
19 #include <asm/cmpxchg.h>
21 #define ATOMIC_INIT(i) { (i) }
26 * On ARM, ordinary assignment (str instruction) doesn't clear the local
27 * strex/ldrex monitor on some implementations. The reason we can use it for
28 * atomic_set() is the clrex or dummy strex done on every exception return.
30 #define atomic_read(v) (*(volatile int *)&(v)->counter)
31 #define atomic_set(v,i) (((v)->counter) = (i))
33 #if __LINUX_ARM_ARCH__ >= 6
36 * ARMv6 UP and SMP safe atomic ops. We use load exclusive and
37 * store exclusive to ensure that these are atomic. We may loop
38 * to ensure that the update happens.
40 static inline void atomic_add(int i, atomic_t *v)
45 prefetchw(&v->counter);
46 __asm__ __volatile__("@ atomic_add\n"
49 " strex %1, %0, [%3]\n"
52 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
53 : "r" (&v->counter), "Ir" (i)
57 static inline int atomic_add_return(int i, atomic_t *v)
63 prefetchw(&v->counter);
65 __asm__ __volatile__("@ atomic_add_return\n"
68 " strex %1, %0, [%3]\n"
71 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
72 : "r" (&v->counter), "Ir" (i)
80 static inline void atomic_sub(int i, atomic_t *v)
85 prefetchw(&v->counter);
86 __asm__ __volatile__("@ atomic_sub\n"
89 " strex %1, %0, [%3]\n"
92 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
93 : "r" (&v->counter), "Ir" (i)
97 static inline int atomic_sub_return(int i, atomic_t *v)
103 prefetchw(&v->counter);
105 __asm__ __volatile__("@ atomic_sub_return\n"
106 "1: ldrex %0, [%3]\n"
108 " strex %1, %0, [%3]\n"
111 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
112 : "r" (&v->counter), "Ir" (i)
120 static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
126 prefetchw(&ptr->counter);
129 __asm__ __volatile__("@ atomic_cmpxchg\n"
133 "strexeq %0, %5, [%3]\n"
134 : "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
135 : "r" (&ptr->counter), "Ir" (old), "r" (new)
144 static inline int __atomic_add_unless(atomic_t *v, int a, int u)
150 prefetchw(&v->counter);
152 __asm__ __volatile__ ("@ atomic_add_unless\n"
153 "1: ldrex %0, [%4]\n"
157 " strex %2, %1, [%4]\n"
161 : "=&r" (oldval), "=&r" (newval), "=&r" (tmp), "+Qo" (v->counter)
162 : "r" (&v->counter), "r" (u), "r" (a)
171 #else /* ARM_ARCH_6 */
174 #error SMP not supported on pre-ARMv6 CPUs
177 static inline int atomic_add_return(int i, atomic_t *v)
182 raw_local_irq_save(flags);
184 v->counter = val += i;
185 raw_local_irq_restore(flags);
189 #define atomic_add(i, v) (void) atomic_add_return(i, v)
191 static inline int atomic_sub_return(int i, atomic_t *v)
196 raw_local_irq_save(flags);
198 v->counter = val -= i;
199 raw_local_irq_restore(flags);
203 #define atomic_sub(i, v) (void) atomic_sub_return(i, v)
205 static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
210 raw_local_irq_save(flags);
212 if (likely(ret == old))
214 raw_local_irq_restore(flags);
219 static inline int __atomic_add_unless(atomic_t *v, int a, int u)
224 while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c)
229 #endif /* __LINUX_ARM_ARCH__ */
231 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
233 #define atomic_inc(v) atomic_add(1, v)
234 #define atomic_dec(v) atomic_sub(1, v)
236 #define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0)
237 #define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
238 #define atomic_inc_return(v) (atomic_add_return(1, v))
239 #define atomic_dec_return(v) (atomic_sub_return(1, v))
240 #define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
242 #define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)
244 #ifndef CONFIG_GENERIC_ATOMIC64
249 #define ATOMIC64_INIT(i) { (i) }
251 #ifdef CONFIG_ARM_LPAE
252 static inline long long atomic64_read(const atomic64_t *v)
256 __asm__ __volatile__("@ atomic64_read\n"
257 " ldrd %0, %H0, [%1]"
259 : "r" (&v->counter), "Qo" (v->counter)
265 static inline void atomic64_set(atomic64_t *v, long long i)
267 __asm__ __volatile__("@ atomic64_set\n"
268 " strd %2, %H2, [%1]"
270 : "r" (&v->counter), "r" (i)
274 static inline long long atomic64_read(const atomic64_t *v)
278 __asm__ __volatile__("@ atomic64_read\n"
279 " ldrexd %0, %H0, [%1]"
281 : "r" (&v->counter), "Qo" (v->counter)
287 static inline void atomic64_set(atomic64_t *v, long long i)
291 prefetchw(&v->counter);
292 __asm__ __volatile__("@ atomic64_set\n"
293 "1: ldrexd %0, %H0, [%2]\n"
294 " strexd %0, %3, %H3, [%2]\n"
297 : "=&r" (tmp), "=Qo" (v->counter)
298 : "r" (&v->counter), "r" (i)
303 static inline void atomic64_add(long long i, atomic64_t *v)
308 prefetchw(&v->counter);
309 __asm__ __volatile__("@ atomic64_add\n"
310 "1: ldrexd %0, %H0, [%3]\n"
311 " adds %Q0, %Q0, %Q4\n"
312 " adc %R0, %R0, %R4\n"
313 " strexd %1, %0, %H0, [%3]\n"
316 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
317 : "r" (&v->counter), "r" (i)
321 static inline long long atomic64_add_return(long long i, atomic64_t *v)
327 prefetchw(&v->counter);
329 __asm__ __volatile__("@ atomic64_add_return\n"
330 "1: ldrexd %0, %H0, [%3]\n"
331 " adds %Q0, %Q0, %Q4\n"
332 " adc %R0, %R0, %R4\n"
333 " strexd %1, %0, %H0, [%3]\n"
336 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
337 : "r" (&v->counter), "r" (i)
345 static inline void atomic64_sub(long long i, atomic64_t *v)
350 prefetchw(&v->counter);
351 __asm__ __volatile__("@ atomic64_sub\n"
352 "1: ldrexd %0, %H0, [%3]\n"
353 " subs %Q0, %Q0, %Q4\n"
354 " sbc %R0, %R0, %R4\n"
355 " strexd %1, %0, %H0, [%3]\n"
358 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
359 : "r" (&v->counter), "r" (i)
363 static inline long long atomic64_sub_return(long long i, atomic64_t *v)
369 prefetchw(&v->counter);
371 __asm__ __volatile__("@ atomic64_sub_return\n"
372 "1: ldrexd %0, %H0, [%3]\n"
373 " subs %Q0, %Q0, %Q4\n"
374 " sbc %R0, %R0, %R4\n"
375 " strexd %1, %0, %H0, [%3]\n"
378 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
379 : "r" (&v->counter), "r" (i)
387 static inline long long atomic64_cmpxchg(atomic64_t *ptr, long long old,
394 prefetchw(&ptr->counter);
397 __asm__ __volatile__("@ atomic64_cmpxchg\n"
398 "ldrexd %1, %H1, [%3]\n"
402 "strexdeq %0, %5, %H5, [%3]"
403 : "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
404 : "r" (&ptr->counter), "r" (old), "r" (new)
413 static inline long long atomic64_xchg(atomic64_t *ptr, long long new)
419 prefetchw(&ptr->counter);
421 __asm__ __volatile__("@ atomic64_xchg\n"
422 "1: ldrexd %0, %H0, [%3]\n"
423 " strexd %1, %4, %H4, [%3]\n"
426 : "=&r" (result), "=&r" (tmp), "+Qo" (ptr->counter)
427 : "r" (&ptr->counter), "r" (new)
435 static inline long long atomic64_dec_if_positive(atomic64_t *v)
441 prefetchw(&v->counter);
443 __asm__ __volatile__("@ atomic64_dec_if_positive\n"
444 "1: ldrexd %0, %H0, [%3]\n"
445 " subs %Q0, %Q0, #1\n"
446 " sbc %R0, %R0, #0\n"
449 " strexd %1, %0, %H0, [%3]\n"
453 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
462 static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u)
469 prefetchw(&v->counter);
471 __asm__ __volatile__("@ atomic64_add_unless\n"
472 "1: ldrexd %0, %H0, [%4]\n"
477 " adds %Q0, %Q0, %Q6\n"
478 " adc %R0, %R0, %R6\n"
479 " strexd %2, %0, %H0, [%4]\n"
483 : "=&r" (val), "+r" (ret), "=&r" (tmp), "+Qo" (v->counter)
484 : "r" (&v->counter), "r" (u), "r" (a)
493 #define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
494 #define atomic64_inc(v) atomic64_add(1LL, (v))
495 #define atomic64_inc_return(v) atomic64_add_return(1LL, (v))
496 #define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
497 #define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
498 #define atomic64_dec(v) atomic64_sub(1LL, (v))
499 #define atomic64_dec_return(v) atomic64_sub_return(1LL, (v))
500 #define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
501 #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL)
503 #endif /* !CONFIG_GENERIC_ATOMIC64 */