2 * arch/arm/kernel/probes.c
4 * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
6 * Some contents moved here from arch/arm/include/asm/kprobes-arm.c which is
7 * Copyright (C) 2006, 2007 Motorola Inc.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/kprobes.h>
17 #include <asm/system_info.h>
18 #include <asm/ptrace.h>
19 #include <linux/bug.h>
24 #ifndef find_str_pc_offset
27 * For STR and STM instructions, an ARM core may choose to use either
28 * a +8 or a +12 displacement from the current instruction's address.
29 * Whichever value is chosen for a given core, it must be the same for
30 * both instructions and may not change. This function measures it.
35 void __init find_str_pc_offset(void)
37 int addr, scratch, ret;
40 "sub %[ret], pc, #4 \n\t"
41 "str pc, %[addr] \n\t"
42 "ldr %[scr], %[addr] \n\t"
43 "sub %[ret], %[scr], %[ret] \n\t"
44 : [ret] "=r" (ret), [scr] "=r" (scratch), [addr] "+m" (addr));
49 #endif /* !find_str_pc_offset */
52 #ifndef test_load_write_pc_interworking
54 bool load_write_pc_interworks;
56 void __init test_load_write_pc_interworking(void)
58 int arch = cpu_architecture();
59 BUG_ON(arch == CPU_ARCH_UNKNOWN);
60 load_write_pc_interworks = arch >= CPU_ARCH_ARMv5T;
63 #endif /* !test_load_write_pc_interworking */
66 #ifndef test_alu_write_pc_interworking
68 bool alu_write_pc_interworks;
70 void __init test_alu_write_pc_interworking(void)
72 int arch = cpu_architecture();
73 BUG_ON(arch == CPU_ARCH_UNKNOWN);
74 alu_write_pc_interworks = arch >= CPU_ARCH_ARMv7;
77 #endif /* !test_alu_write_pc_interworking */
80 void __init arm_kprobe_decode_init(void)
83 test_load_write_pc_interworking();
84 test_alu_write_pc_interworking();
88 static unsigned long __kprobes __check_eq(unsigned long cpsr)
90 return cpsr & PSR_Z_BIT;
93 static unsigned long __kprobes __check_ne(unsigned long cpsr)
95 return (~cpsr) & PSR_Z_BIT;
98 static unsigned long __kprobes __check_cs(unsigned long cpsr)
100 return cpsr & PSR_C_BIT;
103 static unsigned long __kprobes __check_cc(unsigned long cpsr)
105 return (~cpsr) & PSR_C_BIT;
108 static unsigned long __kprobes __check_mi(unsigned long cpsr)
110 return cpsr & PSR_N_BIT;
113 static unsigned long __kprobes __check_pl(unsigned long cpsr)
115 return (~cpsr) & PSR_N_BIT;
118 static unsigned long __kprobes __check_vs(unsigned long cpsr)
120 return cpsr & PSR_V_BIT;
123 static unsigned long __kprobes __check_vc(unsigned long cpsr)
125 return (~cpsr) & PSR_V_BIT;
128 static unsigned long __kprobes __check_hi(unsigned long cpsr)
130 cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
131 return cpsr & PSR_C_BIT;
134 static unsigned long __kprobes __check_ls(unsigned long cpsr)
136 cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
137 return (~cpsr) & PSR_C_BIT;
140 static unsigned long __kprobes __check_ge(unsigned long cpsr)
142 cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
143 return (~cpsr) & PSR_N_BIT;
146 static unsigned long __kprobes __check_lt(unsigned long cpsr)
148 cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
149 return cpsr & PSR_N_BIT;
152 static unsigned long __kprobes __check_gt(unsigned long cpsr)
154 unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
155 temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */
156 return (~temp) & PSR_N_BIT;
159 static unsigned long __kprobes __check_le(unsigned long cpsr)
161 unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
162 temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */
163 return temp & PSR_N_BIT;
166 static unsigned long __kprobes __check_al(unsigned long cpsr)
171 kprobe_check_cc * const kprobe_condition_checks[16] = {
172 &__check_eq, &__check_ne, &__check_cs, &__check_cc,
173 &__check_mi, &__check_pl, &__check_vs, &__check_vc,
174 &__check_hi, &__check_ls, &__check_ge, &__check_lt,
175 &__check_gt, &__check_le, &__check_al, &__check_al
179 void __kprobes kprobe_simulate_nop(struct kprobe *p, struct pt_regs *regs)
183 void __kprobes kprobe_emulate_none(struct kprobe *p, struct pt_regs *regs)
189 * Prepare an instruction slot to receive an instruction for emulating.
190 * This is done by placing a subroutine return after the location where the
191 * instruction will be placed. We also modify ARM instructions to be
192 * unconditional as the condition code will already be checked before any
193 * emulation handler is called.
195 static kprobe_opcode_t __kprobes
196 prepare_emulated_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi,
199 #ifdef CONFIG_THUMB2_KERNEL
201 u16 *thumb_insn = (u16 *)asi->insn;
202 thumb_insn[1] = 0x4770; /* Thumb bx lr */
203 thumb_insn[2] = 0x4770; /* Thumb bx lr */
206 asi->insn[1] = 0xe12fff1e; /* ARM bx lr */
208 asi->insn[1] = 0xe1a0f00e; /* mov pc, lr */
210 /* Make an ARM instruction unconditional */
211 if (insn < 0xe0000000)
212 insn = (insn | 0xe0000000) & ~0x10000000;
217 * Write a (probably modified) instruction into the slot previously prepared by
218 * prepare_emulated_insn
220 static void __kprobes
221 set_emulated_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi,
224 #ifdef CONFIG_THUMB2_KERNEL
226 u16 *ip = (u16 *)asi->insn;
227 if (is_wide_instruction(insn))
237 * When we modify the register numbers encoded in an instruction to be emulated,
238 * the new values come from this define. For ARM and 32-bit Thumb instructions
241 * bit position 16 12 8 4 0
242 * ---------------+---+---+---+---+---+
243 * register r2 r0 r1 -- r3
245 #define INSN_NEW_BITS 0x00020103
247 /* Each nibble has same value as that at INSN_NEW_BITS bit 16 */
248 #define INSN_SAMEAS16_BITS 0x22222222
251 * Validate and modify each of the registers encoded in an instruction.
253 * Each nibble in regs contains a value from enum decode_reg_type. For each
254 * non-zero value, the corresponding nibble in pinsn is validated and modified
255 * according to the type.
257 static bool __kprobes decode_regs(kprobe_opcode_t *pinsn, u32 regs)
259 kprobe_opcode_t insn = *pinsn;
260 kprobe_opcode_t mask = 0xf; /* Start at least significant nibble */
262 for (; regs != 0; regs >>= 4, mask <<= 4) {
264 kprobe_opcode_t new_bits = INSN_NEW_BITS;
266 switch (regs & 0xf) {
269 /* Nibble not a register, skip to next */
273 /* Any register is allowed */
276 case REG_TYPE_SAMEAS16:
277 /* Replace register with same as at bit position 16 */
278 new_bits = INSN_SAMEAS16_BITS;
282 /* Only allow SP (R13) */
283 if ((insn ^ 0xdddddddd) & mask)
288 /* Only allow PC (R15) */
289 if ((insn ^ 0xffffffff) & mask)
294 /* Reject SP (R13) */
295 if (((insn ^ 0xdddddddd) & mask) == 0)
299 case REG_TYPE_NOSPPC:
300 case REG_TYPE_NOSPPCX:
301 /* Reject SP and PC (R13 and R15) */
302 if (((insn ^ 0xdddddddd) & 0xdddddddd & mask) == 0)
306 case REG_TYPE_NOPCWB:
307 if (!is_writeback(insn))
308 break; /* No writeback, so any register is OK */
309 /* fall through... */
312 /* Reject PC (R15) */
313 if (((insn ^ 0xffffffff) & mask) == 0)
318 /* Replace value of nibble with new register number... */
320 insn |= new_bits & mask;
330 static const int decode_struct_sizes[NUM_DECODE_TYPES] = {
331 [DECODE_TYPE_TABLE] = sizeof(struct decode_table),
332 [DECODE_TYPE_CUSTOM] = sizeof(struct decode_custom),
333 [DECODE_TYPE_SIMULATE] = sizeof(struct decode_simulate),
334 [DECODE_TYPE_EMULATE] = sizeof(struct decode_emulate),
335 [DECODE_TYPE_OR] = sizeof(struct decode_or),
336 [DECODE_TYPE_REJECT] = sizeof(struct decode_reject)
340 * kprobe_decode_insn operates on data tables in order to decode an ARM
341 * architecture instruction onto which a kprobe has been placed.
343 * These instruction decoding tables are a concatenation of entries each
344 * of which consist of one of the following structs:
353 * Each of these starts with a struct decode_header which has the following
360 * The least significant DECODE_TYPE_BITS of type_regs contains a value
361 * from enum decode_type, this indicates which of the decode_* structs
362 * the entry contains. The value DECODE_TYPE_END indicates the end of the
365 * When the table is parsed, each entry is checked in turn to see if it
366 * matches the instruction to be decoded using the test:
368 * (insn & mask) == value
370 * If no match is found before the end of the table is reached then decoding
371 * fails with INSN_REJECTED.
373 * When a match is found, decode_regs() is called to validate and modify each
374 * of the registers encoded in the instruction; the data it uses to do this
375 * is (type_regs >> DECODE_TYPE_BITS). A validation failure will cause decoding
376 * to fail with INSN_REJECTED.
378 * Once the instruction has passed the above tests, further processing
379 * depends on the type of the table entry's decode struct.
383 kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi,
384 const union decode_item *table, bool thumb)
386 const struct decode_header *h = (struct decode_header *)table;
387 const struct decode_header *next;
388 bool matched = false;
390 insn = prepare_emulated_insn(insn, asi, thumb);
393 enum decode_type type = h->type_regs.bits & DECODE_TYPE_MASK;
394 u32 regs = h->type_regs.bits >> DECODE_TYPE_BITS;
396 if (type == DECODE_TYPE_END)
397 return INSN_REJECTED;
399 next = (struct decode_header *)
400 ((uintptr_t)h + decode_struct_sizes[type]);
402 if (!matched && (insn & h->mask.bits) != h->value.bits)
405 if (!decode_regs(&insn, regs))
406 return INSN_REJECTED;
410 case DECODE_TYPE_TABLE: {
411 struct decode_table *d = (struct decode_table *)h;
412 next = (struct decode_header *)d->table.table;
416 case DECODE_TYPE_CUSTOM: {
417 struct decode_custom *d = (struct decode_custom *)h;
418 return (*d->decoder.decoder)(insn, asi);
421 case DECODE_TYPE_SIMULATE: {
422 struct decode_simulate *d = (struct decode_simulate *)h;
423 asi->insn_handler = d->handler.handler;
424 return INSN_GOOD_NO_SLOT;
427 case DECODE_TYPE_EMULATE: {
428 struct decode_emulate *d = (struct decode_emulate *)h;
429 asi->insn_handler = d->handler.handler;
430 set_emulated_insn(insn, asi, thumb);
438 case DECODE_TYPE_REJECT:
440 return INSN_REJECTED;