arch/arm/mach-at91/at91cap9_devices.c

   1 /*
   2  * arch/arm/mach-at91/at91cap9_devices.c
   3  *
   4  *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
   5  *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
   6  *  Copyright (C) 2007 Atmel Corporation.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  */
  14 #include <asm/mach/arch.h>
  15 #include <asm/mach/map.h>
  16
  17 #include <linux/dma-mapping.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/mtd/physmap.h>
  20
  21 #include <video/atmel_lcdc.h>
  22
  23 #include <asm/arch/board.h>
  24 #include <asm/arch/gpio.h>
  25 #include <asm/arch/at91cap9.h>
  26 #include <asm/arch/at91cap9_matrix.h>
  27 #include <asm/arch/at91sam9_smc.h>
  28
  29 #include "generic.h"
  30
  31
  32 /* --------------------------------------------------------------------
  33  *  USB Host
  34  * -------------------------------------------------------------------- */
  35
  36 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  37 static u64 ohci_dmamask = DMA_BIT_MASK(32);
  38 static struct at91_usbh_data usbh_data;
  39
  40 static struct resource usbh_resources[] = {
  41         [0] = {
  42                 .start  = AT91CAP9_UHP_BASE,
  43                 .end    = AT91CAP9_UHP_BASE + SZ_1M - 1,
  44                 .flags  = IORESOURCE_MEM,
  45         },
  46         [1] = {
  47                 .start  = AT91CAP9_ID_UHP,
  48                 .end    = AT91CAP9_ID_UHP,
  49                 .flags  = IORESOURCE_IRQ,
  50         },
  51 };
  52
  53 static struct platform_device at91_usbh_device = {
  54         .name           = "at91_ohci",
  55         .id             = -1,
  56         .dev            = {
  57                                 .dma_mask               = &ohci_dmamask,
  58                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
  59                                 .platform_data          = &usbh_data,
  60         },
  61         .resource       = usbh_resources,
  62         .num_resources  = ARRAY_SIZE(usbh_resources),
  63 };
  64
  65 void __init at91_add_device_usbh(struct at91_usbh_data *data)
  66 {
  67         int i;
  68
  69         if (!data)
  70                 return;
  71
  72         /* Enable VBus control for UHP ports */
  73         for (i = 0; i < data->ports; i++) {
  74                 if (data->vbus_pin[i])
  75                         at91_set_gpio_output(data->vbus_pin[i], 0);
  76         }
  77
  78         usbh_data = *data;
  79         platform_device_register(&at91_usbh_device);
  80 }
  81 #else
  82 void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
  83 #endif
  84
  85
  86 /* --------------------------------------------------------------------
  87  *  Ethernet
  88  * -------------------------------------------------------------------- */
  89
  90 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
  91 static u64 eth_dmamask = DMA_BIT_MASK(32);
  92 static struct at91_eth_data eth_data;
  93
  94 static struct resource eth_resources[] = {
  95         [0] = {
  96                 .start  = AT91CAP9_BASE_EMAC,
  97                 .end    = AT91CAP9_BASE_EMAC + SZ_16K - 1,
  98                 .flags  = IORESOURCE_MEM,
  99         },
 100         [1] = {
 101                 .start  = AT91CAP9_ID_EMAC,
 102                 .end    = AT91CAP9_ID_EMAC,
 103                 .flags  = IORESOURCE_IRQ,
 104         },
 105 };
 106
 107 static struct platform_device at91cap9_eth_device = {
 108         .name           = "macb",
 109         .id             = -1,
 110         .dev            = {
 111                                 .dma_mask               = &eth_dmamask,
 112                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 113                                 .platform_data          = &eth_data,
 114         },
 115         .resource       = eth_resources,
 116         .num_resources  = ARRAY_SIZE(eth_resources),
 117 };
 118
 119 void __init at91_add_device_eth(struct at91_eth_data *data)
 120 {
 121         if (!data)
 122                 return;
 123
 124         if (data->phy_irq_pin) {
 125                 at91_set_gpio_input(data->phy_irq_pin, 0);
 126                 at91_set_deglitch(data->phy_irq_pin, 1);
 127         }
 128
 129         /* Pins used for MII and RMII */
 130         at91_set_A_periph(AT91_PIN_PB21, 0);    /* ETXCK_EREFCK */
 131         at91_set_A_periph(AT91_PIN_PB22, 0);    /* ERXDV */
 132         at91_set_A_periph(AT91_PIN_PB25, 0);    /* ERX0 */
 133         at91_set_A_periph(AT91_PIN_PB26, 0);    /* ERX1 */
 134         at91_set_A_periph(AT91_PIN_PB27, 0);    /* ERXER */
 135         at91_set_A_periph(AT91_PIN_PB28, 0);    /* ETXEN */
 136         at91_set_A_periph(AT91_PIN_PB23, 0);    /* ETX0 */
 137         at91_set_A_periph(AT91_PIN_PB24, 0);    /* ETX1 */
 138         at91_set_A_periph(AT91_PIN_PB30, 0);    /* EMDIO */
 139         at91_set_A_periph(AT91_PIN_PB29, 0);    /* EMDC */
 140
 141         if (!data->is_rmii) {
 142                 at91_set_B_periph(AT91_PIN_PC25, 0);    /* ECRS */
 143                 at91_set_B_periph(AT91_PIN_PC26, 0);    /* ECOL */
 144                 at91_set_B_periph(AT91_PIN_PC22, 0);    /* ERX2 */
 145                 at91_set_B_periph(AT91_PIN_PC23, 0);    /* ERX3 */
 146                 at91_set_B_periph(AT91_PIN_PC27, 0);    /* ERXCK */
 147                 at91_set_B_periph(AT91_PIN_PC20, 0);    /* ETX2 */
 148                 at91_set_B_periph(AT91_PIN_PC21, 0);    /* ETX3 */
 149                 at91_set_B_periph(AT91_PIN_PC24, 0);    /* ETXER */
 150         }
 151
 152         eth_data = *data;
 153         platform_device_register(&at91cap9_eth_device);
 154 }
 155 #else
 156 void __init at91_add_device_eth(struct at91_eth_data *data) {}
 157 #endif
 158
 159
 160 /* --------------------------------------------------------------------
 161  *  MMC / SD
 162  * -------------------------------------------------------------------- */
 163
 164 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
 165 static u64 mmc_dmamask = DMA_BIT_MASK(32);
 166 static struct at91_mmc_data mmc0_data, mmc1_data;
 167
 168 static struct resource mmc0_resources[] = {
 169         [0] = {
 170                 .start  = AT91CAP9_BASE_MCI0,
 171                 .end    = AT91CAP9_BASE_MCI0 + SZ_16K - 1,
 172                 .flags  = IORESOURCE_MEM,
 173         },
 174         [1] = {
 175                 .start  = AT91CAP9_ID_MCI0,
 176                 .end    = AT91CAP9_ID_MCI0,
 177                 .flags  = IORESOURCE_IRQ,
 178         },
 179 };
 180
 181 static struct platform_device at91cap9_mmc0_device = {
 182         .name           = "at91_mci",
 183         .id             = 0,
 184         .dev            = {
 185                                 .dma_mask               = &mmc_dmamask,
 186                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 187                                 .platform_data          = &mmc0_data,
 188         },
 189         .resource       = mmc0_resources,
 190         .num_resources  = ARRAY_SIZE(mmc0_resources),
 191 };
 192
 193 static struct resource mmc1_resources[] = {
 194         [0] = {
 195                 .start  = AT91CAP9_BASE_MCI1,
 196                 .end    = AT91CAP9_BASE_MCI1 + SZ_16K - 1,
 197                 .flags  = IORESOURCE_MEM,
 198         },
 199         [1] = {
 200                 .start  = AT91CAP9_ID_MCI1,
 201                 .end    = AT91CAP9_ID_MCI1,
 202                 .flags  = IORESOURCE_IRQ,
 203         },
 204 };
 205
 206 static struct platform_device at91cap9_mmc1_device = {
 207         .name           = "at91_mci",
 208         .id             = 1,
 209         .dev            = {
 210                                 .dma_mask               = &mmc_dmamask,
 211                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 212                                 .platform_data          = &mmc1_data,
 213         },
 214         .resource       = mmc1_resources,
 215         .num_resources  = ARRAY_SIZE(mmc1_resources),
 216 };
 217
 218 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
 219 {
 220         if (!data)
 221                 return;
 222
 223         /* input/irq */
 224         if (data->det_pin) {
 225                 at91_set_gpio_input(data->det_pin, 1);
 226                 at91_set_deglitch(data->det_pin, 1);
 227         }
 228         if (data->wp_pin)
 229                 at91_set_gpio_input(data->wp_pin, 1);
 230         if (data->vcc_pin)
 231                 at91_set_gpio_output(data->vcc_pin, 0);
 232
 233         if (mmc_id == 0) {              /* MCI0 */
 234                 /* CLK */
 235                 at91_set_A_periph(AT91_PIN_PA2, 0);
 236
 237                 /* CMD */
 238                 at91_set_A_periph(AT91_PIN_PA1, 1);
 239
 240                 /* DAT0, maybe DAT1..DAT3 */
 241                 at91_set_A_periph(AT91_PIN_PA0, 1);
 242                 if (data->wire4) {
 243                         at91_set_A_periph(AT91_PIN_PA3, 1);
 244                         at91_set_A_periph(AT91_PIN_PA4, 1);
 245                         at91_set_A_periph(AT91_PIN_PA5, 1);
 246                 }
 247
 248                 mmc0_data = *data;
 249                 at91_clock_associate("mci0_clk", &at91cap9_mmc1_device.dev, "mci_clk");
 250                 platform_device_register(&at91cap9_mmc0_device);
 251         } else {                        /* MCI1 */
 252                 /* CLK */
 253                 at91_set_A_periph(AT91_PIN_PA16, 0);
 254
 255                 /* CMD */
 256                 at91_set_A_periph(AT91_PIN_PA17, 1);
 257
 258                 /* DAT0, maybe DAT1..DAT3 */
 259                 at91_set_A_periph(AT91_PIN_PA18, 1);
 260                 if (data->wire4) {
 261                         at91_set_A_periph(AT91_PIN_PA19, 1);
 262                         at91_set_A_periph(AT91_PIN_PA20, 1);
 263                         at91_set_A_periph(AT91_PIN_PA21, 1);
 264                 }
 265
 266                 mmc1_data = *data;
 267                 at91_clock_associate("mci1_clk", &at91cap9_mmc1_device.dev, "mci_clk");
 268                 platform_device_register(&at91cap9_mmc1_device);
 269         }
 270 }
 271 #else
 272 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
 273 #endif
 274
 275
 276 /* --------------------------------------------------------------------
 277  *  NAND / SmartMedia
 278  * -------------------------------------------------------------------- */
 279
 280 #if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
 281 static struct at91_nand_data nand_data;
 282
 283 #define NAND_BASE       AT91_CHIPSELECT_3
 284
 285 static struct resource nand_resources[] = {
 286         [0] = {
 287                 .start  = NAND_BASE,
 288                 .end    = NAND_BASE + SZ_256M - 1,
 289                 .flags  = IORESOURCE_MEM,
 290         },
 291         [1] = {
 292                 .start  = AT91_BASE_SYS + AT91_ECC,
 293                 .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
 294                 .flags  = IORESOURCE_MEM,
 295         }
 296 };
 297
 298 static struct platform_device at91cap9_nand_device = {
 299         .name           = "at91_nand",
 300         .id             = -1,
 301         .dev            = {
 302                                 .platform_data  = &nand_data,
 303         },
 304         .resource       = nand_resources,
 305         .num_resources  = ARRAY_SIZE(nand_resources),
 306 };
 307
 308 void __init at91_add_device_nand(struct at91_nand_data *data)
 309 {
 310         unsigned long csa, mode;
 311
 312         if (!data)
 313                 return;
 314
 315         csa = at91_sys_read(AT91_MATRIX_EBICSA);
 316         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
 317
 318         /* set the bus interface characteristics */
 319         at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1)
 320                         | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
 321
 322         at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6)
 323                         | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
 324
 325         at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
 326
 327         if (data->bus_width_16)
 328                 mode = AT91_SMC_DBW_16;
 329         else
 330                 mode = AT91_SMC_DBW_8;
 331         at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
 332
 333         /* enable pin */
 334         if (data->enable_pin)
 335                 at91_set_gpio_output(data->enable_pin, 1);
 336
 337         /* ready/busy pin */
 338         if (data->rdy_pin)
 339                 at91_set_gpio_input(data->rdy_pin, 1);
 340
 341         /* card detect pin */
 342         if (data->det_pin)
 343                 at91_set_gpio_input(data->det_pin, 1);
 344
 345         nand_data = *data;
 346         platform_device_register(&at91cap9_nand_device);
 347 }
 348 #else
 349 void __init at91_add_device_nand(struct at91_nand_data *data) {}
 350 #endif
 351
 352 /* --------------------------------------------------------------------
 353  *  TWI (i2c)
 354  * -------------------------------------------------------------------- */
 355
 356 /*
 357  * Prefer the GPIO code since the TWI controller isn't robust
 358  * (gets overruns and underruns under load) and can only issue
 359  * repeated STARTs in one scenario (the driver doesn't yet handle them).
 360  */
 361 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
 362
 363 static struct i2c_gpio_platform_data pdata = {
 364         .sda_pin                = AT91_PIN_PB4,
 365         .sda_is_open_drain      = 1,
 366         .scl_pin                = AT91_PIN_PB5,
 367         .scl_is_open_drain      = 1,
 368         .udelay                 = 2,            /* ~100 kHz */
 369 };
 370
 371 static struct platform_device at91cap9_twi_device = {
 372         .name                   = "i2c-gpio",
 373         .id                     = -1,
 374         .dev.platform_data      = &pdata,
 375 };
 376
 377 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
 378 {
 379         at91_set_GPIO_periph(AT91_PIN_PB4, 1);          /* TWD (SDA) */
 380         at91_set_multi_drive(AT91_PIN_PB4, 1);
 381
 382         at91_set_GPIO_periph(AT91_PIN_PB5, 1);          /* TWCK (SCL) */
 383         at91_set_multi_drive(AT91_PIN_PB5, 1);
 384
 385         i2c_register_board_info(0, devices, nr_devices);
 386         platform_device_register(&at91cap9_twi_device);
 387 }
 388
 389 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
 390
 391 static struct resource twi_resources[] = {
 392         [0] = {
 393                 .start  = AT91CAP9_BASE_TWI,
 394                 .end    = AT91CAP9_BASE_TWI + SZ_16K - 1,
 395                 .flags  = IORESOURCE_MEM,
 396         },
 397         [1] = {
 398                 .start  = AT91CAP9_ID_TWI,
 399                 .end    = AT91CAP9_ID_TWI,
 400                 .flags  = IORESOURCE_IRQ,
 401         },
 402 };
 403
 404 static struct platform_device at91cap9_twi_device = {
 405         .name           = "at91_i2c",
 406         .id             = -1,
 407         .resource       = twi_resources,
 408         .num_resources  = ARRAY_SIZE(twi_resources),
 409 };
 410
 411 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
 412 {
 413         /* pins used for TWI interface */
 414         at91_set_B_periph(AT91_PIN_PB4, 0);             /* TWD */
 415         at91_set_multi_drive(AT91_PIN_PB4, 1);
 416
 417         at91_set_B_periph(AT91_PIN_PB5, 0);             /* TWCK */
 418         at91_set_multi_drive(AT91_PIN_PB5, 1);
 419
 420         i2c_register_board_info(0, devices, nr_devices);
 421         platform_device_register(&at91cap9_twi_device);
 422 }
 423 #else
 424 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
 425 #endif
 426
 427 /* --------------------------------------------------------------------
 428  *  SPI
 429  * -------------------------------------------------------------------- */
 430
 431 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
 432 static u64 spi_dmamask = DMA_BIT_MASK(32);
 433
 434 static struct resource spi0_resources[] = {
 435         [0] = {
 436                 .start  = AT91CAP9_BASE_SPI0,
 437                 .end    = AT91CAP9_BASE_SPI0 + SZ_16K - 1,
 438                 .flags  = IORESOURCE_MEM,
 439         },
 440         [1] = {
 441                 .start  = AT91CAP9_ID_SPI0,
 442                 .end    = AT91CAP9_ID_SPI0,
 443                 .flags  = IORESOURCE_IRQ,
 444         },
 445 };
 446
 447 static struct platform_device at91cap9_spi0_device = {
 448         .name           = "atmel_spi",
 449         .id             = 0,
 450         .dev            = {
 451                                 .dma_mask               = &spi_dmamask,
 452                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 453         },
 454         .resource       = spi0_resources,
 455         .num_resources  = ARRAY_SIZE(spi0_resources),
 456 };
 457
 458 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PD0, AT91_PIN_PD1 };
 459
 460 static struct resource spi1_resources[] = {
 461         [0] = {
 462                 .start  = AT91CAP9_BASE_SPI1,
 463                 .end    = AT91CAP9_BASE_SPI1 + SZ_16K - 1,
 464                 .flags  = IORESOURCE_MEM,
 465         },
 466         [1] = {
 467                 .start  = AT91CAP9_ID_SPI1,
 468                 .end    = AT91CAP9_ID_SPI1,
 469                 .flags  = IORESOURCE_IRQ,
 470         },
 471 };
 472
 473 static struct platform_device at91cap9_spi1_device = {
 474         .name           = "atmel_spi",
 475         .id             = 1,
 476         .dev            = {
 477                                 .dma_mask               = &spi_dmamask,
 478                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 479         },
 480         .resource       = spi1_resources,
 481         .num_resources  = ARRAY_SIZE(spi1_resources),
 482 };
 483
 484 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
 485
 486 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 487 {
 488         int i;
 489         unsigned long cs_pin;
 490         short enable_spi0 = 0;
 491         short enable_spi1 = 0;
 492
 493         /* Choose SPI chip-selects */
 494         for (i = 0; i < nr_devices; i++) {
 495                 if (devices[i].controller_data)
 496                         cs_pin = (unsigned long) devices[i].controller_data;
 497                 else if (devices[i].bus_num == 0)
 498                         cs_pin = spi0_standard_cs[devices[i].chip_select];
 499                 else
 500                         cs_pin = spi1_standard_cs[devices[i].chip_select];
 501
 502                 if (devices[i].bus_num == 0)
 503                         enable_spi0 = 1;
 504                 else
 505                         enable_spi1 = 1;
 506
 507                 /* enable chip-select pin */
 508                 at91_set_gpio_output(cs_pin, 1);
 509
 510                 /* pass chip-select pin to driver */
 511                 devices[i].controller_data = (void *) cs_pin;
 512         }
 513
 514         spi_register_board_info(devices, nr_devices);
 515
 516         /* Configure SPI bus(es) */
 517         if (enable_spi0) {
 518                 at91_set_B_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
 519                 at91_set_B_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
 520                 at91_set_B_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
 521
 522                 at91_clock_associate("spi0_clk", &at91cap9_spi0_device.dev, "spi_clk");
 523                 platform_device_register(&at91cap9_spi0_device);
 524         }
 525         if (enable_spi1) {
 526                 at91_set_A_periph(AT91_PIN_PB12, 0);    /* SPI1_MISO */
 527                 at91_set_A_periph(AT91_PIN_PB13, 0);    /* SPI1_MOSI */
 528                 at91_set_A_periph(AT91_PIN_PB14, 0);    /* SPI1_SPCK */
 529
 530                 at91_clock_associate("spi1_clk", &at91cap9_spi1_device.dev, "spi_clk");
 531                 platform_device_register(&at91cap9_spi1_device);
 532         }
 533 }
 534 #else
 535 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
 536 #endif
 537
 538
 539 /* --------------------------------------------------------------------
 540  *  RTT
 541  * -------------------------------------------------------------------- */
 542
 543 static struct resource rtt_resources[] = {
 544         {
 545                 .start  = AT91_BASE_SYS + AT91_RTT,
 546                 .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
 547                 .flags  = IORESOURCE_MEM,
 548         }
 549 };
 550
 551 static struct platform_device at91cap9_rtt_device = {
 552         .name           = "at91_rtt",
 553         .id             = 0,
 554         .resource       = rtt_resources,
 555         .num_resources  = ARRAY_SIZE(rtt_resources),
 556 };
 557
 558 static void __init at91_add_device_rtt(void)
 559 {
 560         platform_device_register(&at91cap9_rtt_device);
 561 }
 562
 563
 564 /* --------------------------------------------------------------------
 565  *  Watchdog
 566  * -------------------------------------------------------------------- */
 567
 568 #if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
 569 static struct platform_device at91cap9_wdt_device = {
 570         .name           = "at91_wdt",
 571         .id             = -1,
 572         .num_resources  = 0,
 573 };
 574
 575 static void __init at91_add_device_watchdog(void)
 576 {
 577         platform_device_register(&at91cap9_wdt_device);
 578 }
 579 #else
 580 static void __init at91_add_device_watchdog(void) {}
 581 #endif
 582
 583
 584 /* --------------------------------------------------------------------
 585  *  AC97
 586  * -------------------------------------------------------------------- */
 587
 588 #if defined(CONFIG_SND_AT91_AC97) || defined(CONFIG_SND_AT91_AC97_MODULE)
 589 static u64 ac97_dmamask = DMA_BIT_MASK(32);
 590 static struct atmel_ac97_data ac97_data;
 591
 592 static struct resource ac97_resources[] = {
 593         [0] = {
 594                 .start  = AT91CAP9_BASE_AC97C,
 595                 .end    = AT91CAP9_BASE_AC97C + SZ_16K - 1,
 596                 .flags  = IORESOURCE_MEM,
 597         },
 598         [1] = {
 599                 .start  = AT91CAP9_ID_AC97C,
 600                 .end    = AT91CAP9_ID_AC97C,
 601                 .flags  = IORESOURCE_IRQ,
 602         },
 603 };
 604
 605 static struct platform_device at91cap9_ac97_device = {
 606         .name           = "ac97c",
 607         .id             = 1,
 608         .dev            = {
 609                                 .dma_mask               = &ac97_dmamask,
 610                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 611                                 .platform_data          = &ac97_data,
 612         },
 613         .resource       = ac97_resources,
 614         .num_resources  = ARRAY_SIZE(ac97_resources),
 615 };
 616
 617 void __init at91_add_device_ac97(struct atmel_ac97_data *data)
 618 {
 619         if (!data)
 620                 return;
 621
 622         at91_set_A_periph(AT91_PIN_PA6, 0);     /* AC97FS */
 623         at91_set_A_periph(AT91_PIN_PA7, 0);     /* AC97CK */
 624         at91_set_A_periph(AT91_PIN_PA8, 0);     /* AC97TX */
 625         at91_set_A_periph(AT91_PIN_PA9, 0);     /* AC97RX */
 626
 627         /* reset */
 628         if (data->reset_pin)
 629                 at91_set_gpio_output(data->reset_pin, 0);
 630
 631         ac97_data = *data;
 632         platform_device_register(&at91cap9_ac97_device);
 633 }
 634 #else
 635 void __init at91_add_device_ac97(struct atmel_ac97_data *data) {}
 636 #endif
 637
 638
 639 /* --------------------------------------------------------------------
 640  *  LCD Controller
 641  * -------------------------------------------------------------------- */
 642
 643 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
 644 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
 645 static struct atmel_lcdfb_info lcdc_data;
 646
 647 static struct resource lcdc_resources[] = {
 648         [0] = {
 649                 .start  = AT91CAP9_LCDC_BASE,
 650                 .end    = AT91CAP9_LCDC_BASE + SZ_4K - 1,
 651                 .flags  = IORESOURCE_MEM,
 652         },
 653         [1] = {
 654                 .start  = AT91CAP9_ID_LCDC,
 655                 .end    = AT91CAP9_ID_LCDC,
 656                 .flags  = IORESOURCE_IRQ,
 657         },
 658 };
 659
 660 static struct platform_device at91_lcdc_device = {
 661         .name           = "atmel_lcdfb",
 662         .id             = 0,
 663         .dev            = {
 664                                 .dma_mask               = &lcdc_dmamask,
 665                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 666                                 .platform_data          = &lcdc_data,
 667         },
 668         .resource       = lcdc_resources,
 669         .num_resources  = ARRAY_SIZE(lcdc_resources),
 670 };
 671
 672 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
 673 {
 674         if (!data)
 675                 return;
 676
 677         at91_set_A_periph(AT91_PIN_PC1, 0);     /* LCDHSYNC */
 678         at91_set_A_periph(AT91_PIN_PC2, 0);     /* LCDDOTCK */
 679         at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDDEN */
 680         at91_set_B_periph(AT91_PIN_PB9, 0);     /* LCDCC */
 681         at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDD2 */
 682         at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDD3 */
 683         at91_set_A_periph(AT91_PIN_PC8, 0);     /* LCDD4 */
 684         at91_set_A_periph(AT91_PIN_PC9, 0);     /* LCDD5 */
 685         at91_set_A_periph(AT91_PIN_PC10, 0);    /* LCDD6 */
 686         at91_set_A_periph(AT91_PIN_PC11, 0);    /* LCDD7 */
 687         at91_set_A_periph(AT91_PIN_PC14, 0);    /* LCDD10 */
 688         at91_set_A_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
 689         at91_set_A_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
 690         at91_set_A_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
 691         at91_set_A_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
 692         at91_set_A_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
 693         at91_set_A_periph(AT91_PIN_PC22, 0);    /* LCDD18 */
 694         at91_set_A_periph(AT91_PIN_PC23, 0);    /* LCDD19 */
 695         at91_set_A_periph(AT91_PIN_PC24, 0);    /* LCDD20 */
 696         at91_set_A_periph(AT91_PIN_PC25, 0);    /* LCDD21 */
 697         at91_set_A_periph(AT91_PIN_PC26, 0);    /* LCDD22 */
 698         at91_set_A_periph(AT91_PIN_PC27, 0);    /* LCDD23 */
 699
 700         lcdc_data = *data;
 701         platform_device_register(&at91_lcdc_device);
 702 }
 703 #else
 704 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
 705 #endif
 706
 707
 708 /* --------------------------------------------------------------------
 709  *  SSC -- Synchronous Serial Controller
 710  * -------------------------------------------------------------------- */
 711
 712 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
 713 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
 714
 715 static struct resource ssc0_resources[] = {
 716         [0] = {
 717                 .start  = AT91CAP9_BASE_SSC0,
 718                 .end    = AT91CAP9_BASE_SSC0 + SZ_16K - 1,
 719                 .flags  = IORESOURCE_MEM,
 720         },
 721         [1] = {
 722                 .start  = AT91CAP9_ID_SSC0,
 723                 .end    = AT91CAP9_ID_SSC0,
 724                 .flags  = IORESOURCE_IRQ,
 725         },
 726 };
 727
 728 static struct platform_device at91cap9_ssc0_device = {
 729         .name   = "ssc",
 730         .id     = 0,
 731         .dev    = {
 732                 .dma_mask               = &ssc0_dmamask,
 733                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 734         },
 735         .resource       = ssc0_resources,
 736         .num_resources  = ARRAY_SIZE(ssc0_resources),
 737 };
 738
 739 static inline void configure_ssc0_pins(unsigned pins)
 740 {
 741         if (pins & ATMEL_SSC_TF)
 742                 at91_set_A_periph(AT91_PIN_PB0, 1);
 743         if (pins & ATMEL_SSC_TK)
 744                 at91_set_A_periph(AT91_PIN_PB1, 1);
 745         if (pins & ATMEL_SSC_TD)
 746                 at91_set_A_periph(AT91_PIN_PB2, 1);
 747         if (pins & ATMEL_SSC_RD)
 748                 at91_set_A_periph(AT91_PIN_PB3, 1);
 749         if (pins & ATMEL_SSC_RK)
 750                 at91_set_A_periph(AT91_PIN_PB4, 1);
 751         if (pins & ATMEL_SSC_RF)
 752                 at91_set_A_periph(AT91_PIN_PB5, 1);
 753 }
 754
 755 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
 756
 757 static struct resource ssc1_resources[] = {
 758         [0] = {
 759                 .start  = AT91CAP9_BASE_SSC1,
 760                 .end    = AT91CAP9_BASE_SSC1 + SZ_16K - 1,
 761                 .flags  = IORESOURCE_MEM,
 762         },
 763         [1] = {
 764                 .start  = AT91CAP9_ID_SSC1,
 765                 .end    = AT91CAP9_ID_SSC1,
 766                 .flags  = IORESOURCE_IRQ,
 767         },
 768 };
 769
 770 static struct platform_device at91cap9_ssc1_device = {
 771         .name   = "ssc",
 772         .id     = 1,
 773         .dev    = {
 774                 .dma_mask               = &ssc1_dmamask,
 775                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 776         },
 777         .resource       = ssc1_resources,
 778         .num_resources  = ARRAY_SIZE(ssc1_resources),
 779 };
 780
 781 static inline void configure_ssc1_pins(unsigned pins)
 782 {
 783         if (pins & ATMEL_SSC_TF)
 784                 at91_set_A_periph(AT91_PIN_PB6, 1);
 785         if (pins & ATMEL_SSC_TK)
 786                 at91_set_A_periph(AT91_PIN_PB7, 1);
 787         if (pins & ATMEL_SSC_TD)
 788                 at91_set_A_periph(AT91_PIN_PB8, 1);
 789         if (pins & ATMEL_SSC_RD)
 790                 at91_set_A_periph(AT91_PIN_PB9, 1);
 791         if (pins & ATMEL_SSC_RK)
 792                 at91_set_A_periph(AT91_PIN_PB10, 1);
 793         if (pins & ATMEL_SSC_RF)
 794                 at91_set_A_periph(AT91_PIN_PB11, 1);
 795 }
 796
 797 /*
 798  * SSC controllers are accessed through library code, instead of any
 799  * kind of all-singing/all-dancing driver.  For example one could be
 800  * used by a particular I2S audio codec's driver, while another one
 801  * on the same system might be used by a custom data capture driver.
 802  */
 803 void __init at91_add_device_ssc(unsigned id, unsigned pins)
 804 {
 805         struct platform_device *pdev;
 806
 807         /*
 808          * NOTE: caller is responsible for passing information matching
 809          * "pins" to whatever will be using each particular controller.
 810          */
 811         switch (id) {
 812         case AT91CAP9_ID_SSC0:
 813                 pdev = &at91cap9_ssc0_device;
 814                 configure_ssc0_pins(pins);
 815                 at91_clock_associate("ssc0_clk", &pdev->dev, "ssc");
 816                 break;
 817         case AT91CAP9_ID_SSC1:
 818                 pdev = &at91cap9_ssc1_device;
 819                 configure_ssc1_pins(pins);
 820                 at91_clock_associate("ssc1_clk", &pdev->dev, "ssc");
 821                 break;
 822         default:
 823                 return;
 824         }
 825
 826         platform_device_register(pdev);
 827 }
 828
 829 #else
 830 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
 831 #endif
 832
 833
 834 /* --------------------------------------------------------------------
 835  *  UART
 836  * -------------------------------------------------------------------- */
 837
 838 #if defined(CONFIG_SERIAL_ATMEL)
 839 static struct resource dbgu_resources[] = {
 840         [0] = {
 841                 .start  = AT91_VA_BASE_SYS + AT91_DBGU,
 842                 .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
 843                 .flags  = IORESOURCE_MEM,
 844         },
 845         [1] = {
 846                 .start  = AT91_ID_SYS,
 847                 .end    = AT91_ID_SYS,
 848                 .flags  = IORESOURCE_IRQ,
 849         },
 850 };
 851
 852 static struct atmel_uart_data dbgu_data = {
 853         .use_dma_tx     = 0,
 854         .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
 855         .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
 856 };
 857
 858 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
 859
 860 static struct platform_device at91cap9_dbgu_device = {
 861         .name           = "atmel_usart",
 862         .id             = 0,
 863         .dev            = {
 864                                 .dma_mask               = &dbgu_dmamask,
 865                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 866                                 .platform_data          = &dbgu_data,
 867         },
 868         .resource       = dbgu_resources,
 869         .num_resources  = ARRAY_SIZE(dbgu_resources),
 870 };
 871
 872 static inline void configure_dbgu_pins(void)
 873 {
 874         at91_set_A_periph(AT91_PIN_PC30, 0);            /* DRXD */
 875         at91_set_A_periph(AT91_PIN_PC31, 1);            /* DTXD */
 876 }
 877
 878 static struct resource uart0_resources[] = {
 879         [0] = {
 880                 .start  = AT91CAP9_BASE_US0,
 881                 .end    = AT91CAP9_BASE_US0 + SZ_16K - 1,
 882                 .flags  = IORESOURCE_MEM,
 883         },
 884         [1] = {
 885                 .start  = AT91CAP9_ID_US0,
 886                 .end    = AT91CAP9_ID_US0,
 887                 .flags  = IORESOURCE_IRQ,
 888         },
 889 };
 890
 891 static struct atmel_uart_data uart0_data = {
 892         .use_dma_tx     = 1,
 893         .use_dma_rx     = 1,
 894 };
 895
 896 static u64 uart0_dmamask = DMA_BIT_MASK(32);
 897
 898 static struct platform_device at91cap9_uart0_device = {
 899         .name           = "atmel_usart",
 900         .id             = 1,
 901         .dev            = {
 902                                 .dma_mask               = &uart0_dmamask,
 903                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 904                                 .platform_data          = &uart0_data,
 905         },
 906         .resource       = uart0_resources,
 907         .num_resources  = ARRAY_SIZE(uart0_resources),
 908 };
 909
 910 static inline void configure_usart0_pins(unsigned pins)
 911 {
 912         at91_set_A_periph(AT91_PIN_PA22, 1);            /* TXD0 */
 913         at91_set_A_periph(AT91_PIN_PA23, 0);            /* RXD0 */
 914
 915         if (pins & ATMEL_UART_RTS)
 916                 at91_set_A_periph(AT91_PIN_PA24, 0);    /* RTS0 */
 917         if (pins & ATMEL_UART_CTS)
 918                 at91_set_A_periph(AT91_PIN_PA25, 0);    /* CTS0 */
 919 }
 920
 921 static struct resource uart1_resources[] = {
 922         [0] = {
 923                 .start  = AT91CAP9_BASE_US1,
 924                 .end    = AT91CAP9_BASE_US1 + SZ_16K - 1,
 925                 .flags  = IORESOURCE_MEM,
 926         },
 927         [1] = {
 928                 .start  = AT91CAP9_ID_US1,
 929                 .end    = AT91CAP9_ID_US1,
 930                 .flags  = IORESOURCE_IRQ,
 931         },
 932 };
 933
 934 static struct atmel_uart_data uart1_data = {
 935         .use_dma_tx     = 1,
 936         .use_dma_rx     = 1,
 937 };
 938
 939 static u64 uart1_dmamask = DMA_BIT_MASK(32);
 940
 941 static struct platform_device at91cap9_uart1_device = {
 942         .name           = "atmel_usart",
 943         .id             = 2,
 944         .dev            = {
 945                                 .dma_mask               = &uart1_dmamask,
 946                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 947                                 .platform_data          = &uart1_data,
 948         },
 949         .resource       = uart1_resources,
 950         .num_resources  = ARRAY_SIZE(uart1_resources),
 951 };
 952
 953 static inline void configure_usart1_pins(unsigned pins)
 954 {
 955         at91_set_A_periph(AT91_PIN_PD0, 1);             /* TXD1 */
 956         at91_set_A_periph(AT91_PIN_PD1, 0);             /* RXD1 */
 957
 958         if (pins & ATMEL_UART_RTS)
 959                 at91_set_B_periph(AT91_PIN_PD7, 0);     /* RTS1 */
 960         if (pins & ATMEL_UART_CTS)
 961                 at91_set_B_periph(AT91_PIN_PD8, 0);     /* CTS1 */
 962 }
 963
 964 static struct resource uart2_resources[] = {
 965         [0] = {
 966                 .start  = AT91CAP9_BASE_US2,
 967                 .end    = AT91CAP9_BASE_US2 + SZ_16K - 1,
 968                 .flags  = IORESOURCE_MEM,
 969         },
 970         [1] = {
 971                 .start  = AT91CAP9_ID_US2,
 972                 .end    = AT91CAP9_ID_US2,
 973                 .flags  = IORESOURCE_IRQ,
 974         },
 975 };
 976
 977 static struct atmel_uart_data uart2_data = {
 978         .use_dma_tx     = 1,
 979         .use_dma_rx     = 1,
 980 };
 981
 982 static u64 uart2_dmamask = DMA_BIT_MASK(32);
 983
 984 static struct platform_device at91cap9_uart2_device = {
 985         .name           = "atmel_usart",
 986         .id             = 3,
 987         .dev            = {
 988                                 .dma_mask               = &uart2_dmamask,
 989                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 990                                 .platform_data          = &uart2_data,
 991         },
 992         .resource       = uart2_resources,
 993         .num_resources  = ARRAY_SIZE(uart2_resources),
 994 };
 995
 996 static inline void configure_usart2_pins(unsigned pins)
 997 {
 998         at91_set_A_periph(AT91_PIN_PD2, 1);             /* TXD2 */
 999         at91_set_A_periph(AT91_PIN_PD3, 0);             /* RXD2 */
1000
1001         if (pins & ATMEL_UART_RTS)
1002                 at91_set_B_periph(AT91_PIN_PD5, 0);     /* RTS2 */
1003         if (pins & ATMEL_UART_CTS)
1004                 at91_set_B_periph(AT91_PIN_PD6, 0);     /* CTS2 */
1005 }
1006
1007 static struct platform_device *at91_uarts[ATMEL_MAX_UART];      /* the UARTs to use */
1008 struct platform_device *atmel_default_console_device;   /* the serial console device */
1009
1010 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1011 {
1012         struct platform_device *pdev;
1013
1014         switch (id) {
1015                 case 0:         /* DBGU */
1016                         pdev = &at91cap9_dbgu_device;
1017                         configure_dbgu_pins();
1018                         at91_clock_associate("mck", &pdev->dev, "usart");
1019                         break;
1020                 case AT91CAP9_ID_US0:
1021                         pdev = &at91cap9_uart0_device;
1022                         configure_usart0_pins(pins);
1023                         at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1024                         break;
1025                 case AT91CAP9_ID_US1:
1026                         pdev = &at91cap9_uart1_device;
1027                         configure_usart1_pins(pins);
1028                         at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1029                         break;
1030                 case AT91CAP9_ID_US2:
1031                         pdev = &at91cap9_uart2_device;
1032                         configure_usart2_pins(pins);
1033                         at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1034                         break;
1035                 default:
1036                         return;
1037         }
1038         pdev->id = portnr;              /* update to mapped ID */
1039
1040         if (portnr < ATMEL_MAX_UART)
1041                 at91_uarts[portnr] = pdev;
1042 }
1043
1044 void __init at91_set_serial_console(unsigned portnr)
1045 {
1046         if (portnr < ATMEL_MAX_UART)
1047                 atmel_default_console_device = at91_uarts[portnr];
1048         if (!atmel_default_console_device)
1049                 printk(KERN_INFO "AT91: No default serial console defined.\n");
1050 }
1051
1052 void __init at91_add_device_serial(void)
1053 {
1054         int i;
1055
1056         for (i = 0; i < ATMEL_MAX_UART; i++) {
1057                 if (at91_uarts[i])
1058                         platform_device_register(at91_uarts[i]);
1059         }
1060 }
1061 #else
1062 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1063 void __init at91_set_serial_console(unsigned portnr) {}
1064 void __init at91_add_device_serial(void) {}
1065 #endif
1066
1067
1068 /* -------------------------------------------------------------------- */
1069 /*
1070  * These devices are always present and don't need any board-specific
1071  * setup.
1072  */
1073 static int __init at91_add_standard_devices(void)
1074 {
1075         at91_add_device_rtt();
1076         at91_add_device_watchdog();
1077         return 0;
1078 }
1079
1080 arch_initcall(at91_add_standard_devices);