2 * arch/arm/mach-at91/at91rm9200.c
4 * Copyright (C) 2005 SAN People
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/reboot.h>
15 #include <linux/clk/at91_pmc.h>
18 #include <asm/mach/arch.h>
19 #include <asm/mach/map.h>
20 #include <asm/system_misc.h>
21 #include <mach/at91rm9200.h>
22 #include <mach/at91_st.h>
24 #include <mach/hardware.h>
33 /* --------------------------------------------------------------------
35 * -------------------------------------------------------------------- */
38 * The peripheral clocks.
40 static struct clk udc_clk = {
42 .pmc_mask = 1 << AT91RM9200_ID_UDP,
43 .type = CLK_TYPE_PERIPHERAL,
45 static struct clk ohci_clk = {
47 .pmc_mask = 1 << AT91RM9200_ID_UHP,
48 .type = CLK_TYPE_PERIPHERAL,
50 static struct clk ether_clk = {
52 .pmc_mask = 1 << AT91RM9200_ID_EMAC,
53 .type = CLK_TYPE_PERIPHERAL,
55 static struct clk mmc_clk = {
57 .pmc_mask = 1 << AT91RM9200_ID_MCI,
58 .type = CLK_TYPE_PERIPHERAL,
60 static struct clk twi_clk = {
62 .pmc_mask = 1 << AT91RM9200_ID_TWI,
63 .type = CLK_TYPE_PERIPHERAL,
65 static struct clk usart0_clk = {
67 .pmc_mask = 1 << AT91RM9200_ID_US0,
68 .type = CLK_TYPE_PERIPHERAL,
70 static struct clk usart1_clk = {
72 .pmc_mask = 1 << AT91RM9200_ID_US1,
73 .type = CLK_TYPE_PERIPHERAL,
75 static struct clk usart2_clk = {
77 .pmc_mask = 1 << AT91RM9200_ID_US2,
78 .type = CLK_TYPE_PERIPHERAL,
80 static struct clk usart3_clk = {
82 .pmc_mask = 1 << AT91RM9200_ID_US3,
83 .type = CLK_TYPE_PERIPHERAL,
85 static struct clk spi_clk = {
87 .pmc_mask = 1 << AT91RM9200_ID_SPI,
88 .type = CLK_TYPE_PERIPHERAL,
90 static struct clk pioA_clk = {
92 .pmc_mask = 1 << AT91RM9200_ID_PIOA,
93 .type = CLK_TYPE_PERIPHERAL,
95 static struct clk pioB_clk = {
97 .pmc_mask = 1 << AT91RM9200_ID_PIOB,
98 .type = CLK_TYPE_PERIPHERAL,
100 static struct clk pioC_clk = {
102 .pmc_mask = 1 << AT91RM9200_ID_PIOC,
103 .type = CLK_TYPE_PERIPHERAL,
105 static struct clk pioD_clk = {
107 .pmc_mask = 1 << AT91RM9200_ID_PIOD,
108 .type = CLK_TYPE_PERIPHERAL,
110 static struct clk ssc0_clk = {
112 .pmc_mask = 1 << AT91RM9200_ID_SSC0,
113 .type = CLK_TYPE_PERIPHERAL,
115 static struct clk ssc1_clk = {
117 .pmc_mask = 1 << AT91RM9200_ID_SSC1,
118 .type = CLK_TYPE_PERIPHERAL,
120 static struct clk ssc2_clk = {
122 .pmc_mask = 1 << AT91RM9200_ID_SSC2,
123 .type = CLK_TYPE_PERIPHERAL,
125 static struct clk tc0_clk = {
127 .pmc_mask = 1 << AT91RM9200_ID_TC0,
128 .type = CLK_TYPE_PERIPHERAL,
130 static struct clk tc1_clk = {
132 .pmc_mask = 1 << AT91RM9200_ID_TC1,
133 .type = CLK_TYPE_PERIPHERAL,
135 static struct clk tc2_clk = {
137 .pmc_mask = 1 << AT91RM9200_ID_TC2,
138 .type = CLK_TYPE_PERIPHERAL,
140 static struct clk tc3_clk = {
142 .pmc_mask = 1 << AT91RM9200_ID_TC3,
143 .type = CLK_TYPE_PERIPHERAL,
145 static struct clk tc4_clk = {
147 .pmc_mask = 1 << AT91RM9200_ID_TC4,
148 .type = CLK_TYPE_PERIPHERAL,
150 static struct clk tc5_clk = {
152 .pmc_mask = 1 << AT91RM9200_ID_TC5,
153 .type = CLK_TYPE_PERIPHERAL,
156 static struct clk *periph_clocks[] __initdata = {
183 static struct clk_lookup periph_clocks_lookups[] = {
184 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
185 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
186 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
187 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
188 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
189 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
190 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
191 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
192 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
193 CLKDEV_CON_DEV_ID("pclk", "fffd0000.ssc", &ssc0_clk),
194 CLKDEV_CON_DEV_ID("pclk", "fffd4000.ssc", &ssc1_clk),
195 CLKDEV_CON_DEV_ID("pclk", "fffd8000.ssc", &ssc2_clk),
196 CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200.0", &twi_clk),
197 /* fake hclk clock */
198 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
199 CLKDEV_CON_ID("pioA", &pioA_clk),
200 CLKDEV_CON_ID("pioB", &pioB_clk),
201 CLKDEV_CON_ID("pioC", &pioC_clk),
202 CLKDEV_CON_ID("pioD", &pioD_clk),
203 /* usart lookup table for DT entries */
204 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
205 CLKDEV_CON_DEV_ID("usart", "fffc0000.serial", &usart0_clk),
206 CLKDEV_CON_DEV_ID("usart", "fffc4000.serial", &usart1_clk),
207 CLKDEV_CON_DEV_ID("usart", "fffc8000.serial", &usart2_clk),
208 CLKDEV_CON_DEV_ID("usart", "fffcc000.serial", &usart3_clk),
209 /* tc lookup table for DT entries */
210 CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
211 CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
212 CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
213 CLKDEV_CON_DEV_ID("t0_clk", "fffa4000.timer", &tc3_clk),
214 CLKDEV_CON_DEV_ID("t1_clk", "fffa4000.timer", &tc4_clk),
215 CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk),
216 CLKDEV_CON_DEV_ID("mci_clk", "fffb4000.mmc", &mmc_clk),
217 CLKDEV_CON_DEV_ID("emac_clk", "fffbc000.ethernet", ðer_clk),
218 CLKDEV_CON_DEV_ID(NULL, "fffb8000.i2c", &twi_clk),
219 CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk),
220 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
221 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
222 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
223 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
226 static struct clk_lookup usart_clocks_lookups[] = {
227 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
228 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
229 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
230 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
231 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
235 * The four programmable clocks.
236 * You must configure pin multiplexing to bring these signals out.
238 static struct clk pck0 = {
240 .pmc_mask = AT91_PMC_PCK0,
241 .type = CLK_TYPE_PROGRAMMABLE,
244 static struct clk pck1 = {
246 .pmc_mask = AT91_PMC_PCK1,
247 .type = CLK_TYPE_PROGRAMMABLE,
250 static struct clk pck2 = {
252 .pmc_mask = AT91_PMC_PCK2,
253 .type = CLK_TYPE_PROGRAMMABLE,
256 static struct clk pck3 = {
258 .pmc_mask = AT91_PMC_PCK3,
259 .type = CLK_TYPE_PROGRAMMABLE,
263 static void __init at91rm9200_register_clocks(void)
267 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
268 clk_register(periph_clocks[i]);
270 clkdev_add_table(periph_clocks_lookups,
271 ARRAY_SIZE(periph_clocks_lookups));
272 clkdev_add_table(usart_clocks_lookups,
273 ARRAY_SIZE(usart_clocks_lookups));
281 /* --------------------------------------------------------------------
283 * -------------------------------------------------------------------- */
285 static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
287 .id = AT91RM9200_ID_PIOA,
288 .regbase = AT91RM9200_BASE_PIOA,
290 .id = AT91RM9200_ID_PIOB,
291 .regbase = AT91RM9200_BASE_PIOB,
293 .id = AT91RM9200_ID_PIOC,
294 .regbase = AT91RM9200_BASE_PIOC,
296 .id = AT91RM9200_ID_PIOD,
297 .regbase = AT91RM9200_BASE_PIOD,
301 static void at91rm9200_idle(void)
304 * Disable the processor clock. The processor will be automatically
305 * re-enabled by an interrupt or by a reset.
307 at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
310 static void at91rm9200_restart(enum reboot_mode reboot_mode, const char *cmd)
313 * Perform a hardware reset with the use of the Watchdog timer.
315 at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
316 at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
319 /* --------------------------------------------------------------------
320 * AT91RM9200 processor initialization
321 * -------------------------------------------------------------------- */
322 static void __init at91rm9200_map_io(void)
324 /* Map peripherals */
325 at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE);
328 static void __init at91rm9200_ioremap_registers(void)
330 at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
331 at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
332 at91_pm_set_standby(at91rm9200_standby);
335 static void __init at91rm9200_initialize(void)
337 arm_pm_idle = at91rm9200_idle;
338 arm_pm_restart = at91rm9200_restart;
340 /* Initialize GPIO subsystem */
341 at91_gpio_init(at91rm9200_gpio,
342 cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
346 /* --------------------------------------------------------------------
347 * Interrupt initialization
348 * -------------------------------------------------------------------- */
351 * The default interrupt priority levels (0 = lowest, 7 = highest).
353 static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
354 7, /* Advanced Interrupt Controller (FIQ) */
355 7, /* System Peripherals */
356 1, /* Parallel IO Controller A */
357 1, /* Parallel IO Controller B */
358 1, /* Parallel IO Controller C */
359 1, /* Parallel IO Controller D */
364 0, /* Multimedia Card Interface */
365 2, /* USB Device Port */
366 6, /* Two-Wire Interface */
367 5, /* Serial Peripheral Interface */
368 4, /* Serial Synchronous Controller 0 */
369 4, /* Serial Synchronous Controller 1 */
370 4, /* Serial Synchronous Controller 2 */
371 0, /* Timer Counter 0 */
372 0, /* Timer Counter 1 */
373 0, /* Timer Counter 2 */
374 0, /* Timer Counter 3 */
375 0, /* Timer Counter 4 */
376 0, /* Timer Counter 5 */
377 2, /* USB Host port */
378 3, /* Ethernet MAC */
379 0, /* Advanced Interrupt Controller (IRQ0) */
380 0, /* Advanced Interrupt Controller (IRQ1) */
381 0, /* Advanced Interrupt Controller (IRQ2) */
382 0, /* Advanced Interrupt Controller (IRQ3) */
383 0, /* Advanced Interrupt Controller (IRQ4) */
384 0, /* Advanced Interrupt Controller (IRQ5) */
385 0 /* Advanced Interrupt Controller (IRQ6) */
388 AT91_SOC_START(at91rm9200)
389 .map_io = at91rm9200_map_io,
390 .default_irq_priority = at91rm9200_default_irq_priority,
391 .extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
392 | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
393 | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
394 | (1 << AT91RM9200_ID_IRQ6),
395 .ioremap_registers = at91rm9200_ioremap_registers,
396 .register_clocks = at91rm9200_register_clocks,
397 .init = at91rm9200_initialize,