arch/arm/mach-at91/at91sam9261.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9261.c
   3  *
   4  *  Copyright (C) 2005 SAN People
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/clk/at91_pmc.h>
  16
  17 #include <asm/proc-fns.h>
  18 #include <asm/irq.h>
  19 #include <asm/mach/arch.h>
  20 #include <asm/mach/map.h>
  21 #include <asm/system_misc.h>
  22 #include <mach/cpu.h>
  23 #include <mach/at91sam9261.h>
  24 #include <mach/hardware.h>
  25
  26 #include "at91_aic.h"
  27 #include "at91_rstc.h"
  28 #include "soc.h"
  29 #include "generic.h"
  30 #include "sam9_smc.h"
  31 #include "pm.h"
  32
  33 #if defined(CONFIG_OLD_CLK_AT91)
  34 #include "clock.h"
  35
  36 /* --------------------------------------------------------------------
  37  *  Clocks
  38  * -------------------------------------------------------------------- */
  39
  40 /*
  41  * The peripheral clocks.
  42  */
  43 static struct clk pioA_clk = {
  44         .name           = "pioA_clk",
  45         .pmc_mask       = 1 << AT91SAM9261_ID_PIOA,
  46         .type           = CLK_TYPE_PERIPHERAL,
  47 };
  48 static struct clk pioB_clk = {
  49         .name           = "pioB_clk",
  50         .pmc_mask       = 1 << AT91SAM9261_ID_PIOB,
  51         .type           = CLK_TYPE_PERIPHERAL,
  52 };
  53 static struct clk pioC_clk = {
  54         .name           = "pioC_clk",
  55         .pmc_mask       = 1 << AT91SAM9261_ID_PIOC,
  56         .type           = CLK_TYPE_PERIPHERAL,
  57 };
  58 static struct clk usart0_clk = {
  59         .name           = "usart0_clk",
  60         .pmc_mask       = 1 << AT91SAM9261_ID_US0,
  61         .type           = CLK_TYPE_PERIPHERAL,
  62 };
  63 static struct clk usart1_clk = {
  64         .name           = "usart1_clk",
  65         .pmc_mask       = 1 << AT91SAM9261_ID_US1,
  66         .type           = CLK_TYPE_PERIPHERAL,
  67 };
  68 static struct clk usart2_clk = {
  69         .name           = "usart2_clk",
  70         .pmc_mask       = 1 << AT91SAM9261_ID_US2,
  71         .type           = CLK_TYPE_PERIPHERAL,
  72 };
  73 static struct clk mmc_clk = {
  74         .name           = "mci_clk",
  75         .pmc_mask       = 1 << AT91SAM9261_ID_MCI,
  76         .type           = CLK_TYPE_PERIPHERAL,
  77 };
  78 static struct clk udc_clk = {
  79         .name           = "udc_clk",
  80         .pmc_mask       = 1 << AT91SAM9261_ID_UDP,
  81         .type           = CLK_TYPE_PERIPHERAL,
  82 };
  83 static struct clk twi_clk = {
  84         .name           = "twi_clk",
  85         .pmc_mask       = 1 << AT91SAM9261_ID_TWI,
  86         .type           = CLK_TYPE_PERIPHERAL,
  87 };
  88 static struct clk spi0_clk = {
  89         .name           = "spi0_clk",
  90         .pmc_mask       = 1 << AT91SAM9261_ID_SPI0,
  91         .type           = CLK_TYPE_PERIPHERAL,
  92 };
  93 static struct clk spi1_clk = {
  94         .name           = "spi1_clk",
  95         .pmc_mask       = 1 << AT91SAM9261_ID_SPI1,
  96         .type           = CLK_TYPE_PERIPHERAL,
  97 };
  98 static struct clk ssc0_clk = {
  99         .name           = "ssc0_clk",
 100         .pmc_mask       = 1 << AT91SAM9261_ID_SSC0,
 101         .type           = CLK_TYPE_PERIPHERAL,
 102 };
 103 static struct clk ssc1_clk = {
 104         .name           = "ssc1_clk",
 105         .pmc_mask       = 1 << AT91SAM9261_ID_SSC1,
 106         .type           = CLK_TYPE_PERIPHERAL,
 107 };
 108 static struct clk ssc2_clk = {
 109         .name           = "ssc2_clk",
 110         .pmc_mask       = 1 << AT91SAM9261_ID_SSC2,
 111         .type           = CLK_TYPE_PERIPHERAL,
 112 };
 113 static struct clk tc0_clk = {
 114         .name           = "tc0_clk",
 115         .pmc_mask       = 1 << AT91SAM9261_ID_TC0,
 116         .type           = CLK_TYPE_PERIPHERAL,
 117 };
 118 static struct clk tc1_clk = {
 119         .name           = "tc1_clk",
 120         .pmc_mask       = 1 << AT91SAM9261_ID_TC1,
 121         .type           = CLK_TYPE_PERIPHERAL,
 122 };
 123 static struct clk tc2_clk = {
 124         .name           = "tc2_clk",
 125         .pmc_mask       = 1 << AT91SAM9261_ID_TC2,
 126         .type           = CLK_TYPE_PERIPHERAL,
 127 };
 128 static struct clk ohci_clk = {
 129         .name           = "ohci_clk",
 130         .pmc_mask       = 1 << AT91SAM9261_ID_UHP,
 131         .type           = CLK_TYPE_PERIPHERAL,
 132 };
 133 static struct clk lcdc_clk = {
 134         .name           = "lcdc_clk",
 135         .pmc_mask       = 1 << AT91SAM9261_ID_LCDC,
 136         .type           = CLK_TYPE_PERIPHERAL,
 137 };
 138
 139 /* HClocks */
 140 static struct clk hck0 = {
 141         .name           = "hck0",
 142         .pmc_mask       = AT91_PMC_HCK0,
 143         .type           = CLK_TYPE_SYSTEM,
 144         .id             = 0,
 145 };
 146 static struct clk hck1 = {
 147         .name           = "hck1",
 148         .pmc_mask       = AT91_PMC_HCK1,
 149         .type           = CLK_TYPE_SYSTEM,
 150         .id             = 1,
 151 };
 152
 153 static struct clk *periph_clocks[] __initdata = {
 154         &pioA_clk,
 155         &pioB_clk,
 156         &pioC_clk,
 157         &usart0_clk,
 158         &usart1_clk,
 159         &usart2_clk,
 160         &mmc_clk,
 161         &udc_clk,
 162         &twi_clk,
 163         &spi0_clk,
 164         &spi1_clk,
 165         &ssc0_clk,
 166         &ssc1_clk,
 167         &ssc2_clk,
 168         &tc0_clk,
 169         &tc1_clk,
 170         &tc2_clk,
 171         &ohci_clk,
 172         &lcdc_clk,
 173         // irq0 .. irq2
 174 };
 175
 176 static struct clk_lookup periph_clocks_lookups[] = {
 177         CLKDEV_CON_DEV_ID("hclk", "at91sam9261-lcdfb.0", &hck1),
 178         CLKDEV_CON_DEV_ID("hclk", "at91sam9g10-lcdfb.0", &hck1),
 179         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 180         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 181         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 182         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 183         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 184         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
 185         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
 186         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
 187         CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc0_clk),
 188         CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc1_clk),
 189         CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc2_clk),
 190         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
 191         CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261.0", &twi_clk),
 192         CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi_clk),
 193         CLKDEV_CON_ID("pioA", &pioA_clk),
 194         CLKDEV_CON_ID("pioB", &pioB_clk),
 195         CLKDEV_CON_ID("pioC", &pioC_clk),
 196         /* more lookup table for DT entries */
 197         CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
 198         CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
 199         CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk),
 200         CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
 201         CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
 202         CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
 203         CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
 204         CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &hck0),
 205         CLKDEV_CON_DEV_ID("hclk", "600000.fb", &hck1),
 206         CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
 207         CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
 208         CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
 209         CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
 210         CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
 211         CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
 212         CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
 213 };
 214
 215 static struct clk_lookup usart_clocks_lookups[] = {
 216         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 217         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 218         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 219         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 220 };
 221
 222 /*
 223  * The four programmable clocks.
 224  * You must configure pin multiplexing to bring these signals out.
 225  */
 226 static struct clk pck0 = {
 227         .name           = "pck0",
 228         .pmc_mask       = AT91_PMC_PCK0,
 229         .type           = CLK_TYPE_PROGRAMMABLE,
 230         .id             = 0,
 231 };
 232 static struct clk pck1 = {
 233         .name           = "pck1",
 234         .pmc_mask       = AT91_PMC_PCK1,
 235         .type           = CLK_TYPE_PROGRAMMABLE,
 236         .id             = 1,
 237 };
 238 static struct clk pck2 = {
 239         .name           = "pck2",
 240         .pmc_mask       = AT91_PMC_PCK2,
 241         .type           = CLK_TYPE_PROGRAMMABLE,
 242         .id             = 2,
 243 };
 244 static struct clk pck3 = {
 245         .name           = "pck3",
 246         .pmc_mask       = AT91_PMC_PCK3,
 247         .type           = CLK_TYPE_PROGRAMMABLE,
 248         .id             = 3,
 249 };
 250
 251 static void __init at91sam9261_register_clocks(void)
 252 {
 253         int i;
 254
 255         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 256                 clk_register(periph_clocks[i]);
 257
 258         clkdev_add_table(periph_clocks_lookups,
 259                          ARRAY_SIZE(periph_clocks_lookups));
 260         clkdev_add_table(usart_clocks_lookups,
 261                          ARRAY_SIZE(usart_clocks_lookups));
 262
 263         clk_register(&pck0);
 264         clk_register(&pck1);
 265         clk_register(&pck2);
 266         clk_register(&pck3);
 267
 268         clk_register(&hck0);
 269         clk_register(&hck1);
 270 }
 271 #else
 272 #define at91sam9261_register_clocks NULL
 273 #endif
 274 /* --------------------------------------------------------------------
 275  *  GPIO
 276  * -------------------------------------------------------------------- */
 277
 278 static struct at91_gpio_bank at91sam9261_gpio[] __initdata = {
 279         {
 280                 .id             = AT91SAM9261_ID_PIOA,
 281                 .regbase        = AT91SAM9261_BASE_PIOA,
 282         }, {
 283                 .id             = AT91SAM9261_ID_PIOB,
 284                 .regbase        = AT91SAM9261_BASE_PIOB,
 285         }, {
 286                 .id             = AT91SAM9261_ID_PIOC,
 287                 .regbase        = AT91SAM9261_BASE_PIOC,
 288         }
 289 };
 290
 291 /* --------------------------------------------------------------------
 292  *  AT91SAM9261 processor initialization
 293  * -------------------------------------------------------------------- */
 294
 295 static void __init at91sam9261_map_io(void)
 296 {
 297         if (cpu_is_at91sam9g10())
 298                 at91_init_sram(0, AT91SAM9G10_SRAM_BASE, AT91SAM9G10_SRAM_SIZE);
 299         else
 300                 at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
 301 }
 302
 303 static void __init at91sam9261_ioremap_registers(void)
 304 {
 305         at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
 306         at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
 307         at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
 308         at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
 309         at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
 310         at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
 311         at91_pm_set_standby(at91sam9_sdram_standby);
 312 }
 313
 314 static void __init at91sam9261_initialize(void)
 315 {
 316         arm_pm_idle = at91sam9_idle;
 317
 318         at91_sysirq_mask_rtt(AT91SAM9261_BASE_RTT);
 319
 320         /* Register GPIO subsystem */
 321         at91_gpio_init(at91sam9261_gpio, 3);
 322 }
 323
 324 static struct resource rstc_resources[] = {
 325         [0] = {
 326                 .start  = AT91SAM9261_BASE_RSTC,
 327                 .end    = AT91SAM9261_BASE_RSTC + SZ_16 - 1,
 328                 .flags  = IORESOURCE_MEM,
 329         },
 330         [1] = {
 331                 .start  = AT91SAM9261_BASE_SDRAMC,
 332                 .end    = AT91SAM9261_BASE_SDRAMC + SZ_512 - 1,
 333                 .flags  = IORESOURCE_MEM,
 334         },
 335 };
 336
 337 static struct platform_device rstc_device = {
 338         .name           = "at91-sam9260-reset",
 339         .resource       = rstc_resources,
 340         .num_resources  = ARRAY_SIZE(rstc_resources),
 341 };
 342
 343 static void __init at91sam9261_register_devices(void)
 344 {
 345         platform_device_register(&rstc_device);
 346 }
 347
 348 /* --------------------------------------------------------------------
 349  *  Interrupt initialization
 350  * -------------------------------------------------------------------- */
 351
 352 /*
 353  * The default interrupt priority levels (0 = lowest, 7 = highest).
 354  */
 355 static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
 356         7,      /* Advanced Interrupt Controller */
 357         7,      /* System Peripherals */
 358         1,      /* Parallel IO Controller A */
 359         1,      /* Parallel IO Controller B */
 360         1,      /* Parallel IO Controller C */
 361         0,
 362         5,      /* USART 0 */
 363         5,      /* USART 1 */
 364         5,      /* USART 2 */
 365         0,      /* Multimedia Card Interface */
 366         2,      /* USB Device Port */
 367         6,      /* Two-Wire Interface */
 368         5,      /* Serial Peripheral Interface 0 */
 369         5,      /* Serial Peripheral Interface 1 */
 370         4,      /* Serial Synchronous Controller 0 */
 371         4,      /* Serial Synchronous Controller 1 */
 372         4,      /* Serial Synchronous Controller 2 */
 373         0,      /* Timer Counter 0 */
 374         0,      /* Timer Counter 1 */
 375         0,      /* Timer Counter 2 */
 376         2,      /* USB Host port */
 377         3,      /* LCD Controller */
 378         0,
 379         0,
 380         0,
 381         0,
 382         0,
 383         0,
 384         0,
 385         0,      /* Advanced Interrupt Controller */
 386         0,      /* Advanced Interrupt Controller */
 387         0,      /* Advanced Interrupt Controller */
 388 };
 389
 390 AT91_SOC_START(at91sam9261)
 391         .map_io = at91sam9261_map_io,
 392         .default_irq_priority = at91sam9261_default_irq_priority,
 393         .extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
 394                     | (1 << AT91SAM9261_ID_IRQ2),
 395         .ioremap_registers = at91sam9261_ioremap_registers,
 396         .register_clocks = at91sam9261_register_clocks,
 397         .register_devices = at91sam9261_register_devices,
 398         .init = at91sam9261_initialize,
 399 AT91_SOC_END