arch/arm/mach-at91/at91sam9x5.c

   1 /*
   2  *  Chip-specific setup code for the AT91SAM9x5 family
   3  *
   4  *  Copyright (C) 2010-2012 Atmel Corporation.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/clk/at91_pmc.h>
  12
  13 #include <asm/irq.h>
  14 #include <asm/mach/arch.h>
  15 #include <asm/mach/map.h>
  16 #include <mach/at91sam9x5.h>
  17 #include <mach/cpu.h>
  18
  19 #include "board.h"
  20 #include "soc.h"
  21 #include "generic.h"
  22 #include "sam9_smc.h"
  23
  24 #if defined(CONFIG_OLD_CLK_AT91)
  25 #include "clock.h"
  26 /* --------------------------------------------------------------------
  27  *  Clocks
  28  * -------------------------------------------------------------------- */
  29
  30 /*
  31  * The peripheral clocks.
  32  */
  33 static struct clk pioAB_clk = {
  34         .name           = "pioAB_clk",
  35         .pmc_mask       = 1 << AT91SAM9X5_ID_PIOAB,
  36         .type           = CLK_TYPE_PERIPHERAL,
  37 };
  38 static struct clk pioCD_clk = {
  39         .name           = "pioCD_clk",
  40         .pmc_mask       = 1 << AT91SAM9X5_ID_PIOCD,
  41         .type           = CLK_TYPE_PERIPHERAL,
  42 };
  43 static struct clk smd_clk = {
  44         .name           = "smd_clk",
  45         .pmc_mask       = 1 << AT91SAM9X5_ID_SMD,
  46         .type           = CLK_TYPE_PERIPHERAL,
  47 };
  48 static struct clk usart0_clk = {
  49         .name           = "usart0_clk",
  50         .pmc_mask       = 1 << AT91SAM9X5_ID_USART0,
  51         .type           = CLK_TYPE_PERIPHERAL,
  52 };
  53 static struct clk usart1_clk = {
  54         .name           = "usart1_clk",
  55         .pmc_mask       = 1 << AT91SAM9X5_ID_USART1,
  56         .type           = CLK_TYPE_PERIPHERAL,
  57 };
  58 static struct clk usart2_clk = {
  59         .name           = "usart2_clk",
  60         .pmc_mask       = 1 << AT91SAM9X5_ID_USART2,
  61         .type           = CLK_TYPE_PERIPHERAL,
  62 };
  63 /* USART3 clock - Only for sam9g25/sam9x25 */
  64 static struct clk usart3_clk = {
  65         .name           = "usart3_clk",
  66         .pmc_mask       = 1 << AT91SAM9X5_ID_USART3,
  67         .type           = CLK_TYPE_PERIPHERAL,
  68 };
  69 static struct clk twi0_clk = {
  70         .name           = "twi0_clk",
  71         .pmc_mask       = 1 << AT91SAM9X5_ID_TWI0,
  72         .type           = CLK_TYPE_PERIPHERAL,
  73 };
  74 static struct clk twi1_clk = {
  75         .name           = "twi1_clk",
  76         .pmc_mask       = 1 << AT91SAM9X5_ID_TWI1,
  77         .type           = CLK_TYPE_PERIPHERAL,
  78 };
  79 static struct clk twi2_clk = {
  80         .name           = "twi2_clk",
  81         .pmc_mask       = 1 << AT91SAM9X5_ID_TWI2,
  82         .type           = CLK_TYPE_PERIPHERAL,
  83 };
  84 static struct clk mmc0_clk = {
  85         .name           = "mci0_clk",
  86         .pmc_mask       = 1 << AT91SAM9X5_ID_MCI0,
  87         .type           = CLK_TYPE_PERIPHERAL,
  88 };
  89 static struct clk spi0_clk = {
  90         .name           = "spi0_clk",
  91         .pmc_mask       = 1 << AT91SAM9X5_ID_SPI0,
  92         .type           = CLK_TYPE_PERIPHERAL,
  93 };
  94 static struct clk spi1_clk = {
  95         .name           = "spi1_clk",
  96         .pmc_mask       = 1 << AT91SAM9X5_ID_SPI1,
  97         .type           = CLK_TYPE_PERIPHERAL,
  98 };
  99 static struct clk uart0_clk = {
 100         .name           = "uart0_clk",
 101         .pmc_mask       = 1 << AT91SAM9X5_ID_UART0,
 102         .type           = CLK_TYPE_PERIPHERAL,
 103 };
 104 static struct clk uart1_clk = {
 105         .name           = "uart1_clk",
 106         .pmc_mask       = 1 << AT91SAM9X5_ID_UART1,
 107         .type           = CLK_TYPE_PERIPHERAL,
 108 };
 109 static struct clk tcb0_clk = {
 110         .name           = "tcb0_clk",
 111         .pmc_mask       = 1 << AT91SAM9X5_ID_TCB,
 112         .type           = CLK_TYPE_PERIPHERAL,
 113 };
 114 static struct clk pwm_clk = {
 115         .name           = "pwm_clk",
 116         .pmc_mask       = 1 << AT91SAM9X5_ID_PWM,
 117         .type           = CLK_TYPE_PERIPHERAL,
 118 };
 119 static struct clk adc_clk = {
 120         .name           = "adc_clk",
 121         .pmc_mask       = 1 << AT91SAM9X5_ID_ADC,
 122         .type   = CLK_TYPE_PERIPHERAL,
 123 };
 124 static struct clk adc_op_clk = {
 125         .name           = "adc_op_clk",
 126         .type           = CLK_TYPE_PERIPHERAL,
 127         .rate_hz        = 5000000,
 128 };
 129 static struct clk dma0_clk = {
 130         .name           = "dma0_clk",
 131         .pmc_mask       = 1 << AT91SAM9X5_ID_DMA0,
 132         .type   = CLK_TYPE_PERIPHERAL,
 133 };
 134 static struct clk dma1_clk = {
 135         .name           = "dma1_clk",
 136         .pmc_mask       = 1 << AT91SAM9X5_ID_DMA1,
 137         .type           = CLK_TYPE_PERIPHERAL,
 138 };
 139 static struct clk uhphs_clk = {
 140         .name           = "uhphs",
 141         .pmc_mask       = 1 << AT91SAM9X5_ID_UHPHS,
 142         .type           = CLK_TYPE_PERIPHERAL,
 143 };
 144 static struct clk udphs_clk = {
 145         .name           = "udphs_clk",
 146         .pmc_mask       = 1 << AT91SAM9X5_ID_UDPHS,
 147         .type           = CLK_TYPE_PERIPHERAL,
 148 };
 149 /* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
 150 static struct clk macb0_clk = {
 151         .name           = "pclk",
 152         .pmc_mask       = 1 << AT91SAM9X5_ID_EMAC0,
 153         .type           = CLK_TYPE_PERIPHERAL,
 154 };
 155 /* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
 156 static struct clk lcdc_clk = {
 157         .name           = "lcdc_clk",
 158         .pmc_mask       = 1 << AT91SAM9X5_ID_LCDC,
 159         .type           = CLK_TYPE_PERIPHERAL,
 160 };
 161 /* isi clock - Only for sam9g25 */
 162 static struct clk isi_clk = {
 163         .name           = "isi_clk",
 164         .pmc_mask       = 1 << AT91SAM9X5_ID_ISI,
 165         .type           = CLK_TYPE_PERIPHERAL,
 166 };
 167 static struct clk mmc1_clk = {
 168         .name           = "mci1_clk",
 169         .pmc_mask       = 1 << AT91SAM9X5_ID_MCI1,
 170         .type           = CLK_TYPE_PERIPHERAL,
 171 };
 172 /* emac1 clock - Only for sam9x25 */
 173 static struct clk macb1_clk = {
 174         .name           = "pclk",
 175         .pmc_mask       = 1 << AT91SAM9X5_ID_EMAC1,
 176         .type           = CLK_TYPE_PERIPHERAL,
 177 };
 178 static struct clk ssc_clk = {
 179         .name           = "ssc_clk",
 180         .pmc_mask       = 1 << AT91SAM9X5_ID_SSC,
 181         .type           = CLK_TYPE_PERIPHERAL,
 182 };
 183 /* can0 clock - Only for sam9x35 */
 184 static struct clk can0_clk = {
 185         .name           = "can0_clk",
 186         .pmc_mask       = 1 << AT91SAM9X5_ID_CAN0,
 187         .type           = CLK_TYPE_PERIPHERAL,
 188 };
 189 /* can1 clock - Only for sam9x35 */
 190 static struct clk can1_clk = {
 191         .name           = "can1_clk",
 192         .pmc_mask       = 1 << AT91SAM9X5_ID_CAN1,
 193         .type           = CLK_TYPE_PERIPHERAL,
 194 };
 195
 196 static struct clk *periph_clocks[] __initdata = {
 197         &pioAB_clk,
 198         &pioCD_clk,
 199         &smd_clk,
 200         &usart0_clk,
 201         &usart1_clk,
 202         &usart2_clk,
 203         &twi0_clk,
 204         &twi1_clk,
 205         &twi2_clk,
 206         &mmc0_clk,
 207         &spi0_clk,
 208         &spi1_clk,
 209         &uart0_clk,
 210         &uart1_clk,
 211         &tcb0_clk,
 212         &pwm_clk,
 213         &adc_clk,
 214         &adc_op_clk,
 215         &dma0_clk,
 216         &dma1_clk,
 217         &uhphs_clk,
 218         &udphs_clk,
 219         &mmc1_clk,
 220         &ssc_clk,
 221         // irq0
 222 };
 223
 224 static struct clk_lookup periph_clocks_lookups[] = {
 225         /* lookup table for DT entries */
 226         CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
 227         CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
 228         CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
 229         CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
 230         CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
 231         CLKDEV_CON_DEV_ID("usart", "f8040000.serial", &uart0_clk),
 232         CLKDEV_CON_DEV_ID("usart", "f8044000.serial", &uart1_clk),
 233         CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
 234         CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
 235         CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc0_clk),
 236         CLKDEV_CON_DEV_ID("mci_clk", "f000c000.mmc", &mmc1_clk),
 237         CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
 238         CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
 239         CLKDEV_CON_DEV_ID("pclk", "f0010000.ssc", &ssc_clk),
 240         CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
 241         CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
 242         CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
 243         CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
 244         CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
 245         CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
 246         CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
 247         CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
 248         CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
 249         /* additional fake clock for macb_hclk */
 250         CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
 251         CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
 252         CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
 253         CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
 254         CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
 255         CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
 256         CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
 257         CLKDEV_CON_DEV_ID(NULL, "f8034000.pwm", &pwm_clk),
 258 };
 259
 260 /*
 261  * The two programmable clocks.
 262  * You must configure pin multiplexing to bring these signals out.
 263  */
 264 static struct clk pck0 = {
 265         .name           = "pck0",
 266         .pmc_mask       = AT91_PMC_PCK0,
 267         .type           = CLK_TYPE_PROGRAMMABLE,
 268         .id             = 0,
 269 };
 270 static struct clk pck1 = {
 271         .name           = "pck1",
 272         .pmc_mask       = AT91_PMC_PCK1,
 273         .type           = CLK_TYPE_PROGRAMMABLE,
 274         .id             = 1,
 275 };
 276
 277 static void __init at91sam9x5_register_clocks(void)
 278 {
 279         int i;
 280
 281         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 282                 clk_register(periph_clocks[i]);
 283
 284         clkdev_add_table(periph_clocks_lookups,
 285                          ARRAY_SIZE(periph_clocks_lookups));
 286
 287         if (cpu_is_at91sam9g25()
 288         || cpu_is_at91sam9x25())
 289                 clk_register(&usart3_clk);
 290
 291         if (cpu_is_at91sam9g25()
 292         || cpu_is_at91sam9x25()
 293         || cpu_is_at91sam9g35()
 294         || cpu_is_at91sam9x35())
 295                 clk_register(&macb0_clk);
 296
 297         if (cpu_is_at91sam9g15()
 298         || cpu_is_at91sam9g35()
 299         || cpu_is_at91sam9x35())
 300                 clk_register(&lcdc_clk);
 301
 302         if (cpu_is_at91sam9g25())
 303                 clk_register(&isi_clk);
 304
 305         if (cpu_is_at91sam9x25())
 306                 clk_register(&macb1_clk);
 307
 308         if (cpu_is_at91sam9x25()
 309         || cpu_is_at91sam9x35()) {
 310                 clk_register(&can0_clk);
 311                 clk_register(&can1_clk);
 312         }
 313
 314         clk_register(&pck0);
 315         clk_register(&pck1);
 316 }
 317 #else
 318 #define at91sam9x5_register_clocks      NULL
 319 #endif
 320
 321 /* --------------------------------------------------------------------
 322  *  AT91SAM9x5 processor initialization
 323  * -------------------------------------------------------------------- */
 324
 325 static void __init at91sam9x5_map_io(void)
 326 {
 327         at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
 328 }
 329
 330 static void __init at91sam9x5_initialize(void)
 331 {
 332         at91_sysirq_mask_rtc(AT91SAM9X5_BASE_RTC);
 333 }
 334
 335 /* --------------------------------------------------------------------
 336  *  Interrupt initialization
 337  * -------------------------------------------------------------------- */
 338
 339 AT91_SOC_START(at91sam9x5)
 340         .map_io = at91sam9x5_map_io,
 341         .register_clocks = at91sam9x5_register_clocks,
 342         .init = at91sam9x5_initialize,
 343 AT91_SOC_END