2 * Clock and PLL control for DaVinci devices
4 * Copyright (C) 2006-2007 Texas Instruments.
5 * Copyright (C) 2008-2009 Deep Root Systems, LLC
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/errno.h>
17 #include <linux/clk.h>
18 #include <linux/err.h>
19 #include <linux/mutex.h>
20 #include <linux/platform_device.h>
22 #include <linux/delay.h>
24 #include <mach/hardware.h>
27 #include <mach/cputype.h>
30 static LIST_HEAD(clocks);
31 static DEFINE_MUTEX(clocks_mutex);
32 static DEFINE_SPINLOCK(clockfw_lock);
34 static unsigned psc_domain(struct clk *clk)
36 return (clk->flags & PSC_DSP)
37 ? DAVINCI_GPSC_DSPDOMAIN
38 : DAVINCI_GPSC_ARMDOMAIN;
41 static void __clk_enable(struct clk *clk)
44 __clk_enable(clk->parent);
45 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
46 davinci_psc_config(psc_domain(clk), clk->psc_ctlr,
50 static void __clk_disable(struct clk *clk)
52 if (WARN_ON(clk->usecount == 0))
54 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL))
55 davinci_psc_config(psc_domain(clk), clk->psc_ctlr,
58 __clk_disable(clk->parent);
61 int clk_enable(struct clk *clk)
65 if (clk == NULL || IS_ERR(clk))
68 spin_lock_irqsave(&clockfw_lock, flags);
70 spin_unlock_irqrestore(&clockfw_lock, flags);
74 EXPORT_SYMBOL(clk_enable);
76 void clk_disable(struct clk *clk)
80 if (clk == NULL || IS_ERR(clk))
83 spin_lock_irqsave(&clockfw_lock, flags);
85 spin_unlock_irqrestore(&clockfw_lock, flags);
87 EXPORT_SYMBOL(clk_disable);
89 unsigned long clk_get_rate(struct clk *clk)
91 if (clk == NULL || IS_ERR(clk))
96 EXPORT_SYMBOL(clk_get_rate);
98 long clk_round_rate(struct clk *clk, unsigned long rate)
100 if (clk == NULL || IS_ERR(clk))
104 return clk->round_rate(clk, rate);
108 EXPORT_SYMBOL(clk_round_rate);
110 /* Propagate rate to children */
111 static void propagate_rate(struct clk *root)
115 list_for_each_entry(clk, &root->children, childnode) {
117 clk->rate = clk->recalc(clk);
122 int clk_set_rate(struct clk *clk, unsigned long rate)
127 if (clk == NULL || IS_ERR(clk))
130 spin_lock_irqsave(&clockfw_lock, flags);
132 ret = clk->set_rate(clk, rate);
135 clk->rate = clk->recalc(clk);
138 spin_unlock_irqrestore(&clockfw_lock, flags);
142 EXPORT_SYMBOL(clk_set_rate);
144 int clk_register(struct clk *clk)
146 if (clk == NULL || IS_ERR(clk))
149 if (WARN(clk->parent && !clk->parent->rate,
150 "CLK: %s parent %s has no rate!\n",
151 clk->name, clk->parent->name))
154 INIT_LIST_HEAD(&clk->children);
156 mutex_lock(&clocks_mutex);
157 list_add_tail(&clk->node, &clocks);
159 list_add_tail(&clk->childnode, &clk->parent->children);
160 mutex_unlock(&clocks_mutex);
162 /* If rate is already set, use it */
166 /* Else, see if there is a way to calculate it */
168 clk->rate = clk->recalc(clk);
170 /* Otherwise, default to parent rate */
171 else if (clk->parent)
172 clk->rate = clk->parent->rate;
176 EXPORT_SYMBOL(clk_register);
178 void clk_unregister(struct clk *clk)
180 if (clk == NULL || IS_ERR(clk))
183 mutex_lock(&clocks_mutex);
184 list_del(&clk->node);
185 list_del(&clk->childnode);
186 mutex_unlock(&clocks_mutex);
188 EXPORT_SYMBOL(clk_unregister);
190 #ifdef CONFIG_DAVINCI_RESET_CLOCKS
192 * Disable any unused clocks left on by the bootloader
194 static int __init clk_disable_unused(void)
198 spin_lock_irq(&clockfw_lock);
199 list_for_each_entry(ck, &clocks, node) {
200 if (ck->usecount > 0)
202 if (!(ck->flags & CLK_PSC))
205 /* ignore if in Disabled or SwRstDisable states */
206 if (!davinci_psc_is_clk_active(ck->psc_ctlr, ck->lpsc))
209 pr_info("Clocks: disable unused %s\n", ck->name);
210 davinci_psc_config(psc_domain(ck), ck->psc_ctlr, ck->lpsc, 0);
212 spin_unlock_irq(&clockfw_lock);
216 late_initcall(clk_disable_unused);
219 static unsigned long clk_sysclk_recalc(struct clk *clk)
222 struct pll_data *pll;
223 unsigned long rate = clk->rate;
225 /* If this is the PLL base clock, no more calculations needed */
229 if (WARN_ON(!clk->parent))
232 rate = clk->parent->rate;
234 /* Otherwise, the parent must be a PLL */
235 if (WARN_ON(!clk->parent->pll_data))
238 pll = clk->parent->pll_data;
240 /* If pre-PLL, source clock is before the multiplier and divider(s) */
241 if (clk->flags & PRE_PLL)
242 rate = pll->input_rate;
247 v = __raw_readl(pll->base + clk->div_reg);
249 plldiv = (v & PLLDIV_RATIO_MASK) + 1;
257 static unsigned long clk_leafclk_recalc(struct clk *clk)
259 if (WARN_ON(!clk->parent))
262 return clk->parent->rate;
265 static unsigned long clk_pllclk_recalc(struct clk *clk)
267 u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
269 struct pll_data *pll = clk->pll_data;
270 unsigned long rate = clk->rate;
272 pll->base = IO_ADDRESS(pll->phys_base);
273 ctrl = __raw_readl(pll->base + PLLCTL);
274 rate = pll->input_rate = clk->parent->rate;
276 if (ctrl & PLLCTL_PLLEN) {
278 mult = __raw_readl(pll->base + PLLM);
279 if (cpu_is_davinci_dm365())
280 mult = 2 * (mult & PLLM_PLLM_MASK);
282 mult = (mult & PLLM_PLLM_MASK) + 1;
286 if (pll->flags & PLL_HAS_PREDIV) {
287 prediv = __raw_readl(pll->base + PREDIV);
288 if (prediv & PLLDIV_EN)
289 prediv = (prediv & PLLDIV_RATIO_MASK) + 1;
294 /* pre-divider is fixed, but (some?) chips won't report that */
295 if (cpu_is_davinci_dm355() && pll->num == 1)
298 if (pll->flags & PLL_HAS_POSTDIV) {
299 postdiv = __raw_readl(pll->base + POSTDIV);
300 if (postdiv & PLLDIV_EN)
301 postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1;
312 pr_debug("PLL%d: input = %lu MHz [ ",
313 pll->num, clk->parent->rate / 1000000);
317 pr_debug("/ %d ", prediv);
319 pr_debug("* %d ", mult);
321 pr_debug("/ %d ", postdiv);
322 pr_debug("] --> %lu MHz output.\n", rate / 1000000);
328 * davinci_set_pllrate - set the output rate of a given PLL.
330 * Note: Currently tested to work with OMAP-L138 only.
332 * @pll: pll whose rate needs to be changed.
333 * @prediv: The pre divider value. Passing 0 disables the pre-divider.
334 * @pllm: The multiplier value. Passing 0 leads to multiply-by-one.
335 * @postdiv: The post divider value. Passing 0 disables the post-divider.
337 int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
338 unsigned int mult, unsigned int postdiv)
341 unsigned int locktime;
343 if (pll->base == NULL)
347 * PLL lock time required per OMAP-L138 datasheet is
348 * (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm)
349 * as 4 and OSCIN cycle as 25 MHz.
352 locktime = ((2000 * prediv) / 100);
353 prediv = (prediv - 1) | PLLDIV_EN;
358 postdiv = (postdiv - 1) | PLLDIV_EN;
362 ctrl = __raw_readl(pll->base + PLLCTL);
364 /* Switch the PLL to bypass mode */
365 ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
366 __raw_writel(ctrl, pll->base + PLLCTL);
369 * Wait for 4 OSCIN/CLKIN cycles to ensure that the PLLC has switched
370 * to bypass mode. Delay of 1us ensures we are good for all > 4MHz
371 * OSCIN/CLKIN inputs. Typically the input is ~25MHz.
375 /* Reset and enable PLL */
376 ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
377 __raw_writel(ctrl, pll->base + PLLCTL);
379 if (pll->flags & PLL_HAS_PREDIV)
380 __raw_writel(prediv, pll->base + PREDIV);
382 __raw_writel(mult, pll->base + PLLM);
384 if (pll->flags & PLL_HAS_POSTDIV)
385 __raw_writel(postdiv, pll->base + POSTDIV);
388 * Wait for PLL to reset properly, OMAP-L138 datasheet says
393 /* Bring PLL out of reset */
394 ctrl |= PLLCTL_PLLRST;
395 __raw_writel(ctrl, pll->base + PLLCTL);
399 /* Remove PLL from bypass mode */
400 ctrl |= PLLCTL_PLLEN;
401 __raw_writel(ctrl, pll->base + PLLCTL);
405 EXPORT_SYMBOL(davinci_set_pllrate);
407 int __init davinci_clk_init(struct davinci_clk *clocks)
409 struct davinci_clk *c;
412 for (c = clocks; c->lk.clk; c++) {
417 /* Check if clock is a PLL */
419 clk->recalc = clk_pllclk_recalc;
421 /* Else, if it is a PLL-derived clock */
422 else if (clk->flags & CLK_PLL)
423 clk->recalc = clk_sysclk_recalc;
425 /* Otherwise, it is a leaf clock (PSC clock) */
426 else if (clk->parent)
427 clk->recalc = clk_leafclk_recalc;
431 clk->rate = clk->recalc(clk);
434 clk->flags |= CLK_PSC;
439 /* Turn on clocks that Linux doesn't otherwise manage */
440 if (clk->flags & ALWAYS_ENABLED)
447 #ifdef CONFIG_PROC_FS
448 #include <linux/proc_fs.h>
449 #include <linux/seq_file.h>
451 static void *davinci_ck_start(struct seq_file *m, loff_t *pos)
453 return *pos < 1 ? (void *)1 : NULL;
456 static void *davinci_ck_next(struct seq_file *m, void *v, loff_t *pos)
462 static void davinci_ck_stop(struct seq_file *m, void *v)
466 #define CLKNAME_MAX 10 /* longest clock name */
471 dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
474 char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
478 if (parent->flags & CLK_PLL)
480 else if (parent->flags & CLK_PSC)
485 /* <nest spaces> name <pad to end> */
486 memset(buf, ' ', sizeof(buf) - 1);
487 buf[sizeof(buf) - 1] = 0;
488 i = strlen(parent->name);
489 memcpy(buf + nest, parent->name,
490 min(i, (unsigned)(sizeof(buf) - 1 - nest)));
492 seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
493 buf, parent->usecount, state, clk_get_rate(parent));
494 /* REVISIT show device associations too */
496 /* cost is now small, but not linear... */
497 list_for_each_entry(clk, &parent->children, childnode) {
498 dump_clock(s, nest + NEST_DELTA, clk);
502 static int davinci_ck_show(struct seq_file *m, void *v)
504 /* Show clock tree; we know the main oscillator is first.
505 * We trust nonzero usecounts equate to PSC enables...
507 mutex_lock(&clocks_mutex);
508 if (!list_empty(&clocks))
509 dump_clock(m, 0, list_first_entry(&clocks, struct clk, node));
510 mutex_unlock(&clocks_mutex);
515 static const struct seq_operations davinci_ck_op = {
516 .start = davinci_ck_start,
517 .next = davinci_ck_next,
518 .stop = davinci_ck_stop,
519 .show = davinci_ck_show
522 static int davinci_ck_open(struct inode *inode, struct file *file)
524 return seq_open(file, &davinci_ck_op);
527 static const struct file_operations proc_davinci_ck_operations = {
528 .open = davinci_ck_open,
531 .release = seq_release,
534 static int __init davinci_ck_proc_init(void)
536 proc_create("davinci_clocks", 0, NULL, &proc_davinci_ck_operations);
540 __initcall(davinci_ck_proc_init);
541 #endif /* CONFIG_DEBUG_PROC_FS */