2 * TI Common Platform Interrupt Controller (cp_intc) driver
4 * Author: Steve Chen <schen@mvista.com>
5 * Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <linux/export.h>
13 #include <linux/init.h>
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
18 #include <mach/common.h>
19 #include <mach/cp_intc.h>
21 static inline unsigned int cp_intc_read(unsigned offset)
23 return __raw_readl(davinci_intc_base + offset);
26 static inline void cp_intc_write(unsigned long value, unsigned offset)
28 __raw_writel(value, davinci_intc_base + offset);
31 static void cp_intc_ack_irq(struct irq_data *d)
33 cp_intc_write(d->hwirq, CP_INTC_SYS_STAT_IDX_CLR);
36 /* Disable interrupt */
37 static void cp_intc_mask_irq(struct irq_data *d)
39 /* XXX don't know why we need to disable nIRQ here... */
40 cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR);
41 cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_CLR);
42 cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
45 /* Enable interrupt */
46 static void cp_intc_unmask_irq(struct irq_data *d)
48 cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_SET);
51 static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type)
53 unsigned reg = BIT_WORD(d->hwirq);
54 unsigned mask = BIT_MASK(d->hwirq);
55 unsigned polarity = cp_intc_read(CP_INTC_SYS_POLARITY(reg));
56 unsigned type = cp_intc_read(CP_INTC_SYS_TYPE(reg));
59 case IRQ_TYPE_EDGE_RISING:
63 case IRQ_TYPE_EDGE_FALLING:
67 case IRQ_TYPE_LEVEL_HIGH:
71 case IRQ_TYPE_LEVEL_LOW:
79 cp_intc_write(polarity, CP_INTC_SYS_POLARITY(reg));
80 cp_intc_write(type, CP_INTC_SYS_TYPE(reg));
86 * Faking this allows us to to work with suspend functions of
87 * generic drivers which call {enable|disable}_irq_wake for
88 * wake up interrupt sources (eg RTC on DA850).
90 static int cp_intc_set_wake(struct irq_data *d, unsigned int on)
95 static struct irq_chip cp_intc_irq_chip = {
97 .irq_ack = cp_intc_ack_irq,
98 .irq_mask = cp_intc_mask_irq,
99 .irq_unmask = cp_intc_unmask_irq,
100 .irq_set_type = cp_intc_set_irq_type,
101 .irq_set_wake = cp_intc_set_wake,
104 static struct irq_domain *cp_intc_domain;
106 static int cp_intc_host_map(struct irq_domain *h, unsigned int virq,
109 pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
111 irq_set_chip(virq, &cp_intc_irq_chip);
112 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
113 irq_set_handler(virq, handle_edge_irq);
117 static const struct irq_domain_ops cp_intc_host_ops = {
118 .map = cp_intc_host_map,
119 .xlate = irq_domain_xlate_onetwocell,
122 int __init __cp_intc_init(struct device_node *node)
124 u32 num_irq = davinci_soc_info.intc_irq_num;
125 u8 *irq_prio = davinci_soc_info.intc_irq_prios;
126 u32 *host_map = davinci_soc_info.intc_host_map;
127 unsigned num_reg = BITS_TO_LONGS(num_irq);
130 davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC;
131 davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K);
132 if (WARN_ON(!davinci_intc_base))
135 cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);
137 /* Disable all host interrupts */
138 cp_intc_write(0, CP_INTC_HOST_ENABLE(0));
140 /* Disable system interrupts */
141 for (i = 0; i < num_reg; i++)
142 cp_intc_write(~0, CP_INTC_SYS_ENABLE_CLR(i));
144 /* Set to normal mode, no nesting, no priority hold */
145 cp_intc_write(0, CP_INTC_CTRL);
146 cp_intc_write(0, CP_INTC_HOST_CTRL);
148 /* Clear system interrupt status */
149 for (i = 0; i < num_reg; i++)
150 cp_intc_write(~0, CP_INTC_SYS_STAT_CLR(i));
152 /* Enable nIRQ (what about nFIQ?) */
153 cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
156 * Priority is determined by host channel: lower channel number has
157 * higher priority i.e. channel 0 has highest priority and channel 31
158 * had the lowest priority.
160 num_reg = (num_irq + 3) >> 2; /* 4 channels per register */
165 for (k = i = 0; i < num_reg; i++) {
166 for (val = j = 0; j < 4; j++, k++) {
169 val |= irq_prio[k] << 24;
172 cp_intc_write(val, CP_INTC_CHAN_MAP(i));
176 * Default everything to channel 15 if priority not specified.
177 * Note that channel 0-1 are mapped to nFIQ and channels 2-31
178 * are mapped to nIRQ.
180 for (i = 0; i < num_reg; i++)
181 cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i));
185 for (i = 0; host_map[i] != -1; i++)
186 cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i));
188 irq_base = irq_alloc_descs(-1, 0, num_irq, 0);
190 pr_warn("Couldn't allocate IRQ numbers\n");
194 /* create a legacy host */
195 cp_intc_domain = irq_domain_add_legacy(node, num_irq,
196 irq_base, 0, &cp_intc_host_ops, NULL);
198 if (!cp_intc_domain) {
199 pr_err("cp_intc: failed to allocate irq host!\n");
203 /* Enable global interrupt */
204 cp_intc_write(1, CP_INTC_GLOBAL_ENABLE);
209 void __init cp_intc_init(void)
211 __cp_intc_init(NULL);