arch/arm/mach-exynos/clock-exynos5.c

   1 /*
   2  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Clock support for EXYNOS5 SoCs
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/err.h>
  14 #include <linux/io.h>
  15 #include <linux/syscore_ops.h>
  16
  17 #include <plat/cpu-freq.h>
  18 #include <plat/clock.h>
  19 #include <plat/cpu.h>
  20 #include <plat/pll.h>
  21 #include <plat/s5p-clock.h>
  22 #include <plat/clock-clksrc.h>
  23 #include <plat/pm.h>
  24
  25 #include <mach/map.h>
  26 #include <mach/regs-clock.h>
  27 #include <mach/sysmmu.h>
  28
  29 #include "common.h"
  30
  31 #ifdef CONFIG_PM_SLEEP
  32 static struct sleep_save exynos5_clock_save[] = {
  33         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
  34         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
  35         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
  36         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
  37         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
  38         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
  39         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
  40         SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
  41         SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
  42         SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
  43         SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
  44         SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
  45         SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
  46         SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
  47         SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
  48         SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
  49         SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
  50         SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
  51         SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
  52         SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
  53         SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
  54         SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
  55         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
  56         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
  57         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
  58         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
  59         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
  60         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
  61         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
  62         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
  63         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
  64         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
  65         SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
  66         SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
  67         SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
  68         SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
  69         SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
  70         SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
  71         SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
  72         SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
  73         SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
  74         SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
  75         SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
  76         SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
  77         SAVE_ITEM(EXYNOS5_EPLL_CON0),
  78         SAVE_ITEM(EXYNOS5_EPLL_CON1),
  79         SAVE_ITEM(EXYNOS5_EPLL_CON2),
  80         SAVE_ITEM(EXYNOS5_VPLL_CON0),
  81         SAVE_ITEM(EXYNOS5_VPLL_CON1),
  82         SAVE_ITEM(EXYNOS5_VPLL_CON2),
  83 };
  84 #endif
  85
  86 static struct clk exynos5_clk_sclk_dptxphy = {
  87         .name           = "sclk_dptx",
  88 };
  89
  90 static struct clk exynos5_clk_sclk_hdmi24m = {
  91         .name           = "sclk_hdmi24m",
  92         .rate           = 24000000,
  93 };
  94
  95 static struct clk exynos5_clk_sclk_hdmi27m = {
  96         .name           = "sclk_hdmi27m",
  97         .rate           = 27000000,
  98 };
  99
 100 static struct clk exynos5_clk_sclk_hdmiphy = {
 101         .name           = "sclk_hdmiphy",
 102 };
 103
 104 static struct clk exynos5_clk_sclk_usbphy = {
 105         .name           = "sclk_usbphy",
 106         .rate           = 48000000,
 107 };
 108
 109 static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
 110 {
 111         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
 112 }
 113
 114 static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
 115 {
 116         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
 117 }
 118
 119 static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
 120 {
 121         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
 122 }
 123
 124 static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
 125 {
 126         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
 127 }
 128
 129 static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
 130 {
 131         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
 132 }
 133
 134 static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
 135 {
 136         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
 137 }
 138
 139 static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
 140 {
 141         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
 142 }
 143
 144 static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
 145 {
 146         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
 147 }
 148
 149 static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
 150 {
 151         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
 152 }
 153
 154 static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 155 {
 156         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
 157 }
 158
 159 static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
 160 {
 161         return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
 162 }
 163
 164 static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
 165 {
 166         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
 167 }
 168
 169 static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
 170 {
 171         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
 172 }
 173
 174 static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 175 {
 176         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
 177 }
 178
 179 static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
 180 {
 181         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
 182 }
 183
 184 static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
 185 {
 186         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
 187 }
 188
 189 static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
 190 {
 191         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
 192 }
 193
 194 static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
 195 {
 196         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
 197 }
 198
 199 static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
 200 {
 201         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
 202 }
 203
 204 /* Core list of CMU_CPU side */
 205
 206 static struct clksrc_clk exynos5_clk_mout_apll = {
 207         .clk    = {
 208                 .name           = "mout_apll",
 209         },
 210         .sources = &clk_src_apll,
 211         .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
 212 };
 213
 214 static struct clksrc_clk exynos5_clk_sclk_apll = {
 215         .clk    = {
 216                 .name           = "sclk_apll",
 217                 .parent         = &exynos5_clk_mout_apll.clk,
 218         },
 219         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
 220 };
 221
 222 static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
 223         .clk    = {
 224                 .name           = "mout_bpll_fout",
 225         },
 226         .sources = &clk_src_bpll_fout,
 227         .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
 228 };
 229
 230 static struct clk *exynos5_clk_src_bpll_list[] = {
 231         [0] = &clk_fin_bpll,
 232         [1] = &exynos5_clk_mout_bpll_fout.clk,
 233 };
 234
 235 static struct clksrc_sources exynos5_clk_src_bpll = {
 236         .sources        = exynos5_clk_src_bpll_list,
 237         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_list),
 238 };
 239
 240 static struct clksrc_clk exynos5_clk_mout_bpll = {
 241         .clk    = {
 242                 .name           = "mout_bpll",
 243         },
 244         .sources = &exynos5_clk_src_bpll,
 245         .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
 246 };
 247
 248 static struct clk *exynos5_clk_src_bpll_user_list[] = {
 249         [0] = &clk_fin_mpll,
 250         [1] = &exynos5_clk_mout_bpll.clk,
 251 };
 252
 253 static struct clksrc_sources exynos5_clk_src_bpll_user = {
 254         .sources        = exynos5_clk_src_bpll_user_list,
 255         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
 256 };
 257
 258 static struct clksrc_clk exynos5_clk_mout_bpll_user = {
 259         .clk    = {
 260                 .name           = "mout_bpll_user",
 261         },
 262         .sources = &exynos5_clk_src_bpll_user,
 263         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
 264 };
 265
 266 static struct clksrc_clk exynos5_clk_mout_cpll = {
 267         .clk    = {
 268                 .name           = "mout_cpll",
 269         },
 270         .sources = &clk_src_cpll,
 271         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
 272 };
 273
 274 static struct clksrc_clk exynos5_clk_mout_epll = {
 275         .clk    = {
 276                 .name           = "mout_epll",
 277         },
 278         .sources = &clk_src_epll,
 279         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
 280 };
 281
 282 static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
 283         .clk    = {
 284                 .name           = "mout_mpll_fout",
 285         },
 286         .sources = &clk_src_mpll_fout,
 287         .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
 288 };
 289
 290 static struct clk *exynos5_clk_src_mpll_list[] = {
 291         [0] = &clk_fin_mpll,
 292         [1] = &exynos5_clk_mout_mpll_fout.clk,
 293 };
 294
 295 static struct clksrc_sources exynos5_clk_src_mpll = {
 296         .sources        = exynos5_clk_src_mpll_list,
 297         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_list),
 298 };
 299
 300 struct clksrc_clk exynos5_clk_mout_mpll = {
 301         .clk = {
 302                 .name           = "mout_mpll",
 303         },
 304         .sources = &exynos5_clk_src_mpll,
 305         .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
 306 };
 307
 308 static struct clk *exynos_clkset_vpllsrc_list[] = {
 309         [0] = &clk_fin_vpll,
 310         [1] = &exynos5_clk_sclk_hdmi27m,
 311 };
 312
 313 static struct clksrc_sources exynos5_clkset_vpllsrc = {
 314         .sources        = exynos_clkset_vpllsrc_list,
 315         .nr_sources     = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
 316 };
 317
 318 static struct clksrc_clk exynos5_clk_vpllsrc = {
 319         .clk    = {
 320                 .name           = "vpll_src",
 321                 .enable         = exynos5_clksrc_mask_top_ctrl,
 322                 .ctrlbit        = (1 << 0),
 323         },
 324         .sources = &exynos5_clkset_vpllsrc,
 325         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
 326 };
 327
 328 static struct clk *exynos5_clkset_sclk_vpll_list[] = {
 329         [0] = &exynos5_clk_vpllsrc.clk,
 330         [1] = &clk_fout_vpll,
 331 };
 332
 333 static struct clksrc_sources exynos5_clkset_sclk_vpll = {
 334         .sources        = exynos5_clkset_sclk_vpll_list,
 335         .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
 336 };
 337
 338 static struct clksrc_clk exynos5_clk_sclk_vpll = {
 339         .clk    = {
 340                 .name           = "sclk_vpll",
 341         },
 342         .sources = &exynos5_clkset_sclk_vpll,
 343         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
 344 };
 345
 346 static struct clksrc_clk exynos5_clk_sclk_pixel = {
 347         .clk    = {
 348                 .name           = "sclk_pixel",
 349                 .parent         = &exynos5_clk_sclk_vpll.clk,
 350         },
 351         .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
 352 };
 353
 354 static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
 355         [0] = &exynos5_clk_sclk_pixel.clk,
 356         [1] = &exynos5_clk_sclk_hdmiphy,
 357 };
 358
 359 static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
 360         .sources        = exynos5_clkset_sclk_hdmi_list,
 361         .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
 362 };
 363
 364 static struct clksrc_clk exynos5_clk_sclk_hdmi = {
 365         .clk    = {
 366                 .name           = "sclk_hdmi",
 367                 .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
 368                 .ctrlbit        = (1 << 20),
 369         },
 370         .sources = &exynos5_clkset_sclk_hdmi,
 371         .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
 372 };
 373
 374 static struct clksrc_clk *exynos5_sclk_tv[] = {
 375         &exynos5_clk_sclk_pixel,
 376         &exynos5_clk_sclk_hdmi,
 377 };
 378
 379 static struct clk *exynos5_clk_src_mpll_user_list[] = {
 380         [0] = &clk_fin_mpll,
 381         [1] = &exynos5_clk_mout_mpll.clk,
 382 };
 383
 384 static struct clksrc_sources exynos5_clk_src_mpll_user = {
 385         .sources        = exynos5_clk_src_mpll_user_list,
 386         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
 387 };
 388
 389 static struct clksrc_clk exynos5_clk_mout_mpll_user = {
 390         .clk    = {
 391                 .name           = "mout_mpll_user",
 392         },
 393         .sources = &exynos5_clk_src_mpll_user,
 394         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
 395 };
 396
 397 static struct clk *exynos5_clkset_mout_cpu_list[] = {
 398         [0] = &exynos5_clk_mout_apll.clk,
 399         [1] = &exynos5_clk_mout_mpll.clk,
 400 };
 401
 402 static struct clksrc_sources exynos5_clkset_mout_cpu = {
 403         .sources        = exynos5_clkset_mout_cpu_list,
 404         .nr_sources     = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
 405 };
 406
 407 static struct clksrc_clk exynos5_clk_mout_cpu = {
 408         .clk    = {
 409                 .name           = "mout_cpu",
 410         },
 411         .sources = &exynos5_clkset_mout_cpu,
 412         .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
 413 };
 414
 415 static struct clksrc_clk exynos5_clk_dout_armclk = {
 416         .clk    = {
 417                 .name           = "dout_armclk",
 418                 .parent         = &exynos5_clk_mout_cpu.clk,
 419         },
 420         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
 421 };
 422
 423 static struct clksrc_clk exynos5_clk_dout_arm2clk = {
 424         .clk    = {
 425                 .name           = "dout_arm2clk",
 426                 .parent         = &exynos5_clk_dout_armclk.clk,
 427         },
 428         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
 429 };
 430
 431 static struct clk exynos5_clk_armclk = {
 432         .name           = "armclk",
 433         .parent         = &exynos5_clk_dout_arm2clk.clk,
 434 };
 435
 436 /* Core list of CMU_CDREX side */
 437
 438 static struct clk *exynos5_clkset_cdrex_list[] = {
 439         [0] = &exynos5_clk_mout_mpll.clk,
 440         [1] = &exynos5_clk_mout_bpll.clk,
 441 };
 442
 443 static struct clksrc_sources exynos5_clkset_cdrex = {
 444         .sources        = exynos5_clkset_cdrex_list,
 445         .nr_sources     = ARRAY_SIZE(exynos5_clkset_cdrex_list),
 446 };
 447
 448 static struct clksrc_clk exynos5_clk_cdrex = {
 449         .clk    = {
 450                 .name           = "clk_cdrex",
 451         },
 452         .sources = &exynos5_clkset_cdrex,
 453         .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
 454         .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
 455 };
 456
 457 static struct clksrc_clk exynos5_clk_aclk_acp = {
 458         .clk    = {
 459                 .name           = "aclk_acp",
 460                 .parent         = &exynos5_clk_mout_mpll.clk,
 461         },
 462         .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
 463 };
 464
 465 static struct clksrc_clk exynos5_clk_pclk_acp = {
 466         .clk    = {
 467                 .name           = "pclk_acp",
 468                 .parent         = &exynos5_clk_aclk_acp.clk,
 469         },
 470         .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
 471 };
 472
 473 /* Core list of CMU_TOP side */
 474
 475 struct clk *exynos5_clkset_aclk_top_list[] = {
 476         [0] = &exynos5_clk_mout_mpll_user.clk,
 477         [1] = &exynos5_clk_mout_bpll_user.clk,
 478 };
 479
 480 struct clksrc_sources exynos5_clkset_aclk = {
 481         .sources        = exynos5_clkset_aclk_top_list,
 482         .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
 483 };
 484
 485 static struct clksrc_clk exynos5_clk_aclk_400 = {
 486         .clk    = {
 487                 .name           = "aclk_400",
 488         },
 489         .sources = &exynos5_clkset_aclk,
 490         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
 491         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
 492 };
 493
 494 struct clk *exynos5_clkset_aclk_333_166_list[] = {
 495         [0] = &exynos5_clk_mout_cpll.clk,
 496         [1] = &exynos5_clk_mout_mpll_user.clk,
 497 };
 498
 499 struct clksrc_sources exynos5_clkset_aclk_333_166 = {
 500         .sources        = exynos5_clkset_aclk_333_166_list,
 501         .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
 502 };
 503
 504 static struct clksrc_clk exynos5_clk_aclk_333 = {
 505         .clk    = {
 506                 .name           = "aclk_333",
 507         },
 508         .sources = &exynos5_clkset_aclk_333_166,
 509         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
 510         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
 511 };
 512
 513 static struct clksrc_clk exynos5_clk_aclk_166 = {
 514         .clk    = {
 515                 .name           = "aclk_166",
 516         },
 517         .sources = &exynos5_clkset_aclk_333_166,
 518         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
 519         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
 520 };
 521
 522 static struct clksrc_clk exynos5_clk_aclk_266 = {
 523         .clk    = {
 524                 .name           = "aclk_266",
 525                 .parent         = &exynos5_clk_mout_mpll_user.clk,
 526         },
 527         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
 528 };
 529
 530 static struct clksrc_clk exynos5_clk_aclk_200 = {
 531         .clk    = {
 532                 .name           = "aclk_200",
 533         },
 534         .sources = &exynos5_clkset_aclk,
 535         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
 536         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
 537 };
 538
 539 static struct clksrc_clk exynos5_clk_aclk_66_pre = {
 540         .clk    = {
 541                 .name           = "aclk_66_pre",
 542                 .parent         = &exynos5_clk_mout_mpll_user.clk,
 543         },
 544         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
 545 };
 546
 547 static struct clksrc_clk exynos5_clk_aclk_66 = {
 548         .clk    = {
 549                 .name           = "aclk_66",
 550                 .parent         = &exynos5_clk_aclk_66_pre.clk,
 551         },
 552         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
 553 };
 554
 555 static struct clk exynos5_init_clocks_off[] = {
 556         {
 557                 .name           = "timers",
 558                 .parent         = &exynos5_clk_aclk_66.clk,
 559                 .enable         = exynos5_clk_ip_peric_ctrl,
 560                 .ctrlbit        = (1 << 24),
 561         }, {
 562                 .name           = "rtc",
 563                 .parent         = &exynos5_clk_aclk_66.clk,
 564                 .enable         = exynos5_clk_ip_peris_ctrl,
 565                 .ctrlbit        = (1 << 20),
 566         }, {
 567                 .name           = "watchdog",
 568                 .parent         = &exynos5_clk_aclk_66.clk,
 569                 .enable         = exynos5_clk_ip_peris_ctrl,
 570                 .ctrlbit        = (1 << 19),
 571         }, {
 572                 .name           = "biu",        /* bus interface unit clock */
 573                 .devname        = "dw_mmc.0",
 574                 .parent         = &exynos5_clk_aclk_200.clk,
 575                 .enable         = exynos5_clk_ip_fsys_ctrl,
 576                 .ctrlbit        = (1 << 12),
 577         }, {
 578                 .name           = "biu",
 579                 .devname        = "dw_mmc.1",
 580                 .parent         = &exynos5_clk_aclk_200.clk,
 581                 .enable         = exynos5_clk_ip_fsys_ctrl,
 582                 .ctrlbit        = (1 << 13),
 583         }, {
 584                 .name           = "biu",
 585                 .devname        = "dw_mmc.2",
 586                 .parent         = &exynos5_clk_aclk_200.clk,
 587                 .enable         = exynos5_clk_ip_fsys_ctrl,
 588                 .ctrlbit        = (1 << 14),
 589         }, {
 590                 .name           = "biu",
 591                 .devname        = "dw_mmc.3",
 592                 .parent         = &exynos5_clk_aclk_200.clk,
 593                 .enable         = exynos5_clk_ip_fsys_ctrl,
 594                 .ctrlbit        = (1 << 15),
 595         }, {
 596                 .name           = "sata",
 597                 .devname        = "ahci",
 598                 .enable         = exynos5_clk_ip_fsys_ctrl,
 599                 .ctrlbit        = (1 << 6),
 600         }, {
 601                 .name           = "sata_phy",
 602                 .enable         = exynos5_clk_ip_fsys_ctrl,
 603                 .ctrlbit        = (1 << 24),
 604         }, {
 605                 .name           = "sata_phy_i2c",
 606                 .enable         = exynos5_clk_ip_fsys_ctrl,
 607                 .ctrlbit        = (1 << 25),
 608         }, {
 609                 .name           = "mfc",
 610                 .devname        = "s5p-mfc",
 611                 .enable         = exynos5_clk_ip_mfc_ctrl,
 612                 .ctrlbit        = (1 << 0),
 613         }, {
 614                 .name           = "hdmi",
 615                 .devname        = "exynos4-hdmi",
 616                 .enable         = exynos5_clk_ip_disp1_ctrl,
 617                 .ctrlbit        = (1 << 6),
 618         }, {
 619                 .name           = "mixer",
 620                 .devname        = "s5p-mixer",
 621                 .enable         = exynos5_clk_ip_disp1_ctrl,
 622                 .ctrlbit        = (1 << 5),
 623         }, {
 624                 .name           = "jpeg",
 625                 .enable         = exynos5_clk_ip_gen_ctrl,
 626                 .ctrlbit        = (1 << 2),
 627         }, {
 628                 .name           = "dsim0",
 629                 .enable         = exynos5_clk_ip_disp1_ctrl,
 630                 .ctrlbit        = (1 << 3),
 631         }, {
 632                 .name           = "iis",
 633                 .devname        = "samsung-i2s.1",
 634                 .enable         = exynos5_clk_ip_peric_ctrl,
 635                 .ctrlbit        = (1 << 20),
 636         }, {
 637                 .name           = "iis",
 638                 .devname        = "samsung-i2s.2",
 639                 .enable         = exynos5_clk_ip_peric_ctrl,
 640                 .ctrlbit        = (1 << 21),
 641         }, {
 642                 .name           = "pcm",
 643                 .devname        = "samsung-pcm.1",
 644                 .enable         = exynos5_clk_ip_peric_ctrl,
 645                 .ctrlbit        = (1 << 22),
 646         }, {
 647                 .name           = "pcm",
 648                 .devname        = "samsung-pcm.2",
 649                 .enable         = exynos5_clk_ip_peric_ctrl,
 650                 .ctrlbit        = (1 << 23),
 651         }, {
 652                 .name           = "spdif",
 653                 .devname        = "samsung-spdif",
 654                 .enable         = exynos5_clk_ip_peric_ctrl,
 655                 .ctrlbit        = (1 << 26),
 656         }, {
 657                 .name           = "ac97",
 658                 .devname        = "samsung-ac97",
 659                 .enable         = exynos5_clk_ip_peric_ctrl,
 660                 .ctrlbit        = (1 << 27),
 661         }, {
 662                 .name           = "usbhost",
 663                 .enable         = exynos5_clk_ip_fsys_ctrl ,
 664                 .ctrlbit        = (1 << 18),
 665         }, {
 666                 .name           = "usbotg",
 667                 .enable         = exynos5_clk_ip_fsys_ctrl,
 668                 .ctrlbit        = (1 << 7),
 669         }, {
 670                 .name           = "gps",
 671                 .enable         = exynos5_clk_ip_gps_ctrl,
 672                 .ctrlbit        = ((1 << 3) | (1 << 2) | (1 << 0)),
 673         }, {
 674                 .name           = "nfcon",
 675                 .enable         = exynos5_clk_ip_fsys_ctrl,
 676                 .ctrlbit        = (1 << 22),
 677         }, {
 678                 .name           = "iop",
 679                 .enable         = exynos5_clk_ip_fsys_ctrl,
 680                 .ctrlbit        = ((1 << 30) | (1 << 26) | (1 << 23)),
 681         }, {
 682                 .name           = "core_iop",
 683                 .enable         = exynos5_clk_ip_core_ctrl,
 684                 .ctrlbit        = ((1 << 21) | (1 << 3)),
 685         }, {
 686                 .name           = "mcu_iop",
 687                 .enable         = exynos5_clk_ip_fsys_ctrl,
 688                 .ctrlbit        = (1 << 0),
 689         }, {
 690                 .name           = "i2c",
 691                 .devname        = "s3c2440-i2c.0",
 692                 .parent         = &exynos5_clk_aclk_66.clk,
 693                 .enable         = exynos5_clk_ip_peric_ctrl,
 694                 .ctrlbit        = (1 << 6),
 695         }, {
 696                 .name           = "i2c",
 697                 .devname        = "s3c2440-i2c.1",
 698                 .parent         = &exynos5_clk_aclk_66.clk,
 699                 .enable         = exynos5_clk_ip_peric_ctrl,
 700                 .ctrlbit        = (1 << 7),
 701         }, {
 702                 .name           = "i2c",
 703                 .devname        = "s3c2440-i2c.2",
 704                 .parent         = &exynos5_clk_aclk_66.clk,
 705                 .enable         = exynos5_clk_ip_peric_ctrl,
 706                 .ctrlbit        = (1 << 8),
 707         }, {
 708                 .name           = "i2c",
 709                 .devname        = "s3c2440-i2c.3",
 710                 .parent         = &exynos5_clk_aclk_66.clk,
 711                 .enable         = exynos5_clk_ip_peric_ctrl,
 712                 .ctrlbit        = (1 << 9),
 713         }, {
 714                 .name           = "i2c",
 715                 .devname        = "s3c2440-i2c.4",
 716                 .parent         = &exynos5_clk_aclk_66.clk,
 717                 .enable         = exynos5_clk_ip_peric_ctrl,
 718                 .ctrlbit        = (1 << 10),
 719         }, {
 720                 .name           = "i2c",
 721                 .devname        = "s3c2440-i2c.5",
 722                 .parent         = &exynos5_clk_aclk_66.clk,
 723                 .enable         = exynos5_clk_ip_peric_ctrl,
 724                 .ctrlbit        = (1 << 11),
 725         }, {
 726                 .name           = "i2c",
 727                 .devname        = "s3c2440-i2c.6",
 728                 .parent         = &exynos5_clk_aclk_66.clk,
 729                 .enable         = exynos5_clk_ip_peric_ctrl,
 730                 .ctrlbit        = (1 << 12),
 731         }, {
 732                 .name           = "i2c",
 733                 .devname        = "s3c2440-i2c.7",
 734                 .parent         = &exynos5_clk_aclk_66.clk,
 735                 .enable         = exynos5_clk_ip_peric_ctrl,
 736                 .ctrlbit        = (1 << 13),
 737         }, {
 738                 .name           = "i2c",
 739                 .devname        = "s3c2440-hdmiphy-i2c",
 740                 .parent         = &exynos5_clk_aclk_66.clk,
 741                 .enable         = exynos5_clk_ip_peric_ctrl,
 742                 .ctrlbit        = (1 << 14),
 743         }, {
 744                 .name           = "spi",
 745                 .devname        = "exynos4210-spi.0",
 746                 .parent         = &exynos5_clk_aclk_66.clk,
 747                 .enable         = exynos5_clk_ip_peric_ctrl,
 748                 .ctrlbit        = (1 << 16),
 749         }, {
 750                 .name           = "spi",
 751                 .devname        = "exynos4210-spi.1",
 752                 .parent         = &exynos5_clk_aclk_66.clk,
 753                 .enable         = exynos5_clk_ip_peric_ctrl,
 754                 .ctrlbit        = (1 << 17),
 755         }, {
 756                 .name           = "spi",
 757                 .devname        = "exynos4210-spi.2",
 758                 .parent         = &exynos5_clk_aclk_66.clk,
 759                 .enable         = exynos5_clk_ip_peric_ctrl,
 760                 .ctrlbit        = (1 << 18),
 761         }, {
 762                 .name           = SYSMMU_CLOCK_NAME,
 763                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
 764                 .enable         = &exynos5_clk_ip_mfc_ctrl,
 765                 .ctrlbit        = (1 << 1),
 766         }, {
 767                 .name           = SYSMMU_CLOCK_NAME,
 768                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
 769                 .enable         = &exynos5_clk_ip_mfc_ctrl,
 770                 .ctrlbit        = (1 << 2),
 771         }, {
 772                 .name           = SYSMMU_CLOCK_NAME,
 773                 .devname        = SYSMMU_CLOCK_DEVNAME(tv, 2),
 774                 .enable         = &exynos5_clk_ip_disp1_ctrl,
 775                 .ctrlbit        = (1 << 9)
 776         }, {
 777                 .name           = SYSMMU_CLOCK_NAME,
 778                 .devname        = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
 779                 .enable         = &exynos5_clk_ip_gen_ctrl,
 780                 .ctrlbit        = (1 << 7),
 781         }, {
 782                 .name           = SYSMMU_CLOCK_NAME,
 783                 .devname        = SYSMMU_CLOCK_DEVNAME(rot, 4),
 784                 .enable         = &exynos5_clk_ip_gen_ctrl,
 785                 .ctrlbit        = (1 << 6)
 786         }, {
 787                 .name           = SYSMMU_CLOCK_NAME,
 788                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc0, 5),
 789                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 790                 .ctrlbit        = (1 << 7),
 791         }, {
 792                 .name           = SYSMMU_CLOCK_NAME,
 793                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc1, 6),
 794                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 795                 .ctrlbit        = (1 << 8),
 796         }, {
 797                 .name           = SYSMMU_CLOCK_NAME,
 798                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc2, 7),
 799                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 800                 .ctrlbit        = (1 << 9),
 801         }, {
 802                 .name           = SYSMMU_CLOCK_NAME,
 803                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc3, 8),
 804                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 805                 .ctrlbit        = (1 << 10),
 806         }, {
 807                 .name           = SYSMMU_CLOCK_NAME,
 808                 .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
 809                 .enable         = &exynos5_clk_ip_isp0_ctrl,
 810                 .ctrlbit        = (0x3F << 8),
 811         }, {
 812                 .name           = SYSMMU_CLOCK_NAME2,
 813                 .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
 814                 .enable         = &exynos5_clk_ip_isp1_ctrl,
 815                 .ctrlbit        = (0xF << 4),
 816         }, {
 817                 .name           = SYSMMU_CLOCK_NAME,
 818                 .devname        = SYSMMU_CLOCK_DEVNAME(camif0, 12),
 819                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 820                 .ctrlbit        = (1 << 11),
 821         }, {
 822                 .name           = SYSMMU_CLOCK_NAME,
 823                 .devname        = SYSMMU_CLOCK_DEVNAME(camif1, 13),
 824                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 825                 .ctrlbit        = (1 << 12),
 826         }, {
 827                 .name           = SYSMMU_CLOCK_NAME,
 828                 .devname        = SYSMMU_CLOCK_DEVNAME(2d, 14),
 829                 .enable         = &exynos5_clk_ip_acp_ctrl,
 830                 .ctrlbit        = (1 << 7)
 831         }
 832 };
 833
 834 static struct clk exynos5_init_clocks_on[] = {
 835         {
 836                 .name           = "uart",
 837                 .devname        = "s5pv210-uart.0",
 838                 .enable         = exynos5_clk_ip_peric_ctrl,
 839                 .ctrlbit        = (1 << 0),
 840         }, {
 841                 .name           = "uart",
 842                 .devname        = "s5pv210-uart.1",
 843                 .enable         = exynos5_clk_ip_peric_ctrl,
 844                 .ctrlbit        = (1 << 1),
 845         }, {
 846                 .name           = "uart",
 847                 .devname        = "s5pv210-uart.2",
 848                 .enable         = exynos5_clk_ip_peric_ctrl,
 849                 .ctrlbit        = (1 << 2),
 850         }, {
 851                 .name           = "uart",
 852                 .devname        = "s5pv210-uart.3",
 853                 .enable         = exynos5_clk_ip_peric_ctrl,
 854                 .ctrlbit        = (1 << 3),
 855         }, {
 856                 .name           = "uart",
 857                 .devname        = "s5pv210-uart.4",
 858                 .enable         = exynos5_clk_ip_peric_ctrl,
 859                 .ctrlbit        = (1 << 4),
 860         }, {
 861                 .name           = "uart",
 862                 .devname        = "s5pv210-uart.5",
 863                 .enable         = exynos5_clk_ip_peric_ctrl,
 864                 .ctrlbit        = (1 << 5),
 865         }
 866 };
 867
 868 static struct clk exynos5_clk_pdma0 = {
 869         .name           = "dma",
 870         .devname        = "dma-pl330.0",
 871         .enable         = exynos5_clk_ip_fsys_ctrl,
 872         .ctrlbit        = (1 << 1),
 873 };
 874
 875 static struct clk exynos5_clk_pdma1 = {
 876         .name           = "dma",
 877         .devname        = "dma-pl330.1",
 878         .enable         = exynos5_clk_ip_fsys_ctrl,
 879         .ctrlbit        = (1 << 2),
 880 };
 881
 882 static struct clk exynos5_clk_mdma1 = {
 883         .name           = "dma",
 884         .devname        = "dma-pl330.2",
 885         .enable         = exynos5_clk_ip_gen_ctrl,
 886         .ctrlbit        = (1 << 4),
 887 };
 888
 889 struct clk *exynos5_clkset_group_list[] = {
 890         [0] = &clk_ext_xtal_mux,
 891         [1] = NULL,
 892         [2] = &exynos5_clk_sclk_hdmi24m,
 893         [3] = &exynos5_clk_sclk_dptxphy,
 894         [4] = &exynos5_clk_sclk_usbphy,
 895         [5] = &exynos5_clk_sclk_hdmiphy,
 896         [6] = &exynos5_clk_mout_mpll_user.clk,
 897         [7] = &exynos5_clk_mout_epll.clk,
 898         [8] = &exynos5_clk_sclk_vpll.clk,
 899         [9] = &exynos5_clk_mout_cpll.clk,
 900 };
 901
 902 struct clksrc_sources exynos5_clkset_group = {
 903         .sources        = exynos5_clkset_group_list,
 904         .nr_sources     = ARRAY_SIZE(exynos5_clkset_group_list),
 905 };
 906
 907 /* Possible clock sources for aclk_266_gscl_sub Mux */
 908 static struct clk *clk_src_gscl_266_list[] = {
 909         [0] = &clk_ext_xtal_mux,
 910         [1] = &exynos5_clk_aclk_266.clk,
 911 };
 912
 913 static struct clksrc_sources clk_src_gscl_266 = {
 914         .sources        = clk_src_gscl_266_list,
 915         .nr_sources     = ARRAY_SIZE(clk_src_gscl_266_list),
 916 };
 917
 918 static struct clksrc_clk exynos5_clk_dout_mmc0 = {
 919         .clk            = {
 920                 .name           = "dout_mmc0",
 921         },
 922         .sources = &exynos5_clkset_group,
 923         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
 924         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
 925 };
 926
 927 static struct clksrc_clk exynos5_clk_dout_mmc1 = {
 928         .clk            = {
 929                 .name           = "dout_mmc1",
 930         },
 931         .sources = &exynos5_clkset_group,
 932         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
 933         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
 934 };
 935
 936 static struct clksrc_clk exynos5_clk_dout_mmc2 = {
 937         .clk            = {
 938                 .name           = "dout_mmc2",
 939         },
 940         .sources = &exynos5_clkset_group,
 941         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
 942         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
 943 };
 944
 945 static struct clksrc_clk exynos5_clk_dout_mmc3 = {
 946         .clk            = {
 947                 .name           = "dout_mmc3",
 948         },
 949         .sources = &exynos5_clkset_group,
 950         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
 951         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
 952 };
 953
 954 static struct clksrc_clk exynos5_clk_dout_mmc4 = {
 955         .clk            = {
 956                 .name           = "dout_mmc4",
 957         },
 958         .sources = &exynos5_clkset_group,
 959         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
 960         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
 961 };
 962
 963 static struct clksrc_clk exynos5_clk_sclk_uart0 = {
 964         .clk    = {
 965                 .name           = "uclk1",
 966                 .devname        = "exynos4210-uart.0",
 967                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
 968                 .ctrlbit        = (1 << 0),
 969         },
 970         .sources = &exynos5_clkset_group,
 971         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
 972         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
 973 };
 974
 975 static struct clksrc_clk exynos5_clk_sclk_uart1 = {
 976         .clk    = {
 977                 .name           = "uclk1",
 978                 .devname        = "exynos4210-uart.1",
 979                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
 980                 .ctrlbit        = (1 << 4),
 981         },
 982         .sources = &exynos5_clkset_group,
 983         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
 984         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
 985 };
 986
 987 static struct clksrc_clk exynos5_clk_sclk_uart2 = {
 988         .clk    = {
 989                 .name           = "uclk1",
 990                 .devname        = "exynos4210-uart.2",
 991                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
 992                 .ctrlbit        = (1 << 8),
 993         },
 994         .sources = &exynos5_clkset_group,
 995         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
 996         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
 997 };
 998
 999 static struct clksrc_clk exynos5_clk_sclk_uart3 = {
1000         .clk    = {
1001                 .name           = "uclk1",
1002                 .devname        = "exynos4210-uart.3",
1003                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
1004                 .ctrlbit        = (1 << 12),
1005         },
1006         .sources = &exynos5_clkset_group,
1007         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
1008         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
1009 };
1010
1011 static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
1012         .clk    = {
1013                 .name           = "ciu",        /* card interface unit clock */
1014                 .devname        = "dw_mmc.0",
1015                 .parent         = &exynos5_clk_dout_mmc0.clk,
1016                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1017                 .ctrlbit        = (1 << 0),
1018         },
1019         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1020 };
1021
1022 static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
1023         .clk    = {
1024                 .name           = "ciu",
1025                 .devname        = "dw_mmc.1",
1026                 .parent         = &exynos5_clk_dout_mmc1.clk,
1027                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1028                 .ctrlbit        = (1 << 4),
1029         },
1030         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1031 };
1032
1033 static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
1034         .clk    = {
1035                 .name           = "ciu",
1036                 .devname        = "dw_mmc.2",
1037                 .parent         = &exynos5_clk_dout_mmc2.clk,
1038                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1039                 .ctrlbit        = (1 << 8),
1040         },
1041         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1042 };
1043
1044 static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
1045         .clk    = {
1046                 .name           = "ciu",
1047                 .devname        = "dw_mmc.3",
1048                 .parent         = &exynos5_clk_dout_mmc3.clk,
1049                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1050                 .ctrlbit        = (1 << 12),
1051         },
1052         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1053 };
1054
1055 static struct clksrc_clk exynos5_clk_mdout_spi0 = {
1056         .clk    = {
1057                 .name           = "mdout_spi",
1058                 .devname        = "exynos4210-spi.0",
1059         },
1060         .sources = &exynos5_clkset_group,
1061         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
1062         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
1063 };
1064
1065 static struct clksrc_clk exynos5_clk_mdout_spi1 = {
1066         .clk    = {
1067                 .name           = "mdout_spi",
1068                 .devname        = "exynos4210-spi.1",
1069         },
1070         .sources = &exynos5_clkset_group,
1071         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
1072         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
1073 };
1074
1075 static struct clksrc_clk exynos5_clk_mdout_spi2 = {
1076         .clk    = {
1077                 .name           = "mdout_spi",
1078                 .devname        = "exynos4210-spi.2",
1079         },
1080         .sources = &exynos5_clkset_group,
1081         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
1082         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
1083 };
1084
1085 static struct clksrc_clk exynos5_clk_sclk_spi0 = {
1086         .clk    = {
1087                 .name           = "sclk_spi",
1088                 .devname        = "exynos4210-spi.0",
1089                 .parent         = &exynos5_clk_mdout_spi0.clk,
1090                 .enable         = exynos5_clksrc_mask_peric1_ctrl,
1091                 .ctrlbit        = (1 << 16),
1092         },
1093         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
1094 };
1095
1096 static struct clksrc_clk exynos5_clk_sclk_spi1 = {
1097         .clk    = {
1098                 .name           = "sclk_spi",
1099                 .devname        = "exynos4210-spi.1",
1100                 .parent         = &exynos5_clk_mdout_spi1.clk,
1101                 .enable         = exynos5_clksrc_mask_peric1_ctrl,
1102                 .ctrlbit        = (1 << 20),
1103         },
1104         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
1105 };
1106
1107 static struct clksrc_clk exynos5_clk_sclk_spi2 = {
1108         .clk    = {
1109                 .name           = "sclk_spi",
1110                 .devname        = "exynos4210-spi.2",
1111                 .parent         = &exynos5_clk_mdout_spi2.clk,
1112                 .enable         = exynos5_clksrc_mask_peric1_ctrl,
1113                 .ctrlbit        = (1 << 24),
1114         },
1115         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
1116 };
1117
1118 static struct clksrc_clk exynos5_clksrcs[] = {
1119         {
1120                 .clk    = {
1121                         .name           = "sclk_fimd",
1122                         .devname        = "s3cfb.1",
1123                         .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
1124                         .ctrlbit        = (1 << 0),
1125                 },
1126                 .sources = &exynos5_clkset_group,
1127                 .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
1128                 .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
1129         }, {
1130                 .clk    = {
1131                         .name           = "aclk_266_gscl",
1132                 },
1133                 .sources = &clk_src_gscl_266,
1134                 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
1135         }, {
1136                 .clk    = {
1137                         .name           = "sclk_g3d",
1138                         .devname        = "mali-t604.0",
1139                         .enable         = exynos5_clk_block_ctrl,
1140                         .ctrlbit        = (1 << 1),
1141                 },
1142                 .sources = &exynos5_clkset_aclk,
1143                 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
1144                 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
1145         }, {
1146                 .clk    = {
1147                         .name           = "sclk_gscl_wrap",
1148                         .devname        = "s5p-mipi-csis.0",
1149                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1150                         .ctrlbit        = (1 << 24),
1151                 },
1152                 .sources = &exynos5_clkset_group,
1153                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
1154                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
1155         }, {
1156                 .clk    = {
1157                         .name           = "sclk_gscl_wrap",
1158                         .devname        = "s5p-mipi-csis.1",
1159                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1160                         .ctrlbit        = (1 << 28),
1161                 },
1162                 .sources = &exynos5_clkset_group,
1163                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
1164                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
1165         }, {
1166                 .clk    = {
1167                         .name           = "sclk_cam0",
1168                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1169                         .ctrlbit        = (1 << 16),
1170                 },
1171                 .sources = &exynos5_clkset_group,
1172                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
1173                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
1174         }, {
1175                 .clk    = {
1176                         .name           = "sclk_cam1",
1177                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1178                         .ctrlbit        = (1 << 20),
1179                 },
1180                 .sources = &exynos5_clkset_group,
1181                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
1182                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
1183         }, {
1184                 .clk    = {
1185                         .name           = "sclk_jpeg",
1186                         .parent         = &exynos5_clk_mout_cpll.clk,
1187                 },
1188                 .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
1189         },
1190 };
1191
1192 /* Clock initialization code */
1193 static struct clksrc_clk *exynos5_sysclks[] = {
1194         &exynos5_clk_mout_apll,
1195         &exynos5_clk_sclk_apll,
1196         &exynos5_clk_mout_bpll,
1197         &exynos5_clk_mout_bpll_fout,
1198         &exynos5_clk_mout_bpll_user,
1199         &exynos5_clk_mout_cpll,
1200         &exynos5_clk_mout_epll,
1201         &exynos5_clk_mout_mpll,
1202         &exynos5_clk_mout_mpll_fout,
1203         &exynos5_clk_mout_mpll_user,
1204         &exynos5_clk_vpllsrc,
1205         &exynos5_clk_sclk_vpll,
1206         &exynos5_clk_mout_cpu,
1207         &exynos5_clk_dout_armclk,
1208         &exynos5_clk_dout_arm2clk,
1209         &exynos5_clk_cdrex,
1210         &exynos5_clk_aclk_400,
1211         &exynos5_clk_aclk_333,
1212         &exynos5_clk_aclk_266,
1213         &exynos5_clk_aclk_200,
1214         &exynos5_clk_aclk_166,
1215         &exynos5_clk_aclk_66_pre,
1216         &exynos5_clk_aclk_66,
1217         &exynos5_clk_dout_mmc0,
1218         &exynos5_clk_dout_mmc1,
1219         &exynos5_clk_dout_mmc2,
1220         &exynos5_clk_dout_mmc3,
1221         &exynos5_clk_dout_mmc4,
1222         &exynos5_clk_aclk_acp,
1223         &exynos5_clk_pclk_acp,
1224         &exynos5_clk_sclk_spi0,
1225         &exynos5_clk_sclk_spi1,
1226         &exynos5_clk_sclk_spi2,
1227         &exynos5_clk_mdout_spi0,
1228         &exynos5_clk_mdout_spi1,
1229         &exynos5_clk_mdout_spi2,
1230 };
1231
1232 static struct clk *exynos5_clk_cdev[] = {
1233         &exynos5_clk_pdma0,
1234         &exynos5_clk_pdma1,
1235         &exynos5_clk_mdma1,
1236 };
1237
1238 static struct clksrc_clk *exynos5_clksrc_cdev[] = {
1239         &exynos5_clk_sclk_uart0,
1240         &exynos5_clk_sclk_uart1,
1241         &exynos5_clk_sclk_uart2,
1242         &exynos5_clk_sclk_uart3,
1243         &exynos5_clk_sclk_mmc0,
1244         &exynos5_clk_sclk_mmc1,
1245         &exynos5_clk_sclk_mmc2,
1246         &exynos5_clk_sclk_mmc3,
1247 };
1248
1249 static struct clk_lookup exynos5_clk_lookup[] = {
1250         CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
1251         CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
1252         CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
1253         CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
1254         CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
1255         CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
1256         CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
1257         CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
1258         CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
1259         CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
1260         CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
1261         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
1262         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
1263         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
1264 };
1265
1266 static unsigned long exynos5_epll_get_rate(struct clk *clk)
1267 {
1268         return clk->rate;
1269 }
1270
1271 static struct clk *exynos5_clks[] __initdata = {
1272         &exynos5_clk_sclk_hdmi27m,
1273         &exynos5_clk_sclk_hdmiphy,
1274         &clk_fout_bpll,
1275         &clk_fout_bpll_div2,
1276         &clk_fout_cpll,
1277         &clk_fout_mpll_div2,
1278         &exynos5_clk_armclk,
1279 };
1280
1281 static u32 epll_div[][6] = {
1282         { 192000000, 0, 48, 3, 1, 0 },
1283         { 180000000, 0, 45, 3, 1, 0 },
1284         {  73728000, 1, 73, 3, 3, 47710 },
1285         {  67737600, 1, 90, 4, 3, 20762 },
1286         {  49152000, 0, 49, 3, 3, 9961 },
1287         {  45158400, 0, 45, 3, 3, 10381 },
1288         { 180633600, 0, 45, 3, 1, 10381 },
1289 };
1290
1291 static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
1292 {
1293         unsigned int epll_con, epll_con_k;
1294         unsigned int i;
1295         unsigned int tmp;
1296         unsigned int epll_rate;
1297         unsigned int locktime;
1298         unsigned int lockcnt;
1299
1300         /* Return if nothing changed */
1301         if (clk->rate == rate)
1302                 return 0;
1303
1304         if (clk->parent)
1305                 epll_rate = clk_get_rate(clk->parent);
1306         else
1307                 epll_rate = clk_ext_xtal_mux.rate;
1308
1309         if (epll_rate != 24000000) {
1310                 pr_err("Invalid Clock : recommended clock is 24MHz.\n");
1311                 return -EINVAL;
1312         }
1313
1314         epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
1315         epll_con &= ~(0x1 << 27 | \
1316                         PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |   \
1317                         PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1318                         PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1319
1320         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1321                 if (epll_div[i][0] == rate) {
1322                         epll_con_k = epll_div[i][5] << 0;
1323                         epll_con |= epll_div[i][1] << 27;
1324                         epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
1325                         epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
1326                         epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
1327                         break;
1328                 }
1329         }
1330
1331         if (i == ARRAY_SIZE(epll_div)) {
1332                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1333                                 __func__);
1334                 return -EINVAL;
1335         }
1336
1337         epll_rate /= 1000000;
1338
1339         /* 3000 max_cycls : specification data */
1340         locktime = 3000 / epll_rate * epll_div[i][3];
1341         lockcnt = locktime * 10000 / (10000 / epll_rate);
1342
1343         __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
1344
1345         __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
1346         __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
1347
1348         do {
1349                 tmp = __raw_readl(EXYNOS5_EPLL_CON0);
1350         } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
1351
1352         clk->rate = rate;
1353
1354         return 0;
1355 }
1356
1357 static struct clk_ops exynos5_epll_ops = {
1358         .get_rate = exynos5_epll_get_rate,
1359         .set_rate = exynos5_epll_set_rate,
1360 };
1361
1362 static int xtal_rate;
1363
1364 static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
1365 {
1366         return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
1367 }
1368
1369 static struct clk_ops exynos5_fout_apll_ops = {
1370         .get_rate = exynos5_fout_apll_get_rate,
1371 };
1372
1373 #ifdef CONFIG_PM
1374 static int exynos5_clock_suspend(void)
1375 {
1376         s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1377
1378         return 0;
1379 }
1380
1381 static void exynos5_clock_resume(void)
1382 {
1383         s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1384 }
1385 #else
1386 #define exynos5_clock_suspend NULL
1387 #define exynos5_clock_resume NULL
1388 #endif
1389
1390 struct syscore_ops exynos5_clock_syscore_ops = {
1391         .suspend        = exynos5_clock_suspend,
1392         .resume         = exynos5_clock_resume,
1393 };
1394
1395 void __init_or_cpufreq exynos5_setup_clocks(void)
1396 {
1397         struct clk *xtal_clk;
1398         unsigned long apll;
1399         unsigned long bpll;
1400         unsigned long cpll;
1401         unsigned long mpll;
1402         unsigned long epll;
1403         unsigned long vpll;
1404         unsigned long vpllsrc;
1405         unsigned long xtal;
1406         unsigned long armclk;
1407         unsigned long mout_cdrex;
1408         unsigned long aclk_400;
1409         unsigned long aclk_333;
1410         unsigned long aclk_266;
1411         unsigned long aclk_200;
1412         unsigned long aclk_166;
1413         unsigned long aclk_66;
1414         unsigned int ptr;
1415
1416         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1417
1418         xtal_clk = clk_get(NULL, "xtal");
1419         BUG_ON(IS_ERR(xtal_clk));
1420
1421         xtal = clk_get_rate(xtal_clk);
1422
1423         xtal_rate = xtal;
1424
1425         clk_put(xtal_clk);
1426
1427         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1428
1429         apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
1430         bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
1431         cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
1432         mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
1433         epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
1434                         __raw_readl(EXYNOS5_EPLL_CON1));
1435
1436         vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
1437         vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
1438                         __raw_readl(EXYNOS5_VPLL_CON1));
1439
1440         clk_fout_apll.ops = &exynos5_fout_apll_ops;
1441         clk_fout_bpll.rate = bpll;
1442         clk_fout_bpll_div2.rate = bpll >> 1;
1443         clk_fout_cpll.rate = cpll;
1444         clk_fout_mpll.rate = mpll;
1445         clk_fout_mpll_div2.rate = mpll >> 1;
1446         clk_fout_epll.rate = epll;
1447         clk_fout_vpll.rate = vpll;
1448
1449         printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
1450                         "M=%ld, E=%ld V=%ld",
1451                         apll, bpll, cpll, mpll, epll, vpll);
1452
1453         armclk = clk_get_rate(&exynos5_clk_armclk);
1454         mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
1455
1456         aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
1457         aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
1458         aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
1459         aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
1460         aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
1461         aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
1462
1463         printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
1464                         "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
1465                         "ACLK166=%ld, ACLK66=%ld\n",
1466                         armclk, mout_cdrex, aclk_400,
1467                         aclk_333, aclk_266, aclk_200,
1468                         aclk_166, aclk_66);
1469
1470
1471         clk_fout_epll.ops = &exynos5_epll_ops;
1472
1473         if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
1474                 printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
1475                                 clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
1476
1477         clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
1478         clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
1479
1480         clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
1481         clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
1482
1483         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
1484                 s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
1485 }
1486
1487 void __init exynos5_register_clocks(void)
1488 {
1489         int ptr;
1490
1491         s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
1492
1493         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
1494                 s3c_register_clksrc(exynos5_sysclks[ptr], 1);
1495
1496         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
1497                 s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
1498
1499         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
1500                 s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
1501
1502         s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
1503         s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
1504
1505         s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
1506         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
1507                 s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
1508
1509         s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1510         s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1511         clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
1512
1513         register_syscore_ops(&exynos5_clock_syscore_ops);
1514         s3c_pwmclk_init();
1515 }