arch/arm/mach-exynos/exynos.c

   1 /*
   2  * SAMSUNG EXYNOS Flattened Device Tree enabled machine
   3  *
   4  * Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/io.h>
  14 #include <linux/kernel.h>
  15 #include <linux/serial_s3c.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_fdt.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_domain.h>
  22
  23 #include <asm/cacheflush.h>
  24 #include <asm/hardware/cache-l2x0.h>
  25 #include <asm/mach/arch.h>
  26 #include <asm/mach/map.h>
  27 #include <asm/memory.h>
  28
  29 #include "common.h"
  30 #include "mfc.h"
  31 #include "regs-pmu.h"
  32
  33 #define L2_AUX_VAL 0x7C470001
  34 #define L2_AUX_MASK 0xC200ffff
  35
  36 static struct map_desc exynos4_iodesc[] __initdata = {
  37         {
  38                 .virtual        = (unsigned long)S3C_VA_SYS,
  39                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
  40                 .length         = SZ_64K,
  41                 .type           = MT_DEVICE,
  42         }, {
  43                 .virtual        = (unsigned long)S3C_VA_TIMER,
  44                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
  45                 .length         = SZ_16K,
  46                 .type           = MT_DEVICE,
  47         }, {
  48                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
  49                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
  50                 .length         = SZ_4K,
  51                 .type           = MT_DEVICE,
  52         }, {
  53                 .virtual        = (unsigned long)S5P_VA_SROMC,
  54                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
  55                 .length         = SZ_4K,
  56                 .type           = MT_DEVICE,
  57         }, {
  58                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
  59                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
  60                 .length         = SZ_4K,
  61                 .type           = MT_DEVICE,
  62         }, {
  63                 .virtual        = (unsigned long)S5P_VA_PMU,
  64                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
  65                 .length         = SZ_64K,
  66                 .type           = MT_DEVICE,
  67         }, {
  68                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
  69                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
  70                 .length         = SZ_4K,
  71                 .type           = MT_DEVICE,
  72         }, {
  73                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
  74                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
  75                 .length         = SZ_64K,
  76                 .type           = MT_DEVICE,
  77         }, {
  78                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
  79                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
  80                 .length         = SZ_64K,
  81                 .type           = MT_DEVICE,
  82         }, {
  83                 .virtual        = (unsigned long)S5P_VA_CMU,
  84                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
  85                 .length         = SZ_128K,
  86                 .type           = MT_DEVICE,
  87         }, {
  88                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
  89                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
  90                 .length         = SZ_8K,
  91                 .type           = MT_DEVICE,
  92         }, {
  93                 .virtual        = (unsigned long)S5P_VA_L2CC,
  94                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
  95                 .length         = SZ_4K,
  96                 .type           = MT_DEVICE,
  97         }, {
  98                 .virtual        = (unsigned long)S5P_VA_DMC0,
  99                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 100                 .length         = SZ_64K,
 101                 .type           = MT_DEVICE,
 102         }, {
 103                 .virtual        = (unsigned long)S5P_VA_DMC1,
 104                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 105                 .length         = SZ_64K,
 106                 .type           = MT_DEVICE,
 107         }, {
 108                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 109                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 110                 .length         = SZ_4K,
 111                 .type           = MT_DEVICE,
 112         },
 113 };
 114
 115 static struct map_desc exynos5_iodesc[] __initdata = {
 116         {
 117                 .virtual        = (unsigned long)S3C_VA_SYS,
 118                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 119                 .length         = SZ_64K,
 120                 .type           = MT_DEVICE,
 121         }, {
 122                 .virtual        = (unsigned long)S3C_VA_TIMER,
 123                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 124                 .length         = SZ_16K,
 125                 .type           = MT_DEVICE,
 126         }, {
 127                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 128                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 129                 .length         = SZ_4K,
 130                 .type           = MT_DEVICE,
 131         }, {
 132                 .virtual        = (unsigned long)S5P_VA_SROMC,
 133                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 134                 .length         = SZ_4K,
 135                 .type           = MT_DEVICE,
 136         }, {
 137                 .virtual        = (unsigned long)S5P_VA_CMU,
 138                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 139                 .length         = 144 * SZ_1K,
 140                 .type           = MT_DEVICE,
 141         }, {
 142                 .virtual        = (unsigned long)S5P_VA_PMU,
 143                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 144                 .length         = SZ_64K,
 145                 .type           = MT_DEVICE,
 146         },
 147 };
 148
 149 void exynos_restart(enum reboot_mode mode, const char *cmd)
 150 {
 151         struct device_node *np;
 152         u32 val = 0x1;
 153         void __iomem *addr = EXYNOS_SWRESET;
 154
 155         if (of_machine_is_compatible("samsung,exynos5440")) {
 156                 u32 status;
 157                 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
 158
 159                 addr = of_iomap(np, 0) + 0xbc;
 160                 status = __raw_readl(addr);
 161
 162                 addr = of_iomap(np, 0) + 0xcc;
 163                 val = __raw_readl(addr);
 164
 165                 val = (val & 0xffff0000) | (status & 0xffff);
 166         }
 167
 168         __raw_writel(val, addr);
 169 }
 170
 171 static struct platform_device exynos_cpuidle = {
 172         .name              = "exynos_cpuidle",
 173         .dev.platform_data = exynos_enter_aftr,
 174         .id                = -1,
 175 };
 176
 177 void __init exynos_cpuidle_init(void)
 178 {
 179         if (soc_is_exynos5440())
 180                 return;
 181
 182         platform_device_register(&exynos_cpuidle);
 183 }
 184
 185 void __init exynos_cpufreq_init(void)
 186 {
 187         platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
 188 }
 189
 190 void __init exynos_init_late(void)
 191 {
 192         if (of_machine_is_compatible("samsung,exynos5440"))
 193                 /* to be supported later */
 194                 return;
 195
 196         pm_genpd_poweroff_unused();
 197         exynos_pm_init();
 198 }
 199
 200 static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
 201                                         int depth, void *data)
 202 {
 203         struct map_desc iodesc;
 204         __be32 *reg;
 205         int len;
 206
 207         if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
 208                 !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
 209                 return 0;
 210
 211         reg = of_get_flat_dt_prop(node, "reg", &len);
 212         if (reg == NULL || len != (sizeof(unsigned long) * 2))
 213                 return 0;
 214
 215         iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
 216         iodesc.length = be32_to_cpu(reg[1]) - 1;
 217         iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
 218         iodesc.type = MT_DEVICE;
 219         iotable_init(&iodesc, 1);
 220         return 1;
 221 }
 222
 223 /*
 224  * exynos_map_io
 225  *
 226  * register the standard cpu IO areas
 227  */
 228 static void __init exynos_map_io(void)
 229 {
 230         if (soc_is_exynos4())
 231                 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 232
 233         if (soc_is_exynos5())
 234                 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 235 }
 236
 237 void __init exynos_init_io(void)
 238 {
 239         debug_ll_io_init();
 240
 241         of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
 242
 243         /* detect cpu id and rev. */
 244         s5p_init_cpu(S5P_VA_CHIPID);
 245
 246         exynos_map_io();
 247 }
 248
 249 static int __init exynos4_l2x0_cache_init(void)
 250 {
 251         int ret;
 252
 253         if (!soc_is_exynos4())
 254                 return 0;
 255
 256         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 257         if (ret)
 258                 return ret;
 259
 260         if (IS_ENABLED(CONFIG_S5P_SLEEP)) {
 261                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 262                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 263         }
 264         return 0;
 265 }
 266 early_initcall(exynos4_l2x0_cache_init);
 267
 268 static void __init exynos_dt_machine_init(void)
 269 {
 270         struct device_node *i2c_np;
 271         const char *i2c_compat = "samsung,s3c2440-i2c";
 272         unsigned int tmp;
 273         int id;
 274
 275         /*
 276          * Exynos5's legacy i2c controller and new high speed i2c
 277          * controller have muxed interrupt sources. By default the
 278          * interrupts for 4-channel HS-I2C controller are enabled.
 279          * If node for first four channels of legacy i2c controller
 280          * are available then re-configure the interrupts via the
 281          * system register.
 282          */
 283         if (soc_is_exynos5()) {
 284                 for_each_compatible_node(i2c_np, NULL, i2c_compat) {
 285                         if (of_device_is_available(i2c_np)) {
 286                                 id = of_alias_get_id(i2c_np, "i2c");
 287                                 if (id < 4) {
 288                                         tmp = readl(EXYNOS5_SYS_I2C_CFG);
 289                                         writel(tmp & ~(0x1 << id),
 290                                                         EXYNOS5_SYS_I2C_CFG);
 291                                 }
 292                         }
 293                 }
 294         }
 295
 296         exynos_cpuidle_init();
 297         exynos_cpufreq_init();
 298
 299         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 300 }
 301
 302 static char const *exynos_dt_compat[] __initconst = {
 303         "samsung,exynos3",
 304         "samsung,exynos3250",
 305         "samsung,exynos4",
 306         "samsung,exynos4210",
 307         "samsung,exynos4212",
 308         "samsung,exynos4412",
 309         "samsung,exynos5",
 310         "samsung,exynos5250",
 311         "samsung,exynos5260",
 312         "samsung,exynos5420",
 313         "samsung,exynos5440",
 314         NULL
 315 };
 316
 317 static void __init exynos_reserve(void)
 318 {
 319 #ifdef CONFIG_S5P_DEV_MFC
 320         int i;
 321         char *mfc_mem[] = {
 322                 "samsung,mfc-v5",
 323                 "samsung,mfc-v6",
 324                 "samsung,mfc-v7",
 325         };
 326
 327         for (i = 0; i < ARRAY_SIZE(mfc_mem); i++)
 328                 if (of_scan_flat_dt(s5p_fdt_alloc_mfc_mem, mfc_mem[i]))
 329                         break;
 330 #endif
 331 }
 332
 333 DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
 334         /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
 335         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
 336         .smp            = smp_ops(exynos_smp_ops),
 337         .map_io         = exynos_init_io,
 338         .init_early     = exynos_firmware_init,
 339         .init_machine   = exynos_dt_machine_init,
 340         .init_late      = exynos_init_late,
 341         .dt_compat      = exynos_dt_compat,
 342         .restart        = exynos_restart,
 343         .reserve        = exynos_reserve,
 344 MACHINE_END