1 /* linux/arch/arm/mach-exynos/include/mach/map.h
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * EXYNOS4 - Memory map definitions
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __ASM_ARCH_MAP_H
14 #define __ASM_ARCH_MAP_H __FILE__
16 #include <plat/map-base.h>
19 * EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
20 * So need to define it, and here is to avoid redefinition warning.
22 #define S3C_UART_OFFSET (0x10000)
24 #include <plat/map-s5p.h>
26 #define EXYNOS4_PA_SYSRAM0 0x02025000
27 #define EXYNOS4_PA_SYSRAM1 0x02020000
29 #define EXYNOS4_PA_FIMC0 0x11800000
30 #define EXYNOS4_PA_FIMC1 0x11810000
31 #define EXYNOS4_PA_FIMC2 0x11820000
32 #define EXYNOS4_PA_FIMC3 0x11830000
34 #define EXYNOS4_PA_JPEG 0x11840000
36 #define EXYNOS4_PA_G2D 0x12800000
38 #define EXYNOS4_PA_I2S0 0x03830000
39 #define EXYNOS4_PA_I2S1 0xE3100000
40 #define EXYNOS4_PA_I2S2 0xE2A00000
42 #define EXYNOS4_PA_PCM0 0x03840000
43 #define EXYNOS4_PA_PCM1 0x13980000
44 #define EXYNOS4_PA_PCM2 0x13990000
46 #define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
48 #define EXYNOS4_PA_ONENAND 0x0C000000
49 #define EXYNOS4_PA_ONENAND_DMA 0x0C600000
51 #define EXYNOS4_PA_CHIPID 0x10000000
53 #define EXYNOS4_PA_SYSCON 0x10010000
54 #define EXYNOS4_PA_PMU 0x10020000
55 #define EXYNOS4_PA_CMU 0x10030000
57 #define EXYNOS4_PA_SYSTIMER 0x10050000
58 #define EXYNOS4_PA_WATCHDOG 0x10060000
59 #define EXYNOS4_PA_RTC 0x10070000
61 #define EXYNOS4_PA_KEYPAD 0x100A0000
63 #define EXYNOS4_PA_DMC0 0x10400000
64 #define EXYNOS4_PA_DMC1 0x10410000
66 #define EXYNOS4_PA_COMBINER 0x10440000
68 #define EXYNOS4_PA_GIC_CPU 0x10480000
69 #define EXYNOS4_PA_GIC_DIST 0x10490000
71 #define EXYNOS4_PA_COREPERI 0x10500000
72 #define EXYNOS4_PA_TWD 0x10500600
73 #define EXYNOS4_PA_L2CC 0x10502000
75 #define EXYNOS4_PA_MDMA 0x10810000
76 #define EXYNOS4_PA_PDMA0 0x12680000
77 #define EXYNOS4_PA_PDMA1 0x12690000
79 #define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
80 #define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
81 #define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
82 #define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
83 #define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000
84 #define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000
85 #define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
86 #define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
87 #define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
88 #define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
89 #define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
90 #define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
91 #define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000
92 #define EXYNOS4_PA_SYSMMU_TV 0x12E20000
93 #define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
94 #define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
95 #define EXYNOS4_PA_SPI0 0x13920000
96 #define EXYNOS4_PA_SPI1 0x13930000
97 #define EXYNOS4_PA_SPI2 0x13940000
100 #define EXYNOS4_PA_GPIO1 0x11400000
101 #define EXYNOS4_PA_GPIO2 0x11000000
102 #define EXYNOS4_PA_GPIO3 0x03860000
104 #define EXYNOS4_PA_MIPI_CSIS0 0x11880000
105 #define EXYNOS4_PA_MIPI_CSIS1 0x11890000
107 #define EXYNOS4_PA_FIMD0 0x11C00000
109 #define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
110 #define EXYNOS4_PA_DWMCI 0x12550000
112 #define EXYNOS4_PA_SATA 0x12560000
113 #define EXYNOS4_PA_SATAPHY 0x125D0000
114 #define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
116 #define EXYNOS4_PA_SROMC 0x12570000
118 #define EXYNOS4_PA_EHCI 0x12580000
119 #define EXYNOS4_PA_OHCI 0x12590000
120 #define EXYNOS4_PA_HSPHY 0x125B0000
121 #define EXYNOS4_PA_MFC 0x13400000
123 #define EXYNOS4_PA_UART 0x13800000
125 #define EXYNOS4_PA_VP 0x12C00000
126 #define EXYNOS4_PA_MIXER 0x12C10000
127 #define EXYNOS4_PA_SDO 0x12C20000
128 #define EXYNOS4_PA_HDMI 0x12D00000
129 #define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
131 #define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
133 #define EXYNOS4_PA_ADC 0x13910000
134 #define EXYNOS4_PA_ADC1 0x13911000
136 #define EXYNOS4_PA_AC97 0x139A0000
138 #define EXYNOS4_PA_SPDIF 0x139B0000
140 #define EXYNOS4_PA_TIMER 0x139D0000
142 #define EXYNOS4_PA_SDRAM 0x40000000
144 /* Compatibiltiy Defines */
146 #define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0)
147 #define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1)
148 #define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2)
149 #define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3)
150 #define S3C_PA_IIC EXYNOS4_PA_IIC(0)
151 #define S3C_PA_IIC1 EXYNOS4_PA_IIC(1)
152 #define S3C_PA_IIC2 EXYNOS4_PA_IIC(2)
153 #define S3C_PA_IIC3 EXYNOS4_PA_IIC(3)
154 #define S3C_PA_IIC4 EXYNOS4_PA_IIC(4)
155 #define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
156 #define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
157 #define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
158 #define S3C_PA_RTC EXYNOS4_PA_RTC
159 #define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
160 #define S3C_PA_UART EXYNOS4_PA_UART
161 #define S3C_PA_SPI0 EXYNOS4_PA_SPI0
162 #define S3C_PA_SPI1 EXYNOS4_PA_SPI1
163 #define S3C_PA_SPI2 EXYNOS4_PA_SPI2
165 #define S5P_PA_EHCI EXYNOS4_PA_EHCI
166 #define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
167 #define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
168 #define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2
169 #define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
170 #define S5P_PA_JPEG EXYNOS4_PA_JPEG
171 #define S5P_PA_G2D EXYNOS4_PA_G2D
172 #define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
173 #define S5P_PA_HDMI EXYNOS4_PA_HDMI
174 #define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY
175 #define S5P_PA_MFC EXYNOS4_PA_MFC
176 #define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
177 #define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
178 #define S5P_PA_MIXER EXYNOS4_PA_MIXER
179 #define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
180 #define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
181 #define S5P_PA_SDO EXYNOS4_PA_SDO
182 #define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
183 #define S5P_PA_VP EXYNOS4_PA_VP
185 #define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
186 #define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
187 #define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
189 /* Compatibility UART */
191 #define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
193 #define S5P_PA_UART(x) (EXYNOS4_PA_UART + ((x) * S3C_UART_OFFSET))
194 #define S5P_PA_UART0 S5P_PA_UART(0)
195 #define S5P_PA_UART1 S5P_PA_UART(1)
196 #define S5P_PA_UART2 S5P_PA_UART(2)
197 #define S5P_PA_UART3 S5P_PA_UART(3)
198 #define S5P_PA_UART4 S5P_PA_UART(4)
200 #define S5P_SZ_UART SZ_256
202 #endif /* __ASM_ARCH_MAP_H */