2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * arch/arm/mach-exynos/mcpm-exynos.c
7 * Based on arch/arm/mach-vexpress/dcscb.c
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/arm-cci.h>
15 #include <linux/delay.h>
17 #include <linux/of_address.h>
18 #include <linux/syscore_ops.h>
20 #include <asm/cputype.h>
27 #define EXYNOS5420_CPUS_PER_CLUSTER 4
28 #define EXYNOS5420_NR_CLUSTERS 2
30 #define EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN BIT(9)
31 #define EXYNOS5420_USE_ARM_CORE_DOWN_STATE BIT(29)
32 #define EXYNOS5420_USE_L2_COMMON_UP_STATE BIT(30)
34 static void __iomem *ns_sram_base_addr;
37 * The common v7_exit_coherency_flush API could not be used because of the
38 * Erratum 799270 workaround. This macro is the same as the common one (in
39 * arch/arm/include/asm/cacheflush.h) except for the erratum handling.
41 #define exynos_v7_exit_coherency_flush(level) \
43 "stmfd sp!, {fp, ip}\n\t"\
44 "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR\n\t" \
45 "bic r0, r0, #"__stringify(CR_C)"\n\t" \
46 "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR\n\t" \
48 "bl v7_flush_dcache_"__stringify(level)"\n\t" \
49 "mrc p15, 0, r0, c1, c0, 1 @ get ACTLR\n\t" \
50 "bic r0, r0, #(1 << 6) @ disable local coherency\n\t" \
51 /* Dummy Load of a device register to avoid Erratum 799270 */ \
53 "and r4, r4, #0\n\t" \
54 "orr r0, r0, r4\n\t" \
55 "mcr p15, 0, r0, c1, c0, 1 @ set ACTLR\n\t" \
58 "ldmfd sp!, {fp, ip}" \
60 : "Ir" (pmu_base_addr + S5P_INFORM0) \
61 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
62 "r9", "r10", "lr", "memory")
65 * We can't use regular spinlocks. In the switcher case, it is possible
66 * for an outbound CPU to call power_down() after its inbound counterpart
67 * is already live using the same logical CPU number which trips lockdep
70 static arch_spinlock_t exynos_mcpm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
72 cpu_use_count[EXYNOS5420_CPUS_PER_CLUSTER][EXYNOS5420_NR_CLUSTERS];
74 #define exynos_cluster_usecnt(cluster) \
75 (cpu_use_count[0][cluster] + \
76 cpu_use_count[1][cluster] + \
77 cpu_use_count[2][cluster] + \
78 cpu_use_count[3][cluster])
80 #define exynos_cluster_unused(cluster) !exynos_cluster_usecnt(cluster)
82 static int exynos_power_up(unsigned int cpu, unsigned int cluster)
84 unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
86 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
87 if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
88 cluster >= EXYNOS5420_NR_CLUSTERS)
92 * Since this is called with IRQs enabled, and no arch_spin_lock_irq
93 * variant exists, we need to disable IRQs manually here.
96 arch_spin_lock(&exynos_mcpm_lock);
98 cpu_use_count[cpu][cluster]++;
99 if (cpu_use_count[cpu][cluster] == 1) {
100 bool was_cluster_down =
101 (exynos_cluster_usecnt(cluster) == 1);
104 * Turn on the cluster (L2/COMMON) and then power on the
107 if (was_cluster_down)
108 exynos_cluster_power_up(cluster);
110 exynos_cpu_power_up(cpunr);
111 } else if (cpu_use_count[cpu][cluster] != 2) {
113 * The only possible values are:
116 * 2 = CPU requested to be up before it had a chance
117 * to actually make itself down.
118 * Any other value is a bug.
123 arch_spin_unlock(&exynos_mcpm_lock);
130 * NOTE: This function requires the stack data to be visible through power down
131 * and can only be executed on processors like A15 and A7 that hit the cache
132 * with the C bit clear in the SCTLR register.
134 static void exynos_power_down(void)
136 unsigned int mpidr, cpu, cluster;
137 bool last_man = false, skip_wfi = false;
140 mpidr = read_cpuid_mpidr();
141 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
142 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
143 cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
145 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
146 BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
147 cluster >= EXYNOS5420_NR_CLUSTERS);
149 __mcpm_cpu_going_down(cpu, cluster);
151 arch_spin_lock(&exynos_mcpm_lock);
152 BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
153 cpu_use_count[cpu][cluster]--;
154 if (cpu_use_count[cpu][cluster] == 0) {
155 exynos_cpu_power_down(cpunr);
157 if (exynos_cluster_unused(cluster)) {
158 exynos_cluster_power_down(cluster);
161 } else if (cpu_use_count[cpu][cluster] == 1) {
163 * A power_up request went ahead of us.
164 * Even if we do not want to shut this CPU down,
165 * the caller expects a certain state as if the WFI
166 * was aborted. So let's continue with cache cleaning.
173 if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
174 arch_spin_unlock(&exynos_mcpm_lock);
176 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
178 * On the Cortex-A15 we need to disable
179 * L2 prefetching before flushing the cache.
182 "mcr p15, 1, %0, c15, c0, 3\n\t"
188 /* Flush all cache levels for this cluster. */
189 exynos_v7_exit_coherency_flush(all);
192 * Disable cluster-level coherency by masking
193 * incoming snoops and DVM messages:
195 cci_disable_port_by_cpu(mpidr);
197 __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
199 arch_spin_unlock(&exynos_mcpm_lock);
201 /* Disable and flush the local CPU cache. */
202 exynos_v7_exit_coherency_flush(louis);
205 __mcpm_cpu_down(cpu, cluster);
207 /* Now we are prepared for power-down, do it: */
211 /* Not dead at this point? Let our caller cope. */
214 static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
216 unsigned int tries = 100;
217 unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
219 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
220 BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
221 cluster >= EXYNOS5420_NR_CLUSTERS);
223 /* Wait for the core state to be OFF */
225 if (ACCESS_ONCE(cpu_use_count[cpu][cluster]) == 0) {
226 if ((exynos_cpu_power_state(cpunr) == 0))
227 return 0; /* success: the CPU is halted */
230 /* Otherwise, wait and retry: */
234 return -ETIMEDOUT; /* timeout */
237 static void exynos_powered_up(void)
239 unsigned int mpidr, cpu, cluster;
241 mpidr = read_cpuid_mpidr();
242 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
243 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
245 arch_spin_lock(&exynos_mcpm_lock);
246 if (cpu_use_count[cpu][cluster] == 0)
247 cpu_use_count[cpu][cluster] = 1;
248 arch_spin_unlock(&exynos_mcpm_lock);
251 static void exynos_suspend(u64 residency)
253 unsigned int mpidr, cpunr;
258 * Execution reaches here only if cpu did not power down.
259 * Hence roll back the changes done in exynos_power_down function.
261 * CAUTION: "This function requires the stack data to be visible through
262 * power down and can only be executed on processors like A15 and A7
263 * that hit the cache with the C bit clear in the SCTLR register."
265 mpidr = read_cpuid_mpidr();
266 cpunr = exynos_pmu_cpunr(mpidr);
268 exynos_cpu_power_up(cpunr);
271 static const struct mcpm_platform_ops exynos_power_ops = {
272 .power_up = exynos_power_up,
273 .power_down = exynos_power_down,
274 .wait_for_powerdown = exynos_wait_for_powerdown,
275 .suspend = exynos_suspend,
276 .powered_up = exynos_powered_up,
279 static void __init exynos_mcpm_usage_count_init(void)
281 unsigned int mpidr, cpu, cluster;
283 mpidr = read_cpuid_mpidr();
284 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
285 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
287 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
288 BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
289 cluster >= EXYNOS5420_NR_CLUSTERS);
291 cpu_use_count[cpu][cluster] = 1;
295 * Enable cluster-level coherency, in preparation for turning on the MMU.
297 static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
302 "b cci_enable_port_for_self");
305 static void __init exynos_cache_off(void)
307 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
308 /* disable L2 prefetching on the Cortex-A15 */
310 "mcr p15, 1, %0, c15, c0, 3\n\t"
315 exynos_v7_exit_coherency_flush(all);
318 static const struct of_device_id exynos_dt_mcpm_match[] = {
319 { .compatible = "samsung,exynos5420" },
320 { .compatible = "samsung,exynos5800" },
324 static void exynos_mcpm_setup_entry_point(void)
327 * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
328 * as part of secondary_cpu_start(). Let's redirect it to the
329 * mcpm_entry_point(). This is done during both secondary boot-up as
330 * well as system resume.
332 __raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */
333 __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */
334 __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
337 static struct syscore_ops exynos_mcpm_syscore_ops = {
338 .resume = exynos_mcpm_setup_entry_point,
341 static int __init exynos_mcpm_init(void)
343 struct device_node *node;
344 unsigned int value, i;
347 node = of_find_matching_node(NULL, exynos_dt_mcpm_match);
355 node = of_find_compatible_node(NULL, NULL,
356 "samsung,exynos4210-sysram-ns");
360 ns_sram_base_addr = of_iomap(node, 0);
362 if (!ns_sram_base_addr) {
363 pr_err("failed to map non-secure iRAM base address\n");
368 * To increase the stability of KFC reset we need to program
369 * the PMU SPARE3 register
371 pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
373 exynos_mcpm_usage_count_init();
375 ret = mcpm_platform_register(&exynos_power_ops);
377 ret = mcpm_sync_init(exynos_pm_power_up_setup);
379 ret = mcpm_loopback(exynos_cache_off); /* turn on the CCI */
381 iounmap(ns_sram_base_addr);
387 pr_info("Exynos MCPM support installed\n");
390 * On Exynos5420/5800 for the A15 and A7 clusters:
392 * EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN ensures that all the cores
393 * in a cluster are turned off before turning off the cluster L2.
395 * EXYNOS5420_USE_ARM_CORE_DOWN_STATE ensures that a cores is powered
396 * off before waking it up.
398 * EXYNOS5420_USE_L2_COMMON_UP_STATE ensures that cluster L2 will be
399 * turned on before the first man is powered up.
401 for (i = 0; i < EXYNOS5420_NR_CLUSTERS; i++) {
402 value = pmu_raw_readl(EXYNOS_COMMON_OPTION(i));
403 value |= EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN |
404 EXYNOS5420_USE_ARM_CORE_DOWN_STATE |
405 EXYNOS5420_USE_L2_COMMON_UP_STATE;
406 pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i));
409 exynos_mcpm_setup_entry_point();
411 register_syscore_ops(&exynos_mcpm_syscore_ops);
416 early_initcall(exynos_mcpm_init);