2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
7 * Copyright (C) 2002 ARM Ltd.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/errno.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/jiffies.h>
20 #include <linux/smp.h>
22 #include <linux/of_address.h>
24 #include <asm/cacheflush.h>
25 #include <asm/smp_plat.h>
26 #include <asm/smp_scu.h>
27 #include <asm/firmware.h>
32 extern void exynos4_secondary_startup(void);
35 * exynos_core_power_down : power down the specified cpu
36 * @cpu : the cpu to power down
38 * Power down the specified cpu. The sequence must be finished by a
39 * call to cpu_do_idle()
42 void exynos_cpu_power_down(int cpu)
44 __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
48 * exynos_cpu_power_up : power up the specified cpu
49 * @cpu : the cpu to power up
51 * Power up the specified cpu
53 void exynos_cpu_power_up(int cpu)
55 __raw_writel(S5P_CORE_LOCAL_PWR_EN,
56 EXYNOS_ARM_CORE_CONFIGURATION(cpu));
60 * exynos_cpu_power_state : returns the power state of the cpu
61 * @cpu : the cpu to retrieve the power state from
64 int exynos_cpu_power_state(int cpu)
66 return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
67 S5P_CORE_LOCAL_PWR_EN);
71 * exynos_cluster_power_down : power down the specified cluster
72 * @cluster : the cluster to power down
74 void exynos_cluster_power_down(int cluster)
76 __raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
80 * exynos_cluster_power_up : power up the specified cluster
81 * @cluster : the cluster to power up
83 void exynos_cluster_power_up(int cluster)
85 __raw_writel(S5P_CORE_LOCAL_PWR_EN,
86 EXYNOS_COMMON_CONFIGURATION(cluster));
90 * exynos_cluster_power_state : returns the power state of the cluster
91 * @cluster : the cluster to retrieve the power state from
94 int exynos_cluster_power_state(int cluster)
96 return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
97 S5P_CORE_LOCAL_PWR_EN);
100 static inline void __iomem *cpu_boot_reg_base(void)
102 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
104 return sysram_base_addr;
107 static inline void __iomem *cpu_boot_reg(int cpu)
109 void __iomem *boot_reg;
111 boot_reg = cpu_boot_reg_base();
113 return ERR_PTR(-ENODEV);
114 if (soc_is_exynos4412())
116 else if (soc_is_exynos5420() || soc_is_exynos5800())
122 * Write pen_release in a way that is guaranteed to be visible to all
123 * observers, irrespective of whether they're taking part in coherency
124 * or not. This is necessary for the hotplug code to work reliably.
126 static void write_pen_release(int val)
130 sync_cache_w(&pen_release);
133 static void __iomem *scu_base_addr(void)
135 return (void __iomem *)(S5P_VA_SCU);
138 static DEFINE_SPINLOCK(boot_lock);
140 static void exynos_secondary_init(unsigned int cpu)
143 * let the primary processor know we're out of the
144 * pen, then head off into the C entry point
146 write_pen_release(-1);
149 * Synchronise with the boot thread.
151 spin_lock(&boot_lock);
152 spin_unlock(&boot_lock);
155 static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
157 unsigned long timeout;
158 unsigned long phys_cpu = cpu_logical_map(cpu);
162 * Set synchronisation state between this boot processor
163 * and the secondary one
165 spin_lock(&boot_lock);
168 * The secondary processor is waiting to be released from
169 * the holding pen - release it, then wait for it to flag
170 * that it has been released by resetting pen_release.
172 * Note that "pen_release" is the hardware CPU ID, whereas
173 * "cpu" is Linux's internal ID.
175 write_pen_release(phys_cpu);
177 if (!exynos_cpu_power_state(cpu)) {
178 exynos_cpu_power_up(cpu);
181 /* wait max 10 ms until cpu1 is on */
182 while (exynos_cpu_power_state(cpu) != S5P_CORE_LOCAL_PWR_EN) {
190 printk(KERN_ERR "cpu1 power enable failed");
191 spin_unlock(&boot_lock);
196 * Send the secondary CPU a soft interrupt, thereby causing
197 * the boot monitor to read the system wide flags register,
198 * and branch to the address found there.
201 timeout = jiffies + (1 * HZ);
202 while (time_before(jiffies, timeout)) {
203 unsigned long boot_addr;
207 boot_addr = virt_to_phys(exynos4_secondary_startup);
210 * Try to set boot address using firmware first
211 * and fall back to boot register if it fails.
213 ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);
214 if (ret && ret != -ENOSYS)
216 if (ret == -ENOSYS) {
217 void __iomem *boot_reg = cpu_boot_reg(phys_cpu);
219 if (IS_ERR(boot_reg)) {
220 ret = PTR_ERR(boot_reg);
223 __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
226 call_firmware_op(cpu_boot, phys_cpu);
228 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
230 if (pen_release == -1)
237 * now the secondary core is starting up let it run its
238 * calibrations, then wait for it to finish
241 spin_unlock(&boot_lock);
243 return pen_release != -1 ? ret : 0;
247 * Initialise the CPU possible map early - this describes the CPUs
248 * which may be present or become present in the system.
251 static void __init exynos_smp_init_cpus(void)
253 void __iomem *scu_base = scu_base_addr();
254 unsigned int i, ncores;
256 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
257 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
260 * CPU Nodes are passed thru DT and set_cpu_possible
261 * is set by "arm_dt_init_cpu_maps".
266 if (ncores > nr_cpu_ids) {
267 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
272 for (i = 0; i < ncores; i++)
273 set_cpu_possible(i, true);
276 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
280 exynos_sysram_init();
282 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
283 scu_enable(scu_base_addr());
286 * Write the address of secondary startup into the
287 * system-wide flags register. The boot monitor waits
288 * until it receives a soft interrupt, and then the
289 * secondary CPU branches to this address.
291 * Try using firmware operation first and fall back to
292 * boot register if it fails.
294 for (i = 1; i < max_cpus; ++i) {
295 unsigned long phys_cpu;
296 unsigned long boot_addr;
299 phys_cpu = cpu_logical_map(i);
300 boot_addr = virt_to_phys(exynos4_secondary_startup);
302 ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);
303 if (ret && ret != -ENOSYS)
305 if (ret == -ENOSYS) {
306 void __iomem *boot_reg = cpu_boot_reg(phys_cpu);
308 if (IS_ERR(boot_reg))
310 __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
315 struct smp_operations exynos_smp_ops __initdata = {
316 .smp_init_cpus = exynos_smp_init_cpus,
317 .smp_prepare_cpus = exynos_smp_prepare_cpus,
318 .smp_secondary_init = exynos_secondary_init,
319 .smp_boot_secondary = exynos_boot_secondary,
320 #ifdef CONFIG_HOTPLUG_CPU
321 .cpu_die = exynos_cpu_die,