arch/arm/mach-exynos/pm.c

   1 /*
   2  * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS - Power Management support
   6  *
   7  * Based on arch/arm/mach-s3c2410/pm.c
   8  * Copyright (c) 2006 Simtec Electronics
   9  *      Ben Dooks <ben@simtec.co.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14 */
  15
  16 #include <linux/init.h>
  17 #include <linux/suspend.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/io.h>
  20 #include <linux/irqchip/arm-gic.h>
  21 #include <linux/err.h>
  22 #include <linux/clk.h>
  23
  24 #include <asm/cacheflush.h>
  25 #include <asm/hardware/cache-l2x0.h>
  26 #include <asm/smp_scu.h>
  27 #include <asm/suspend.h>
  28
  29 #include <plat/pm-common.h>
  30 #include <plat/pll.h>
  31 #include <plat/regs-srom.h>
  32
  33 #include <mach/map.h>
  34
  35 #include "common.h"
  36 #include "regs-pmu.h"
  37
  38 /**
  39  * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
  40  * @hwirq: Hardware IRQ signal of the GIC
  41  * @mask: Mask in PMU wake-up mask register
  42  */
  43 struct exynos_wkup_irq {
  44         unsigned int hwirq;
  45         u32 mask;
  46 };
  47
  48 static struct sleep_save exynos5_sys_save[] = {
  49         SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
  50 };
  51
  52 static struct sleep_save exynos_core_save[] = {
  53         /* SROM side */
  54         SAVE_ITEM(S5P_SROM_BW),
  55         SAVE_ITEM(S5P_SROM_BC0),
  56         SAVE_ITEM(S5P_SROM_BC1),
  57         SAVE_ITEM(S5P_SROM_BC2),
  58         SAVE_ITEM(S5P_SROM_BC3),
  59 };
  60
  61 /*
  62  * GIC wake-up support
  63  */
  64
  65 static u32 exynos_irqwake_intmask = 0xffffffff;
  66
  67 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
  68         { 76, BIT(1) }, /* RTC alarm */
  69         { 77, BIT(2) }, /* RTC tick */
  70         { /* sentinel */ },
  71 };
  72
  73 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
  74         { 75, BIT(1) }, /* RTC alarm */
  75         { 76, BIT(2) }, /* RTC tick */
  76         { /* sentinel */ },
  77 };
  78
  79 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
  80 {
  81         const struct exynos_wkup_irq *wkup_irq;
  82
  83         if (soc_is_exynos5250())
  84                 wkup_irq = exynos5250_wkup_irq;
  85         else
  86                 wkup_irq = exynos4_wkup_irq;
  87
  88         while (wkup_irq->mask) {
  89                 if (wkup_irq->hwirq == data->hwirq) {
  90                         if (!state)
  91                                 exynos_irqwake_intmask |= wkup_irq->mask;
  92                         else
  93                                 exynos_irqwake_intmask &= ~wkup_irq->mask;
  94                         return 0;
  95                 }
  96                 ++wkup_irq;
  97         }
  98
  99         return -ENOENT;
 100 }
 101
 102 /* For Cortex-A9 Diagnostic and Power control register */
 103 static unsigned int save_arm_register[2];
 104
 105 static int exynos_cpu_suspend(unsigned long arg)
 106 {
 107 #ifdef CONFIG_CACHE_L2X0
 108         outer_flush_all();
 109 #endif
 110
 111         if (soc_is_exynos5250())
 112                 flush_cache_all();
 113
 114         /* issue the standby signal into the pm unit. */
 115         cpu_do_idle();
 116
 117         pr_info("Failed to suspend the system\n");
 118         return 1; /* Aborting suspend */
 119 }
 120
 121 static void exynos_pm_prepare(void)
 122 {
 123         unsigned int tmp;
 124
 125         /* Set wake-up mask registers */
 126         __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
 127         __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
 128
 129         s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 130
 131         if (soc_is_exynos5250()) {
 132                 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
 133                 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
 134                 tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
 135                 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
 136                 __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
 137         }
 138
 139         /* Set value of power down register for sleep mode */
 140
 141         exynos_sys_powerdown_conf(SYS_SLEEP);
 142         __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
 143
 144         /* ensure at least INFORM0 has the resume address */
 145
 146         __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
 147 }
 148
 149 static int exynos_pm_suspend(void)
 150 {
 151         unsigned long tmp;
 152
 153         /* Setting Central Sequence Register for power down mode */
 154
 155         tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 156         tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
 157         __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 158
 159         /* Setting SEQ_OPTION register */
 160
 161         tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
 162         __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
 163
 164         if (!soc_is_exynos5250()) {
 165                 /* Save Power control register */
 166                 asm ("mrc p15, 0, %0, c15, c0, 0"
 167                      : "=r" (tmp) : : "cc");
 168                 save_arm_register[0] = tmp;
 169
 170                 /* Save Diagnostic register */
 171                 asm ("mrc p15, 0, %0, c15, c0, 1"
 172                      : "=r" (tmp) : : "cc");
 173                 save_arm_register[1] = tmp;
 174         }
 175
 176         return 0;
 177 }
 178
 179 static void exynos_pm_resume(void)
 180 {
 181         unsigned long tmp;
 182
 183         /*
 184          * If PMU failed while entering sleep mode, WFI will be
 185          * ignored by PMU and then exiting cpu_do_idle().
 186          * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
 187          * in this situation.
 188          */
 189         tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 190         if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
 191                 tmp |= S5P_CENTRAL_LOWPWR_CFG;
 192                 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 193                 /* clear the wakeup state register */
 194                 __raw_writel(0x0, S5P_WAKEUP_STAT);
 195                 /* No need to perform below restore code */
 196                 goto early_wakeup;
 197         }
 198         if (!soc_is_exynos5250()) {
 199                 /* Restore Power control register */
 200                 tmp = save_arm_register[0];
 201                 asm volatile ("mcr p15, 0, %0, c15, c0, 0"
 202                               : : "r" (tmp)
 203                               : "cc");
 204
 205                 /* Restore Diagnostic register */
 206                 tmp = save_arm_register[1];
 207                 asm volatile ("mcr p15, 0, %0, c15, c0, 1"
 208                               : : "r" (tmp)
 209                               : "cc");
 210         }
 211
 212         /* For release retention */
 213
 214         __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
 215         __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
 216         __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
 217         __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
 218         __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
 219         __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
 220         __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
 221
 222         if (soc_is_exynos5250())
 223                 s3c_pm_do_restore(exynos5_sys_save,
 224                         ARRAY_SIZE(exynos5_sys_save));
 225
 226         s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 227
 228         if (IS_ENABLED(CONFIG_SMP) && !soc_is_exynos5250())
 229                 scu_enable(S5P_VA_SCU);
 230
 231 early_wakeup:
 232
 233         /* Clear SLEEP mode set in INFORM1 */
 234         __raw_writel(0x0, S5P_INFORM1);
 235
 236         return;
 237 }
 238
 239 static struct syscore_ops exynos_pm_syscore_ops = {
 240         .suspend        = exynos_pm_suspend,
 241         .resume         = exynos_pm_resume,
 242 };
 243
 244 /*
 245  * Suspend Ops
 246  */
 247
 248 static int exynos_suspend_enter(suspend_state_t state)
 249 {
 250         int ret;
 251
 252         s3c_pm_debug_init();
 253
 254         S3C_PMDBG("%s: suspending the system...\n", __func__);
 255
 256         S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
 257                         exynos_irqwake_intmask, exynos_get_eint_wake_mask());
 258
 259         if (exynos_irqwake_intmask == -1U
 260             && exynos_get_eint_wake_mask() == -1U) {
 261                 pr_err("%s: No wake-up sources!\n", __func__);
 262                 pr_err("%s: Aborting sleep\n", __func__);
 263                 return -EINVAL;
 264         }
 265
 266         s3c_pm_save_uarts();
 267         exynos_pm_prepare();
 268         flush_cache_all();
 269         s3c_pm_check_store();
 270
 271         ret = cpu_suspend(0, exynos_cpu_suspend);
 272         if (ret)
 273                 return ret;
 274
 275         s3c_pm_restore_uarts();
 276
 277         S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
 278                         __raw_readl(S5P_WAKEUP_STAT));
 279
 280         s3c_pm_check_restore();
 281
 282         S3C_PMDBG("%s: resuming the system...\n", __func__);
 283
 284         return 0;
 285 }
 286
 287 static int exynos_suspend_prepare(void)
 288 {
 289         s3c_pm_check_prepare();
 290
 291         return 0;
 292 }
 293
 294 static void exynos_suspend_finish(void)
 295 {
 296         s3c_pm_check_cleanup();
 297 }
 298
 299 static const struct platform_suspend_ops exynos_suspend_ops = {
 300         .enter          = exynos_suspend_enter,
 301         .prepare        = exynos_suspend_prepare,
 302         .finish         = exynos_suspend_finish,
 303         .valid          = suspend_valid_only_mem,
 304 };
 305
 306 void __init exynos_pm_init(void)
 307 {
 308         u32 tmp;
 309
 310         /* Platform-specific GIC callback */
 311         gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
 312
 313         /* All wakeup disable */
 314         tmp = __raw_readl(S5P_WAKEUP_MASK);
 315         tmp |= ((0xFF << 8) | (0x1F << 1));
 316         __raw_writel(tmp, S5P_WAKEUP_MASK);
 317
 318         register_syscore_ops(&exynos_pm_syscore_ops);
 319         suspend_set_ops(&exynos_suspend_ops);
 320 }