2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2012 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/delay.h>
17 #include <linux/slab.h>
18 #include <linux/jiffies.h>
19 #include <linux/err.h>
22 #define PLL_NUM_OFFSET 0x10
23 #define PLL_DENOM_OFFSET 0x20
25 #define BM_PLL_POWER (0x1 << 12)
26 #define BM_PLL_LOCK (0x1 << 31)
29 * struct clk_pllv3 - IMX PLL clock version 3
30 * @clk_hw: clock source
31 * @base: base address of PLL registers
32 * @powerup_set: set POWER bit to power up the PLL
33 * @div_mask: mask of divider bits
35 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
36 * is actually a multiplier, and always sits at bit 0.
45 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
47 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
49 unsigned long timeout = jiffies + msecs_to_jiffies(10);
50 u32 val = readl_relaxed(pll->base) & BM_PLL_POWER;
52 /* No need to wait for lock when pll is not powered up */
53 if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
56 /* Wait for PLL to lock */
58 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
60 if (time_after(jiffies, timeout))
62 usleep_range(50, 500);
65 return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;
68 static int clk_pllv3_prepare(struct clk_hw *hw)
70 struct clk_pllv3 *pll = to_clk_pllv3(hw);
74 val = readl_relaxed(pll->base);
79 writel_relaxed(val, pll->base);
81 ret = clk_pllv3_wait_lock(pll);
88 static void clk_pllv3_unprepare(struct clk_hw *hw)
90 struct clk_pllv3 *pll = to_clk_pllv3(hw);
93 val = readl_relaxed(pll->base);
98 writel_relaxed(val, pll->base);
101 static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
102 unsigned long parent_rate)
104 struct clk_pllv3 *pll = to_clk_pllv3(hw);
105 u32 div = readl_relaxed(pll->base) & pll->div_mask;
107 return (div == 1) ? parent_rate * 22 : parent_rate * 20;
110 static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
111 unsigned long *prate)
113 unsigned long parent_rate = *prate;
115 return (rate >= parent_rate * 22) ? parent_rate * 22 :
119 static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
120 unsigned long parent_rate)
122 struct clk_pllv3 *pll = to_clk_pllv3(hw);
125 if (rate == parent_rate * 22)
127 else if (rate == parent_rate * 20)
132 val = readl_relaxed(pll->base);
133 val &= ~pll->div_mask;
135 writel_relaxed(val, pll->base);
137 return clk_pllv3_wait_lock(pll);
140 static const struct clk_ops clk_pllv3_ops = {
141 .prepare = clk_pllv3_prepare,
142 .unprepare = clk_pllv3_unprepare,
143 .recalc_rate = clk_pllv3_recalc_rate,
144 .round_rate = clk_pllv3_round_rate,
145 .set_rate = clk_pllv3_set_rate,
148 static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
149 unsigned long parent_rate)
151 struct clk_pllv3 *pll = to_clk_pllv3(hw);
152 u32 div = readl_relaxed(pll->base) & pll->div_mask;
154 return parent_rate * div / 2;
157 static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
158 unsigned long *prate)
160 unsigned long parent_rate = *prate;
161 unsigned long min_rate = parent_rate * 54 / 2;
162 unsigned long max_rate = parent_rate * 108 / 2;
167 else if (rate < min_rate)
169 div = rate * 2 / parent_rate;
171 return parent_rate * div / 2;
174 static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
175 unsigned long parent_rate)
177 struct clk_pllv3 *pll = to_clk_pllv3(hw);
178 unsigned long min_rate = parent_rate * 54 / 2;
179 unsigned long max_rate = parent_rate * 108 / 2;
182 if (rate < min_rate || rate > max_rate)
185 div = rate * 2 / parent_rate;
186 val = readl_relaxed(pll->base);
187 val &= ~pll->div_mask;
189 writel_relaxed(val, pll->base);
191 return clk_pllv3_wait_lock(pll);
194 static const struct clk_ops clk_pllv3_sys_ops = {
195 .prepare = clk_pllv3_prepare,
196 .unprepare = clk_pllv3_unprepare,
197 .recalc_rate = clk_pllv3_sys_recalc_rate,
198 .round_rate = clk_pllv3_sys_round_rate,
199 .set_rate = clk_pllv3_sys_set_rate,
202 static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
203 unsigned long parent_rate)
205 struct clk_pllv3 *pll = to_clk_pllv3(hw);
206 u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
207 u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
208 u32 div = readl_relaxed(pll->base) & pll->div_mask;
210 return (parent_rate * div) + ((parent_rate / mfd) * mfn);
213 static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
214 unsigned long *prate)
216 unsigned long parent_rate = *prate;
217 unsigned long min_rate = parent_rate * 27;
218 unsigned long max_rate = parent_rate * 54;
220 u32 mfn, mfd = 1000000;
225 else if (rate < min_rate)
228 div = rate / parent_rate;
229 temp64 = (u64) (rate - div * parent_rate);
231 do_div(temp64, parent_rate);
234 return parent_rate * div + parent_rate / mfd * mfn;
237 static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
238 unsigned long parent_rate)
240 struct clk_pllv3 *pll = to_clk_pllv3(hw);
241 unsigned long min_rate = parent_rate * 27;
242 unsigned long max_rate = parent_rate * 54;
244 u32 mfn, mfd = 1000000;
247 if (rate < min_rate || rate > max_rate)
250 div = rate / parent_rate;
251 temp64 = (u64) (rate - div * parent_rate);
253 do_div(temp64, parent_rate);
256 val = readl_relaxed(pll->base);
257 val &= ~pll->div_mask;
259 writel_relaxed(val, pll->base);
260 writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
261 writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
263 return clk_pllv3_wait_lock(pll);
266 static const struct clk_ops clk_pllv3_av_ops = {
267 .prepare = clk_pllv3_prepare,
268 .unprepare = clk_pllv3_unprepare,
269 .recalc_rate = clk_pllv3_av_recalc_rate,
270 .round_rate = clk_pllv3_av_round_rate,
271 .set_rate = clk_pllv3_av_set_rate,
274 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
275 unsigned long parent_rate)
280 static const struct clk_ops clk_pllv3_enet_ops = {
281 .prepare = clk_pllv3_prepare,
282 .unprepare = clk_pllv3_unprepare,
283 .recalc_rate = clk_pllv3_enet_recalc_rate,
286 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
287 const char *parent_name, void __iomem *base,
290 struct clk_pllv3 *pll;
291 const struct clk_ops *ops;
293 struct clk_init_data init;
295 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
297 return ERR_PTR(-ENOMEM);
301 ops = &clk_pllv3_sys_ops;
304 ops = &clk_pllv3_ops;
305 pll->powerup_set = true;
308 ops = &clk_pllv3_av_ops;
311 ops = &clk_pllv3_enet_ops;
314 ops = &clk_pllv3_ops;
317 pll->div_mask = div_mask;
322 init.parent_names = &parent_name;
323 init.num_parents = 1;
325 pll->hw.init = &init;
327 clk = clk_register(NULL, &pll->hw);