2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MX31 specific definitions
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/init.h>
21 #include <linux/err.h>
23 #include <asm/pgtable.h>
24 #include <asm/hardware/cache-l2x0.h>
25 #include <asm/mach/map.h>
27 #include <mach/common.h>
28 #include <mach/devices-common.h>
29 #include <mach/hardware.h>
30 #include <mach/iomux-v3.h>
31 #include <mach/irqs.h>
33 static void imx3_idle(void)
35 unsigned long reg = 0;
37 mx3_cpu_lp_set(MX3_WAIT);
41 /* disable I and D cache */
42 "mrc p15, 0, %0, c1, c0, 0\n"
43 "bic %0, %0, #0x00001000\n"
44 "bic %0, %0, #0x00000004\n"
45 "mcr p15, 0, %0, c1, c0, 0\n"
46 /* invalidate I cache */
48 "mcr p15, 0, %0, c7, c5, 0\n"
49 /* clear and invalidate D cache */
51 "mcr p15, 0, %0, c7, c14, 0\n"
54 "mcr p15, 0, %0, c7, c0, 4\n"
55 "nop\n" "nop\n" "nop\n" "nop\n"
56 "nop\n" "nop\n" "nop\n"
57 /* enable I and D cache */
58 "mrc p15, 0, %0, c1, c0, 0\n"
59 "orr %0, %0, #0x00001000\n"
60 "orr %0, %0, #0x00000004\n"
61 "mcr p15, 0, %0, c1, c0, 0\n"
66 static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
69 if (mtype == MT_DEVICE) {
71 * Access all peripherals below 0x80000000 as nonshared device
72 * on mx3, but leave l2cc alone. Otherwise cache corruptions
75 if (phys_addr < 0x80000000 &&
76 !addr_in_module(phys_addr, MX3x_L2CC))
77 mtype = MT_DEVICE_NONSHARED;
80 return __arm_ioremap(phys_addr, size, mtype);
83 void imx3_init_l2x0(void)
85 void __iomem *l2x0_base;
86 void __iomem *clkctl_base;
89 * First of all, we must repair broken chip settings. There are some
90 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
91 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
92 * Workaraound is to setup the correct register setting prior enabling the
93 * L2 cache. This should not hurt already working CPUs, as they are using the
96 #define L2_MEM_VAL 0x10
98 clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
99 if (clkctl_base != NULL) {
100 writel(0x00000515, clkctl_base + L2_MEM_VAL);
101 iounmap(clkctl_base);
103 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
106 l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
107 if (IS_ERR(l2x0_base)) {
108 printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
113 l2x0_init(l2x0_base, 0x00030024, 0x00000000);
116 #ifdef CONFIG_SOC_IMX31
117 static struct map_desc mx31_io_desc[] __initdata = {
118 imx_map_entry(MX31, X_MEMC, MT_DEVICE),
119 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
120 imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
121 imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
122 imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
126 * This function initializes the memory map. It is called during the
127 * system startup to create static physical to virtual memory mappings
128 * for the IO modules.
130 void __init mx31_map_io(void)
132 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
135 void __init imx31_init_early(void)
137 mxc_set_cpu_type(MXC_CPU_MX31);
138 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
140 imx_ioremap = imx3_ioremap;
143 void __init mx31_init_irq(void)
145 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
148 static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
149 .per_2_per_addr = 1677,
152 static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
155 .bp_2_ap_addr = 1029,
158 static struct sdma_platform_data imx31_sdma_pdata __initdata = {
159 .fw_name = "sdma-imx31-to2.bin",
160 .script_addrs = &imx31_to2_sdma_script,
163 void __init imx31_soc_init(void)
165 int to_version = mx31_revision() >> 4;
169 mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
170 mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
171 mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
173 if (to_version == 1) {
174 strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
175 strlen(imx31_sdma_pdata.fw_name));
176 imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
179 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
181 imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
182 imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));
184 #endif /* ifdef CONFIG_SOC_IMX31 */
186 #ifdef CONFIG_SOC_IMX35
187 static struct map_desc mx35_io_desc[] __initdata = {
188 imx_map_entry(MX35, X_MEMC, MT_DEVICE),
189 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
190 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
191 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
192 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
195 void __init mx35_map_io(void)
197 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
200 void __init imx35_init_early(void)
202 mxc_set_cpu_type(MXC_CPU_MX35);
203 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
204 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
206 imx_ioremap = imx3_ioremap;
209 void __init mx35_init_irq(void)
211 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
214 static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
216 .uart_2_mcu_addr = 817,
217 .mcu_2_app_addr = 747,
218 .uartsh_2_mcu_addr = 1183,
219 .per_2_shp_addr = 1033,
220 .mcu_2_shp_addr = 961,
221 .ata_2_mcu_addr = 1333,
222 .mcu_2_ata_addr = 1252,
223 .app_2_mcu_addr = 683,
224 .shp_2_per_addr = 1111,
225 .shp_2_mcu_addr = 892,
228 static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
230 .uart_2_mcu_addr = 904,
231 .per_2_app_addr = 1597,
232 .mcu_2_app_addr = 834,
233 .uartsh_2_mcu_addr = 1270,
234 .per_2_shp_addr = 1120,
235 .mcu_2_shp_addr = 1048,
236 .ata_2_mcu_addr = 1429,
237 .mcu_2_ata_addr = 1339,
238 .app_2_per_addr = 1531,
239 .app_2_mcu_addr = 770,
240 .shp_2_per_addr = 1198,
241 .shp_2_mcu_addr = 979,
244 static struct sdma_platform_data imx35_sdma_pdata __initdata = {
245 .fw_name = "sdma-imx35-to2.bin",
246 .script_addrs = &imx35_to2_sdma_script,
249 void __init imx35_soc_init(void)
251 int to_version = mx35_revision() >> 4;
255 /* i.mx35 has the i.mx31 type gpio */
256 mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
257 mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
258 mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
260 if (to_version == 1) {
261 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
262 strlen(imx35_sdma_pdata.fw_name));
263 imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
266 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
268 #endif /* ifdef CONFIG_SOC_IMX35 */