2 * linux/arch/arm/mach-integrator/integrator_ap.c
4 * Copyright (C) 2000-2003 Deep Blue Solutions Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/string.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/amba/bus.h>
29 #include <linux/amba/kmi.h>
30 #include <linux/clocksource.h>
31 #include <linux/clockchips.h>
32 #include <linux/interrupt.h>
34 #include <linux/mtd/physmap.h>
35 #include <linux/clk.h>
36 #include <linux/platform_data/clk-integrator.h>
37 #include <video/vga.h>
39 #include <mach/hardware.h>
40 #include <mach/platform.h>
41 #include <asm/hardware/arm_timer.h>
42 #include <asm/setup.h>
43 #include <asm/param.h> /* HZ */
44 #include <asm/mach-types.h>
45 #include <asm/sched_clock.h>
48 #include <mach/irqs.h>
50 #include <asm/mach/arch.h>
51 #include <asm/mach/irq.h>
52 #include <asm/mach/map.h>
53 #include <asm/mach/time.h>
55 #include <plat/fpga-irq.h>
60 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
63 * Setup a VA for the Integrator interrupt controller (for header #0,
66 #define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
67 #define VA_SC_BASE __io_address(INTEGRATOR_SC_BASE)
68 #define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE)
69 #define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC)
73 * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
74 * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
75 * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k)
76 * ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
77 * ef000000 Cache flush
78 * f1000000 10000000 Core module registers
79 * f1100000 11000000 System controller registers
80 * f1200000 12000000 EBI registers
81 * f1300000 13000000 Counter/Timer
82 * f1400000 14000000 Interrupt controller
83 * f1600000 16000000 UART 0
84 * f1700000 17000000 UART 1
85 * f1a00000 1a000000 Debug LEDs
86 * f1b00000 1b000000 GPIO
89 static struct map_desc ap_io_desc[] __initdata = {
91 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
92 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
96 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
97 .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
101 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
102 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
106 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
107 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
111 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
112 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
116 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
117 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
121 .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
122 .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
126 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
127 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
131 .virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
132 .pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
136 .virtual = PCI_MEMORY_VADDR,
137 .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
141 .virtual = PCI_CONFIG_VADDR,
142 .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
146 .virtual = PCI_V3_VADDR,
147 .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE),
151 .virtual = PCI_IO_VADDR,
152 .pfn = __phys_to_pfn(PHYS_PCI_IO_BASE),
158 static void __init ap_map_io(void)
160 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
161 vga_base = PCI_MEMORY_VADDR;
164 #define INTEGRATOR_SC_VALID_INT 0x003fffff
166 static void __init ap_init_irq(void)
168 /* Disable all interrupts initially. */
169 /* Do the core module ones */
170 writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
172 /* do the header card stuff next */
173 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
174 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
176 fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
177 -1, INTEGRATOR_SC_VALID_INT, NULL);
178 integrator_clk_init(false);
182 static unsigned long ic_irq_enable;
184 static int irq_suspend(void)
186 ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
190 static void irq_resume(void)
192 /* disable all irq sources */
193 writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
194 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
195 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
197 writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
200 #define irq_suspend NULL
201 #define irq_resume NULL
204 static struct syscore_ops irq_syscore_ops = {
205 .suspend = irq_suspend,
206 .resume = irq_resume,
209 static int __init irq_syscore_init(void)
211 register_syscore_ops(&irq_syscore_ops);
216 device_initcall(irq_syscore_init);
221 #define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
222 #define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
223 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
224 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
226 static int ap_flash_init(struct platform_device *dev)
230 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
232 tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
233 writel(tmp, EBI_CSR1);
235 if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
236 writel(0xa05f, EBI_LOCK);
237 writel(tmp, EBI_CSR1);
243 static void ap_flash_exit(struct platform_device *dev)
247 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
249 tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
250 writel(tmp, EBI_CSR1);
252 if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
253 writel(0xa05f, EBI_LOCK);
254 writel(tmp, EBI_CSR1);
259 static void ap_flash_set_vpp(struct platform_device *pdev, int on)
261 void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
263 writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
266 static struct physmap_flash_data ap_flash_data = {
268 .init = ap_flash_init,
269 .exit = ap_flash_exit,
270 .set_vpp = ap_flash_set_vpp,
273 static struct resource cfi_flash_resource = {
274 .start = INTEGRATOR_FLASH_BASE,
275 .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
276 .flags = IORESOURCE_MEM,
279 static struct platform_device cfi_flash_device = {
280 .name = "physmap-flash",
283 .platform_data = &ap_flash_data,
286 .resource = &cfi_flash_resource,
289 static void __init ap_init(void)
291 unsigned long sc_dec;
294 platform_device_register(&cfi_flash_device);
296 sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
297 for (i = 0; i < 4; i++) {
298 struct lm_device *lmdev;
300 if ((sc_dec & (16 << i)) == 0)
303 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
307 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
308 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
309 lmdev->resource.flags = IORESOURCE_MEM;
310 lmdev->irq = IRQ_AP_EXPINT0 + i;
313 lm_device_register(lmdev);
318 * Where is the timer (VA)?
320 #define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
321 #define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
322 #define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
324 static unsigned long timer_reload;
326 static u32 notrace integrator_read_sched_clock(void)
328 return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
331 static void integrator_clocksource_init(unsigned long inrate)
333 void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
334 u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
335 unsigned long rate = inrate;
337 if (rate >= 1500000) {
339 ctrl |= TIMER_CTRL_DIV16;
342 writel(0xffff, base + TIMER_LOAD);
343 writel(ctrl, base + TIMER_CTRL);
345 clocksource_mmio_init(base + TIMER_VALUE, "timer2",
346 rate, 200, 16, clocksource_mmio_readl_down);
347 setup_sched_clock(integrator_read_sched_clock, 16, rate);
350 static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
353 * IRQ handler for the timer
355 static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
357 struct clock_event_device *evt = dev_id;
359 /* clear the interrupt */
360 writel(1, clkevt_base + TIMER_INTCLR);
362 evt->event_handler(evt);
367 static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
369 u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
372 writel(ctrl, clkevt_base + TIMER_CTRL);
375 case CLOCK_EVT_MODE_PERIODIC:
376 /* Enable the timer and start the periodic tick */
377 writel(timer_reload, clkevt_base + TIMER_LOAD);
378 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
379 writel(ctrl, clkevt_base + TIMER_CTRL);
381 case CLOCK_EVT_MODE_ONESHOT:
382 /* Leave the timer disabled, .set_next_event will enable it */
383 ctrl &= ~TIMER_CTRL_PERIODIC;
384 writel(ctrl, clkevt_base + TIMER_CTRL);
386 case CLOCK_EVT_MODE_UNUSED:
387 case CLOCK_EVT_MODE_SHUTDOWN:
388 case CLOCK_EVT_MODE_RESUME:
390 /* Just leave in disabled state */
396 static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
398 unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
400 writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
401 writel(next, clkevt_base + TIMER_LOAD);
402 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
407 static struct clock_event_device integrator_clockevent = {
409 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
410 .set_mode = clkevt_set_mode,
411 .set_next_event = clkevt_set_next_event,
415 static struct irqaction integrator_timer_irq = {
417 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
418 .handler = integrator_timer_interrupt,
419 .dev_id = &integrator_clockevent,
422 static void integrator_clockevent_init(unsigned long inrate)
424 unsigned long rate = inrate;
425 unsigned int ctrl = 0;
427 /* Calculate and program a divisor */
428 if (rate > 0x100000 * HZ) {
430 ctrl |= TIMER_CTRL_DIV256;
431 } else if (rate > 0x10000 * HZ) {
433 ctrl |= TIMER_CTRL_DIV16;
435 timer_reload = rate / HZ;
436 writel(ctrl, clkevt_base + TIMER_CTRL);
438 setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
439 clockevents_config_and_register(&integrator_clockevent,
445 void __init ap_init_early(void)
452 static void __init ap_init_timer(void)
457 clk = clk_get_sys("ap_timer", NULL);
459 clk_prepare_enable(clk);
460 rate = clk_get_rate(clk);
462 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
463 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
464 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
466 integrator_clocksource_init(rate);
467 integrator_clockevent_init(rate);
470 static struct sys_timer ap_timer = {
471 .init = ap_init_timer,
474 MACHINE_START(INTEGRATOR, "ARM-Integrator")
475 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
476 .atag_offset = 0x100,
477 .reserve = integrator_reserve,
479 .nr_irqs = NR_IRQS_INTEGRATOR_AP,
480 .init_early = ap_init_early,
481 .init_irq = ap_init_irq,
482 .handle_irq = fpga_handle_irq,
484 .init_machine = ap_init,
485 .restart = integrator_restart,