arch/arm/mach-integrator/integrator_ap.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_ap.c
   3  *
   4  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <linux/types.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/slab.h>
  26 #include <linux/string.h>
  27 #include <linux/syscore_ops.h>
  28 #include <linux/amba/bus.h>
  29 #include <linux/amba/kmi.h>
  30 #include <linux/clocksource.h>
  31 #include <linux/clockchips.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/io.h>
  34 #include <linux/mtd/physmap.h>
  35 #include <linux/clk.h>
  36 #include <linux/platform_data/clk-integrator.h>
  37 #include <linux/of_irq.h>
  38 #include <linux/of_address.h>
  39 #include <linux/of_platform.h>
  40 #include <video/vga.h>
  41
  42 #include <mach/hardware.h>
  43 #include <mach/platform.h>
  44 #include <asm/hardware/arm_timer.h>
  45 #include <asm/setup.h>
  46 #include <asm/param.h>          /* HZ */
  47 #include <asm/mach-types.h>
  48 #include <asm/sched_clock.h>
  49
  50 #include <mach/lm.h>
  51 #include <mach/irqs.h>
  52
  53 #include <asm/mach/arch.h>
  54 #include <asm/mach/irq.h>
  55 #include <asm/mach/map.h>
  56 #include <asm/mach/time.h>
  57
  58 #include <plat/fpga-irq.h>
  59
  60 #include "common.h"
  61
  62 /*
  63  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  64  * is the (PA >> 12).
  65  *
  66  * Setup a VA for the Integrator interrupt controller (for header #0,
  67  * just for now).
  68  */
  69 #define VA_IC_BASE      __io_address(INTEGRATOR_IC_BASE)
  70 #define VA_SC_BASE      __io_address(INTEGRATOR_SC_BASE)
  71 #define VA_EBI_BASE     __io_address(INTEGRATOR_EBI_BASE)
  72 #define VA_CMIC_BASE    __io_address(INTEGRATOR_HDR_IC)
  73
  74 /*
  75  * Logical      Physical
  76  * e8000000     40000000        PCI memory              PHYS_PCI_MEM_BASE       (max 512M)
  77  * ec000000     61000000        PCI config space        PHYS_PCI_CONFIG_BASE    (max 16M)
  78  * ed000000     62000000        PCI V3 regs             PHYS_PCI_V3_BASE        (max 64k)
  79  * ee000000     60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
  80  * ef000000                     Cache flush
  81  * f1000000     10000000        Core module registers
  82  * f1100000     11000000        System controller registers
  83  * f1200000     12000000        EBI registers
  84  * f1300000     13000000        Counter/Timer
  85  * f1400000     14000000        Interrupt controller
  86  * f1600000     16000000        UART 0
  87  * f1700000     17000000        UART 1
  88  * f1a00000     1a000000        Debug LEDs
  89  * f1b00000     1b000000        GPIO
  90  */
  91
  92 static struct map_desc ap_io_desc[] __initdata = {
  93         {
  94                 .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
  95                 .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
  96                 .length         = SZ_4K,
  97                 .type           = MT_DEVICE
  98         }, {
  99                 .virtual        = IO_ADDRESS(INTEGRATOR_SC_BASE),
 100                 .pfn            = __phys_to_pfn(INTEGRATOR_SC_BASE),
 101                 .length         = SZ_4K,
 102                 .type           = MT_DEVICE
 103         }, {
 104                 .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
 105                 .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
 106                 .length         = SZ_4K,
 107                 .type           = MT_DEVICE
 108         }, {
 109                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
 110                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
 111                 .length         = SZ_4K,
 112                 .type           = MT_DEVICE
 113         }, {
 114                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
 115                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
 116                 .length         = SZ_4K,
 117                 .type           = MT_DEVICE
 118         }, {
 119                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
 120                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
 121                 .length         = SZ_4K,
 122                 .type           = MT_DEVICE
 123         }, {
 124                 .virtual        = IO_ADDRESS(INTEGRATOR_UART1_BASE),
 125                 .pfn            = __phys_to_pfn(INTEGRATOR_UART1_BASE),
 126                 .length         = SZ_4K,
 127                 .type           = MT_DEVICE
 128         }, {
 129                 .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
 130                 .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
 131                 .length         = SZ_4K,
 132                 .type           = MT_DEVICE
 133         }, {
 134                 .virtual        = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
 135                 .pfn            = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
 136                 .length         = SZ_4K,
 137                 .type           = MT_DEVICE
 138         }, {
 139                 .virtual        = PCI_MEMORY_VADDR,
 140                 .pfn            = __phys_to_pfn(PHYS_PCI_MEM_BASE),
 141                 .length         = SZ_16M,
 142                 .type           = MT_DEVICE
 143         }, {
 144                 .virtual        = PCI_CONFIG_VADDR,
 145                 .pfn            = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
 146                 .length         = SZ_16M,
 147                 .type           = MT_DEVICE
 148         }, {
 149                 .virtual        = PCI_V3_VADDR,
 150                 .pfn            = __phys_to_pfn(PHYS_PCI_V3_BASE),
 151                 .length         = SZ_64K,
 152                 .type           = MT_DEVICE
 153         }, {
 154                 .virtual        = PCI_IO_VADDR,
 155                 .pfn            = __phys_to_pfn(PHYS_PCI_IO_BASE),
 156                 .length         = SZ_64K,
 157                 .type           = MT_DEVICE
 158         }
 159 };
 160
 161 static void __init ap_map_io(void)
 162 {
 163         iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
 164         vga_base = PCI_MEMORY_VADDR;
 165 }
 166
 167 #ifdef CONFIG_PM
 168 static unsigned long ic_irq_enable;
 169
 170 static int irq_suspend(void)
 171 {
 172         ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
 173         return 0;
 174 }
 175
 176 static void irq_resume(void)
 177 {
 178         /* disable all irq sources */
 179         writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 180         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 181         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 182
 183         writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
 184 }
 185 #else
 186 #define irq_suspend NULL
 187 #define irq_resume NULL
 188 #endif
 189
 190 static struct syscore_ops irq_syscore_ops = {
 191         .suspend        = irq_suspend,
 192         .resume         = irq_resume,
 193 };
 194
 195 static int __init irq_syscore_init(void)
 196 {
 197         register_syscore_ops(&irq_syscore_ops);
 198
 199         return 0;
 200 }
 201
 202 device_initcall(irq_syscore_init);
 203
 204 /*
 205  * Flash handling.
 206  */
 207 #define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
 208 #define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
 209 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
 210 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
 211
 212 static int ap_flash_init(struct platform_device *dev)
 213 {
 214         u32 tmp;
 215
 216         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
 217
 218         tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
 219         writel(tmp, EBI_CSR1);
 220
 221         if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
 222                 writel(0xa05f, EBI_LOCK);
 223                 writel(tmp, EBI_CSR1);
 224                 writel(0, EBI_LOCK);
 225         }
 226         return 0;
 227 }
 228
 229 static void ap_flash_exit(struct platform_device *dev)
 230 {
 231         u32 tmp;
 232
 233         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
 234
 235         tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
 236         writel(tmp, EBI_CSR1);
 237
 238         if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
 239                 writel(0xa05f, EBI_LOCK);
 240                 writel(tmp, EBI_CSR1);
 241                 writel(0, EBI_LOCK);
 242         }
 243 }
 244
 245 static void ap_flash_set_vpp(struct platform_device *pdev, int on)
 246 {
 247         void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
 248
 249         writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
 250 }
 251
 252 static struct physmap_flash_data ap_flash_data = {
 253         .width          = 4,
 254         .init           = ap_flash_init,
 255         .exit           = ap_flash_exit,
 256         .set_vpp        = ap_flash_set_vpp,
 257 };
 258
 259 static struct resource cfi_flash_resource = {
 260         .start          = INTEGRATOR_FLASH_BASE,
 261         .end            = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
 262         .flags          = IORESOURCE_MEM,
 263 };
 264
 265 static struct platform_device cfi_flash_device = {
 266         .name           = "physmap-flash",
 267         .id             = 0,
 268         .dev            = {
 269                 .platform_data  = &ap_flash_data,
 270         },
 271         .num_resources  = 1,
 272         .resource       = &cfi_flash_resource,
 273 };
 274
 275 /*
 276  * Where is the timer (VA)?
 277  */
 278 #define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
 279 #define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
 280 #define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
 281
 282 static unsigned long timer_reload;
 283
 284 static u32 notrace integrator_read_sched_clock(void)
 285 {
 286         return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
 287 }
 288
 289 static void integrator_clocksource_init(unsigned long inrate,
 290                                         void __iomem *base)
 291 {
 292         u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
 293         unsigned long rate = inrate;
 294
 295         if (rate >= 1500000) {
 296                 rate /= 16;
 297                 ctrl |= TIMER_CTRL_DIV16;
 298         }
 299
 300         writel(0xffff, base + TIMER_LOAD);
 301         writel(ctrl, base + TIMER_CTRL);
 302
 303         clocksource_mmio_init(base + TIMER_VALUE, "timer2",
 304                         rate, 200, 16, clocksource_mmio_readl_down);
 305         setup_sched_clock(integrator_read_sched_clock, 16, rate);
 306 }
 307
 308 static void __iomem * clkevt_base;
 309
 310 /*
 311  * IRQ handler for the timer
 312  */
 313 static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
 314 {
 315         struct clock_event_device *evt = dev_id;
 316
 317         /* clear the interrupt */
 318         writel(1, clkevt_base + TIMER_INTCLR);
 319
 320         evt->event_handler(evt);
 321
 322         return IRQ_HANDLED;
 323 }
 324
 325 static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
 326 {
 327         u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
 328
 329         /* Disable timer */
 330         writel(ctrl, clkevt_base + TIMER_CTRL);
 331
 332         switch (mode) {
 333         case CLOCK_EVT_MODE_PERIODIC:
 334                 /* Enable the timer and start the periodic tick */
 335                 writel(timer_reload, clkevt_base + TIMER_LOAD);
 336                 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
 337                 writel(ctrl, clkevt_base + TIMER_CTRL);
 338                 break;
 339         case CLOCK_EVT_MODE_ONESHOT:
 340                 /* Leave the timer disabled, .set_next_event will enable it */
 341                 ctrl &= ~TIMER_CTRL_PERIODIC;
 342                 writel(ctrl, clkevt_base + TIMER_CTRL);
 343                 break;
 344         case CLOCK_EVT_MODE_UNUSED:
 345         case CLOCK_EVT_MODE_SHUTDOWN:
 346         case CLOCK_EVT_MODE_RESUME:
 347         default:
 348                 /* Just leave in disabled state */
 349                 break;
 350         }
 351
 352 }
 353
 354 static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
 355 {
 356         unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
 357
 358         writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 359         writel(next, clkevt_base + TIMER_LOAD);
 360         writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 361
 362         return 0;
 363 }
 364
 365 static struct clock_event_device integrator_clockevent = {
 366         .name           = "timer1",
 367         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 368         .set_mode       = clkevt_set_mode,
 369         .set_next_event = clkevt_set_next_event,
 370         .rating         = 300,
 371 };
 372
 373 static struct irqaction integrator_timer_irq = {
 374         .name           = "timer",
 375         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 376         .handler        = integrator_timer_interrupt,
 377         .dev_id         = &integrator_clockevent,
 378 };
 379
 380 static void integrator_clockevent_init(unsigned long inrate,
 381                                 void __iomem *base, int irq)
 382 {
 383         unsigned long rate = inrate;
 384         unsigned int ctrl = 0;
 385
 386         clkevt_base = base;
 387         /* Calculate and program a divisor */
 388         if (rate > 0x100000 * HZ) {
 389                 rate /= 256;
 390                 ctrl |= TIMER_CTRL_DIV256;
 391         } else if (rate > 0x10000 * HZ) {
 392                 rate /= 16;
 393                 ctrl |= TIMER_CTRL_DIV16;
 394         }
 395         timer_reload = rate / HZ;
 396         writel(ctrl, clkevt_base + TIMER_CTRL);
 397
 398         setup_irq(irq, &integrator_timer_irq);
 399         clockevents_config_and_register(&integrator_clockevent,
 400                                         rate,
 401                                         1,
 402                                         0xffffU);
 403 }
 404
 405 void __init ap_init_early(void)
 406 {
 407 }
 408
 409 #ifdef CONFIG_OF
 410
 411 static void __init ap_init_timer_of(void)
 412 {
 413         struct device_node *node;
 414         const char *path;
 415         void __iomem *base;
 416         int err;
 417         int irq;
 418         struct clk *clk;
 419         unsigned long rate;
 420
 421         clk = clk_get_sys("ap_timer", NULL);
 422         BUG_ON(IS_ERR(clk));
 423         clk_prepare_enable(clk);
 424         rate = clk_get_rate(clk);
 425
 426         err = of_property_read_string(of_aliases,
 427                                 "arm,timer-primary", &path);
 428         if (WARN_ON(err))
 429                 return;
 430         node = of_find_node_by_path(path);
 431         base = of_iomap(node, 0);
 432         if (WARN_ON(!base))
 433                 return;
 434         writel(0, base + TIMER_CTRL);
 435         integrator_clocksource_init(rate, base);
 436
 437         err = of_property_read_string(of_aliases,
 438                                 "arm,timer-secondary", &path);
 439         if (WARN_ON(err))
 440                 return;
 441         node = of_find_node_by_path(path);
 442         base = of_iomap(node, 0);
 443         if (WARN_ON(!base))
 444                 return;
 445         irq = irq_of_parse_and_map(node, 0);
 446         writel(0, base + TIMER_CTRL);
 447         integrator_clockevent_init(rate, base, irq);
 448 }
 449
 450 static struct sys_timer ap_of_timer = {
 451         .init           = ap_init_timer_of,
 452 };
 453
 454 static const struct of_device_id fpga_irq_of_match[] __initconst = {
 455         { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
 456         { /* Sentinel */ }
 457 };
 458
 459 static void __init ap_init_irq_of(void)
 460 {
 461         /* disable core module IRQs */
 462         writel(0xffffffffU, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 463         of_irq_init(fpga_irq_of_match);
 464         integrator_clk_init(false);
 465 }
 466
 467 /* For the Device Tree, add in the UART callbacks as AUXDATA */
 468 static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
 469         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
 470                 "rtc", NULL),
 471         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
 472                 "uart0", &integrator_uart_data),
 473         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
 474                 "uart1", &integrator_uart_data),
 475         OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
 476                 "kmi0", NULL),
 477         OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
 478                 "kmi1", NULL),
 479         { /* sentinel */ },
 480 };
 481
 482 static void __init ap_init_of(void)
 483 {
 484         unsigned long sc_dec;
 485         int i;
 486
 487         of_platform_populate(NULL, of_default_bus_match_table,
 488                         ap_auxdata_lookup, NULL);
 489
 490         platform_device_register(&cfi_flash_device);
 491
 492         sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
 493         for (i = 0; i < 4; i++) {
 494                 struct lm_device *lmdev;
 495
 496                 if ((sc_dec & (16 << i)) == 0)
 497                         continue;
 498
 499                 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
 500                 if (!lmdev)
 501                         continue;
 502
 503                 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
 504                 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
 505                 lmdev->resource.flags = IORESOURCE_MEM;
 506                 lmdev->irq = IRQ_AP_EXPINT0 + i;
 507                 lmdev->id = i;
 508
 509                 lm_device_register(lmdev);
 510         }
 511 }
 512
 513 static const char * ap_dt_board_compat[] = {
 514         "arm,integrator-ap",
 515         NULL,
 516 };
 517
 518 DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
 519         .reserve        = integrator_reserve,
 520         .map_io         = ap_map_io,
 521         .nr_irqs        = NR_IRQS_INTEGRATOR_AP,
 522         .init_early     = ap_init_early,
 523         .init_irq       = ap_init_irq_of,
 524         .handle_irq     = fpga_handle_irq,
 525         .timer          = &ap_of_timer,
 526         .init_machine   = ap_init_of,
 527         .restart        = integrator_restart,
 528         .dt_compat      = ap_dt_board_compat,
 529 MACHINE_END
 530
 531 #endif
 532
 533 #ifdef CONFIG_ATAGS
 534
 535 /*
 536  * This is where non-devicetree initialization code is collected and stashed
 537  * for eventual deletion.
 538  */
 539
 540 static void __init ap_init_timer(void)
 541 {
 542         struct clk *clk;
 543         unsigned long rate;
 544
 545         clk = clk_get_sys("ap_timer", NULL);
 546         BUG_ON(IS_ERR(clk));
 547         clk_prepare_enable(clk);
 548         rate = clk_get_rate(clk);
 549
 550         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 551         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 552         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 553
 554         integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE);
 555         integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE,
 556                                 IRQ_TIMERINT1);
 557 }
 558
 559 static struct sys_timer ap_timer = {
 560         .init           = ap_init_timer,
 561 };
 562
 563 #define INTEGRATOR_SC_VALID_INT 0x003fffff
 564
 565 static void __init ap_init_irq(void)
 566 {
 567         /* Disable all interrupts initially. */
 568         /* Do the core module ones */
 569         writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 570
 571         /* do the header card stuff next */
 572         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 573         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 574
 575         fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
 576                 -1, INTEGRATOR_SC_VALID_INT, NULL);
 577         integrator_clk_init(false);
 578 }
 579
 580 static void __init ap_init(void)
 581 {
 582         unsigned long sc_dec;
 583         int i;
 584
 585         platform_device_register(&cfi_flash_device);
 586
 587         sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
 588         for (i = 0; i < 4; i++) {
 589                 struct lm_device *lmdev;
 590
 591                 if ((sc_dec & (16 << i)) == 0)
 592                         continue;
 593
 594                 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
 595                 if (!lmdev)
 596                         continue;
 597
 598                 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
 599                 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
 600                 lmdev->resource.flags = IORESOURCE_MEM;
 601                 lmdev->irq = IRQ_AP_EXPINT0 + i;
 602                 lmdev->id = i;
 603
 604                 lm_device_register(lmdev);
 605         }
 606
 607         integrator_init(false);
 608 }
 609
 610 MACHINE_START(INTEGRATOR, "ARM-Integrator")
 611         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 612         .atag_offset    = 0x100,
 613         .reserve        = integrator_reserve,
 614         .map_io         = ap_map_io,
 615         .nr_irqs        = NR_IRQS_INTEGRATOR_AP,
 616         .init_early     = ap_init_early,
 617         .init_irq       = ap_init_irq,
 618         .handle_irq     = fpga_handle_irq,
 619         .timer          = &ap_timer,
 620         .init_machine   = ap_init,
 621         .restart        = integrator_restart,
 622 MACHINE_END
 623
 624 #endif