2 * arch/arm/mach-ixp4xx/include/mach/io.h
4 * Author: Deepak Saxena <dsaxena@plexity.net>
6 * Copyright (C) 2002-2005 MontaVista Software, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __ASM_ARM_ARCH_IO_H
14 #define __ASM_ARM_ARCH_IO_H
16 #include <linux/bitops.h>
18 #include <mach/hardware.h>
20 extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
21 extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
25 * IXP4xx provides two methods of accessing PCI memory space:
27 * 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB).
28 * To access PCI via this space, we simply ioremap() the BAR
29 * into the kernel and we can use the standard read[bwl]/write[bwl]
30 * macros. This is the preffered method due to speed but it
31 * limits the system to just 64MB of PCI memory. This can be
32 * problematic if using video cards and other memory-heavy targets.
34 * 2) If > 64MB of memory space is required, the IXP4xx can use indirect
35 * registers to access the whole 4 GB of PCI memory space (as we do below
36 * for I/O transactions). This allows currently for up to 1 GB (0x10000000
37 * to 0x4FFFFFFF) of memory on the bus. The disadvantage of this is that
38 * every PCI access requires three local register accesses plus a spinlock,
39 * but in some cases the performance hit is acceptable. In addition, you
40 * cannot mmap() PCI devices in this case.
42 #ifdef CONFIG_IXP4XX_INDIRECT_PCI
45 * In the case of using indirect PCI, we simply return the actual PCI
46 * address and our read/write implementation use that to drive the
47 * access registers. If something outside of PCI is ioremap'd, we
48 * fallback to the default.
51 extern unsigned long pcibios_min_mem;
52 static inline int is_pci_memory(u32 addr)
54 return (addr >= pcibios_min_mem) && (addr <= 0x4FFFFFFF);
57 #define writeb(v, p) __indirect_writeb(v, p)
58 #define writew(v, p) __indirect_writew(v, p)
59 #define writel(v, p) __indirect_writel(v, p)
61 #define writeb_relaxed(v, p) __indirect_writeb(v, p)
62 #define writew_relaxed(v, p) __indirect_writew(v, p)
63 #define writel_relaxed(v, p) __indirect_writel(v, p)
65 #define writesb(p, v, l) __indirect_writesb(p, v, l)
66 #define writesw(p, v, l) __indirect_writesw(p, v, l)
67 #define writesl(p, v, l) __indirect_writesl(p, v, l)
69 #define readb(p) __indirect_readb(p)
70 #define readw(p) __indirect_readw(p)
71 #define readl(p) __indirect_readl(p)
73 #define readb_relaxed(p) __indirect_readb(p)
74 #define readw_relaxed(p) __indirect_readw(p)
75 #define readl_relaxed(p) __indirect_readl(p)
77 #define readsb(p, v, l) __indirect_readsb(p, v, l)
78 #define readsw(p, v, l) __indirect_readsw(p, v, l)
79 #define readsl(p, v, l) __indirect_readsl(p, v, l)
81 static inline void __indirect_writeb(u8 value, volatile void __iomem *p)
84 u32 n, byte_enables, data;
86 if (!is_pci_memory(addr)) {
87 __raw_writeb(value, p);
92 byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
93 data = value << (8*n);
94 ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
97 static inline void __indirect_writesb(volatile void __iomem *bus_addr,
98 const u8 *vaddr, int count)
101 writeb(*vaddr++, bus_addr);
104 static inline void __indirect_writew(u16 value, volatile void __iomem *p)
107 u32 n, byte_enables, data;
109 if (!is_pci_memory(addr)) {
110 __raw_writew(value, p);
115 byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
116 data = value << (8*n);
117 ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
120 static inline void __indirect_writesw(volatile void __iomem *bus_addr,
121 const u16 *vaddr, int count)
124 writew(*vaddr++, bus_addr);
127 static inline void __indirect_writel(u32 value, volatile void __iomem *p)
129 u32 addr = (__force u32)p;
131 if (!is_pci_memory(addr)) {
132 __raw_writel(value, p);
136 ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value);
139 static inline void __indirect_writesl(volatile void __iomem *bus_addr,
140 const u32 *vaddr, int count)
143 writel(*vaddr++, bus_addr);
146 static inline unsigned char __indirect_readb(const volatile void __iomem *p)
149 u32 n, byte_enables, data;
151 if (!is_pci_memory(addr))
152 return __raw_readb(p);
155 byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
156 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
159 return data >> (8*n);
162 static inline void __indirect_readsb(const volatile void __iomem *bus_addr,
163 u8 *vaddr, u32 count)
166 *vaddr++ = readb(bus_addr);
169 static inline unsigned short __indirect_readw(const volatile void __iomem *p)
172 u32 n, byte_enables, data;
174 if (!is_pci_memory(addr))
175 return __raw_readw(p);
178 byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
179 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
185 static inline void __indirect_readsw(const volatile void __iomem *bus_addr,
186 u16 *vaddr, u32 count)
189 *vaddr++ = readw(bus_addr);
192 static inline unsigned long __indirect_readl(const volatile void __iomem *p)
194 u32 addr = (__force u32)p;
197 if (!is_pci_memory(addr))
198 return __raw_readl(p);
200 if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
206 static inline void __indirect_readsl(const volatile void __iomem *bus_addr,
207 u32 *vaddr, u32 count)
210 *vaddr++ = readl(bus_addr);
215 * We can use the built-in functions b/c they end up calling writeb/readb
217 #define memset_io(c,v,l) _memset_io((c),(v),(l))
218 #define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l))
219 #define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l))
221 #endif /* CONFIG_IXP4XX_INDIRECT_PCI */
225 #define __io(v) __typesafe_io(v)
230 * IXP4xx does not have a transparent cpu -> PCI I/O translation
231 * window. Instead, it has a set of registers that must be tweaked
232 * with the proper byte lanes, command types, and address for the
233 * transaction. This means that we need to override the default
238 static inline void outb(u8 value, u32 addr)
240 u32 n, byte_enables, data;
242 byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
243 data = value << (8*n);
244 ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
248 static inline void outsb(u32 io_addr, const u8 *vaddr, u32 count)
251 outb(*vaddr++, io_addr);
255 static inline void outw(u16 value, u32 addr)
257 u32 n, byte_enables, data;
259 byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
260 data = value << (8*n);
261 ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
265 static inline void outsw(u32 io_addr, const u16 *vaddr, u32 count)
268 outw(cpu_to_le16(*vaddr++), io_addr);
272 static inline void outl(u32 value, u32 addr)
274 ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value);
278 static inline void outsl(u32 io_addr, const u32 *vaddr, u32 count)
281 outl(cpu_to_le32(*vaddr++), io_addr);
285 static inline u8 inb(u32 addr)
287 u32 n, byte_enables, data;
289 byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
290 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
293 return data >> (8*n);
297 static inline void insb(u32 io_addr, u8 *vaddr, u32 count)
300 *vaddr++ = inb(io_addr);
304 static inline u16 inw(u32 addr)
306 u32 n, byte_enables, data;
308 byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
309 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
316 static inline void insw(u32 io_addr, u16 *vaddr, u32 count)
319 *vaddr++ = le16_to_cpu(inw(io_addr));
323 static inline u32 inl(u32 addr)
326 if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data))
333 static inline void insl(u32 io_addr, u32 *vaddr, u32 count)
336 *vaddr++ = le32_to_cpu(inl(io_addr));
339 #define PIO_OFFSET 0x10000UL
340 #define PIO_MASK 0x0ffffUL
342 #define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \
343 ((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
345 #define ioread8(p) ioread8(p)
346 static inline unsigned int ioread8(const void __iomem *addr)
348 unsigned long port = (unsigned long __force)addr;
349 if (__is_io_address(port))
350 return (unsigned int)inb(port & PIO_MASK);
352 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
353 return (unsigned int)__raw_readb(addr);
355 return (unsigned int)__indirect_readb(addr);
359 #define ioread8_rep(p, v, c) ioread8_rep(p, v, c)
360 static inline void ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
362 unsigned long port = (unsigned long __force)addr;
363 if (__is_io_address(port))
364 insb(port & PIO_MASK, vaddr, count);
366 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
367 __raw_readsb(addr, vaddr, count);
369 __indirect_readsb(addr, vaddr, count);
373 #define ioread16(p) ioread16(p)
374 static inline unsigned int ioread16(const void __iomem *addr)
376 unsigned long port = (unsigned long __force)addr;
377 if (__is_io_address(port))
378 return (unsigned int)inw(port & PIO_MASK);
380 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
381 return le16_to_cpu((__force __le16)__raw_readw(addr));
383 return (unsigned int)__indirect_readw(addr);
387 #define ioread16_rep(p, v, c) ioread16_rep(p, v, c)
388 static inline void ioread16_rep(const void __iomem *addr, void *vaddr,
391 unsigned long port = (unsigned long __force)addr;
392 if (__is_io_address(port))
393 insw(port & PIO_MASK, vaddr, count);
395 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
396 __raw_readsw(addr, vaddr, count);
398 __indirect_readsw(addr, vaddr, count);
402 #define ioread32(p) ioread32(p)
403 static inline unsigned int ioread32(const void __iomem *addr)
405 unsigned long port = (unsigned long __force)addr;
406 if (__is_io_address(port))
407 return (unsigned int)inl(port & PIO_MASK);
409 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
410 return le32_to_cpu((__force __le32)__raw_readl(addr));
412 return (unsigned int)__indirect_readl(addr);
417 #define ioread32_rep(p, v, c) ioread32_rep(p, v, c)
418 static inline void ioread32_rep(const void __iomem *addr, void *vaddr,
421 unsigned long port = (unsigned long __force)addr;
422 if (__is_io_address(port))
423 insl(port & PIO_MASK, vaddr, count);
425 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
426 __raw_readsl(addr, vaddr, count);
428 __indirect_readsl(addr, vaddr, count);
432 #define iowrite8(v, p) iowrite8(v, p)
433 static inline void iowrite8(u8 value, void __iomem *addr)
435 unsigned long port = (unsigned long __force)addr;
436 if (__is_io_address(port))
437 outb(value, port & PIO_MASK);
439 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
440 __raw_writeb(value, addr);
442 __indirect_writeb(value, addr);
446 #define iowrite8_rep(p, v, c) iowrite8_rep(p, v, c)
447 static inline void iowrite8_rep(void __iomem *addr, const void *vaddr,
450 unsigned long port = (unsigned long __force)addr;
451 if (__is_io_address(port))
452 outsb(port & PIO_MASK, vaddr, count);
454 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
455 __raw_writesb(addr, vaddr, count);
457 __indirect_writesb(addr, vaddr, count);
461 #define iowrite16(v, p) iowrite16(v, p)
462 static inline void iowrite16(u16 value, void __iomem *addr)
464 unsigned long port = (unsigned long __force)addr;
465 if (__is_io_address(port))
466 outw(value, port & PIO_MASK);
468 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
469 __raw_writew(cpu_to_le16(value), addr);
471 __indirect_writew(value, addr);
475 #define iowrite16_rep(p, v, c) iowrite16_rep(p, v, c)
476 static inline void iowrite16_rep(void __iomem *addr, const void *vaddr,
479 unsigned long port = (unsigned long __force)addr;
480 if (__is_io_address(port))
481 outsw(port & PIO_MASK, vaddr, count);
483 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
484 __raw_writesw(addr, vaddr, count);
486 __indirect_writesw(addr, vaddr, count);
490 #define iowrite32(v, p) iowrite32(v, p)
491 static inline void iowrite32(u32 value, void __iomem *addr)
493 unsigned long port = (unsigned long __force)addr;
494 if (__is_io_address(port))
495 outl(value, port & PIO_MASK);
497 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
498 __raw_writel((u32 __force)cpu_to_le32(value), addr);
500 __indirect_writel(value, addr);
504 #define iowrite32_rep(p, v, c) iowrite32_rep(p, v, c)
505 static inline void iowrite32_rep(void __iomem *addr, const void *vaddr,
508 unsigned long port = (unsigned long __force)addr;
509 if (__is_io_address(port))
510 outsl(port & PIO_MASK, vaddr, count);
512 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
513 __raw_writesl(addr, vaddr, count);
515 __indirect_writesl(addr, vaddr, count);
519 #define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET))
520 #define ioport_unmap(addr)
521 #endif /* CONFIG_PCI */
523 #endif /* __ASM_ARM_ARCH_IO_H */