arch/arm/mach-omap1/clock.c

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock.c
   3  *
   4  *  Copyright (C) 2004 - 2005 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *
   7  *  Modified to use omap shared clock framework by
   8  *  Tony Lindgren <tony@atomide.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/io.h>
  21
  22 #include <asm/mach-types.h>
  23 #include <asm/clkdev.h>
  24
  25 #include <mach/cpu.h>
  26 #include <mach/usb.h>
  27 #include <mach/clock.h>
  28 #include <mach/sram.h>
  29
  30 static const struct clkops clkops_generic;
  31 static const struct clkops clkops_uart;
  32 static const struct clkops clkops_dspck;
  33
  34 #include "clock.h"
  35
  36 static int clk_omap1_dummy_enable(struct clk *clk)
  37 {
  38         return 0;
  39 }
  40
  41 static void clk_omap1_dummy_disable(struct clk *clk)
  42 {
  43 }
  44
  45 static const struct clkops clkops_dummy = {
  46         .enable = clk_omap1_dummy_enable,
  47         .disable = clk_omap1_dummy_disable,
  48 };
  49
  50 static struct clk dummy_ck = {
  51         .name   = "dummy",
  52         .ops    = &clkops_dummy,
  53         .flags  = RATE_FIXED,
  54 };
  55
  56 struct omap_clk {
  57         u32             cpu;
  58         struct clk_lookup lk;
  59 };
  60
  61 #define CLK(dev, con, ck, cp)           \
  62         {                               \
  63                  .cpu = cp,             \
  64                 .lk = {                 \
  65                         .dev_id = dev,  \
  66                         .con_id = con,  \
  67                         .clk = ck,      \
  68                 },                      \
  69         }
  70
  71 #define CK_310  (1 << 0)
  72 #define CK_730  (1 << 1)
  73 #define CK_1510 (1 << 2)
  74 #define CK_16XX (1 << 3)
  75
  76 static struct omap_clk omap_clks[] = {
  77         /* non-ULPD clocks */
  78         CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310),
  79         CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310),
  80         /* CK_GEN1 clocks */
  81         CLK(NULL,       "ck_dpll1out",  &ck_dpll1out.clk, CK_16XX),
  82         CLK(NULL,       "ck_sossi",     &sossi_ck,      CK_16XX),
  83         CLK(NULL,       "arm_ck",       &arm_ck,        CK_16XX | CK_1510 | CK_310),
  84         CLK(NULL,       "armper_ck",    &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
  85         CLK(NULL,       "arm_gpio_ck",  &arm_gpio_ck,   CK_1510 | CK_310),
  86         CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
  87         CLK(NULL,       "armtim_ck",    &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
  88         CLK(NULL,       "armwdt_ck",    &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
  89         CLK(NULL,       "arminth_ck",   &arminth_ck1510, CK_1510 | CK_310),
  90         CLK(NULL,       "arminth_ck",   &arminth_ck16xx, CK_16XX),
  91         /* CK_GEN2 clocks */
  92         CLK(NULL,       "dsp_ck",       &dsp_ck,        CK_16XX | CK_1510 | CK_310),
  93         CLK(NULL,       "dspmmu_ck",    &dspmmu_ck,     CK_16XX | CK_1510 | CK_310),
  94         CLK(NULL,       "dspper_ck",    &dspper_ck,     CK_16XX | CK_1510 | CK_310),
  95         CLK(NULL,       "dspxor_ck",    &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
  96         CLK(NULL,       "dsptim_ck",    &dsptim_ck,     CK_16XX | CK_1510 | CK_310),
  97         /* CK_GEN3 clocks */
  98         CLK(NULL,       "tc_ck",        &tc_ck.clk,     CK_16XX | CK_1510 | CK_310 | CK_730),
  99         CLK(NULL,       "tipb_ck",      &tipb_ck,       CK_1510 | CK_310),
 100         CLK(NULL,       "l3_ocpi_ck",   &l3_ocpi_ck,    CK_16XX),
 101         CLK(NULL,       "tc1_ck",       &tc1_ck,        CK_16XX),
 102         CLK(NULL,       "tc2_ck",       &tc2_ck,        CK_16XX),
 103         CLK(NULL,       "dma_ck",       &dma_ck,        CK_16XX | CK_1510 | CK_310),
 104         CLK(NULL,       "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
 105         CLK(NULL,       "api_ck",       &api_ck.clk,    CK_16XX | CK_1510 | CK_310),
 106         CLK(NULL,       "lb_ck",        &lb_ck.clk,     CK_1510 | CK_310),
 107         CLK(NULL,       "rhea1_ck",     &rhea1_ck,      CK_16XX),
 108         CLK(NULL,       "rhea2_ck",     &rhea2_ck,      CK_16XX),
 109         CLK(NULL,       "lcd_ck",       &lcd_ck_16xx,   CK_16XX | CK_730),
 110         CLK(NULL,       "lcd_ck",       &lcd_ck_1510.clk, CK_1510 | CK_310),
 111         /* ULPD clocks */
 112         CLK(NULL,       "uart1_ck",     &uart1_1510,    CK_1510 | CK_310),
 113         CLK(NULL,       "uart1_ck",     &uart1_16xx.clk, CK_16XX),
 114         CLK(NULL,       "uart2_ck",     &uart2_ck,      CK_16XX | CK_1510 | CK_310),
 115         CLK(NULL,       "uart3_ck",     &uart3_1510,    CK_1510 | CK_310),
 116         CLK(NULL,       "uart3_ck",     &uart3_16xx.clk, CK_16XX),
 117         CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),
 118         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck1510, CK_1510 | CK_310),
 119         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck16xx, CK_16XX),
 120         CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX),
 121         CLK(NULL,       "mclk",         &mclk_1510,     CK_1510 | CK_310),
 122         CLK(NULL,       "mclk",         &mclk_16xx,     CK_16XX),
 123         CLK(NULL,       "bclk",         &bclk_1510,     CK_1510 | CK_310),
 124         CLK(NULL,       "bclk",         &bclk_16xx,     CK_16XX),
 125         CLK("mmci-omap.0", "mmc_ck",    &mmc1_ck,       CK_16XX | CK_1510 | CK_310),
 126         CLK("mmci-omap.1", "mmc_ck",    &mmc2_ck,       CK_16XX),
 127         /* Virtual clocks */
 128         CLK(NULL,       "mpu",          &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
 129         CLK("i2c_omap.1", "i2c_fck",    &i2c_fck,       CK_16XX | CK_1510 | CK_310),
 130         CLK("i2c_omap.1", "i2c_ick",    &i2c_ick,       CK_16XX),
 131 };
 132
 133 static int omap1_clk_enable_generic(struct clk * clk);
 134 static int omap1_clk_enable(struct clk *clk);
 135 static void omap1_clk_disable_generic(struct clk * clk);
 136 static void omap1_clk_disable(struct clk *clk);
 137
 138 __u32 arm_idlect1_mask;
 139
 140 /*-------------------------------------------------------------------------
 141  * Omap1 specific clock functions
 142  *-------------------------------------------------------------------------*/
 143
 144 static void omap1_watchdog_recalc(struct clk * clk)
 145 {
 146         clk->rate = clk->parent->rate / 14;
 147 }
 148
 149 static void omap1_uart_recalc(struct clk * clk)
 150 {
 151         unsigned int val = omap_readl(clk->enable_reg);
 152         if (val & clk->enable_bit)
 153                 clk->rate = 48000000;
 154         else
 155                 clk->rate = 12000000;
 156 }
 157
 158 static void omap1_sossi_recalc(struct clk *clk)
 159 {
 160         u32 div = omap_readl(MOD_CONF_CTRL_1);
 161
 162         div = (div >> 17) & 0x7;
 163         div++;
 164         clk->rate = clk->parent->rate / div;
 165 }
 166
 167 static int omap1_clk_enable_dsp_domain(struct clk *clk)
 168 {
 169         int retval;
 170
 171         retval = omap1_clk_enable(&api_ck.clk);
 172         if (!retval) {
 173                 retval = omap1_clk_enable_generic(clk);
 174                 omap1_clk_disable(&api_ck.clk);
 175         }
 176
 177         return retval;
 178 }
 179
 180 static void omap1_clk_disable_dsp_domain(struct clk *clk)
 181 {
 182         if (omap1_clk_enable(&api_ck.clk) == 0) {
 183                 omap1_clk_disable_generic(clk);
 184                 omap1_clk_disable(&api_ck.clk);
 185         }
 186 }
 187
 188 static const struct clkops clkops_dspck = {
 189         .enable         = &omap1_clk_enable_dsp_domain,
 190         .disable        = &omap1_clk_disable_dsp_domain,
 191 };
 192
 193 static int omap1_clk_enable_uart_functional(struct clk *clk)
 194 {
 195         int ret;
 196         struct uart_clk *uclk;
 197
 198         ret = omap1_clk_enable_generic(clk);
 199         if (ret == 0) {
 200                 /* Set smart idle acknowledgement mode */
 201                 uclk = (struct uart_clk *)clk;
 202                 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
 203                             uclk->sysc_addr);
 204         }
 205
 206         return ret;
 207 }
 208
 209 static void omap1_clk_disable_uart_functional(struct clk *clk)
 210 {
 211         struct uart_clk *uclk;
 212
 213         /* Set force idle acknowledgement mode */
 214         uclk = (struct uart_clk *)clk;
 215         omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
 216
 217         omap1_clk_disable_generic(clk);
 218 }
 219
 220 static const struct clkops clkops_uart = {
 221         .enable         = &omap1_clk_enable_uart_functional,
 222         .disable        = &omap1_clk_disable_uart_functional,
 223 };
 224
 225 static void omap1_clk_allow_idle(struct clk *clk)
 226 {
 227         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
 228
 229         if (!(clk->flags & CLOCK_IDLE_CONTROL))
 230                 return;
 231
 232         if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
 233                 arm_idlect1_mask |= 1 << iclk->idlect_shift;
 234 }
 235
 236 static void omap1_clk_deny_idle(struct clk *clk)
 237 {
 238         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
 239
 240         if (!(clk->flags & CLOCK_IDLE_CONTROL))
 241                 return;
 242
 243         if (iclk->no_idle_count++ == 0)
 244                 arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
 245 }
 246
 247 static __u16 verify_ckctl_value(__u16 newval)
 248 {
 249         /* This function checks for following limitations set
 250          * by the hardware (all conditions must be true):
 251          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 252          * ARM_CK >= TC_CK
 253          * DSP_CK >= TC_CK
 254          * DSPMMU_CK >= TC_CK
 255          *
 256          * In addition following rules are enforced:
 257          * LCD_CK <= TC_CK
 258          * ARMPER_CK <= TC_CK
 259          *
 260          * However, maximum frequencies are not checked for!
 261          */
 262         __u8 per_exp;
 263         __u8 lcd_exp;
 264         __u8 arm_exp;
 265         __u8 dsp_exp;
 266         __u8 tc_exp;
 267         __u8 dspmmu_exp;
 268
 269         per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
 270         lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
 271         arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
 272         dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
 273         tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
 274         dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
 275
 276         if (dspmmu_exp < dsp_exp)
 277                 dspmmu_exp = dsp_exp;
 278         if (dspmmu_exp > dsp_exp+1)
 279                 dspmmu_exp = dsp_exp+1;
 280         if (tc_exp < arm_exp)
 281                 tc_exp = arm_exp;
 282         if (tc_exp < dspmmu_exp)
 283                 tc_exp = dspmmu_exp;
 284         if (tc_exp > lcd_exp)
 285                 lcd_exp = tc_exp;
 286         if (tc_exp > per_exp)
 287                 per_exp = tc_exp;
 288
 289         newval &= 0xf000;
 290         newval |= per_exp << CKCTL_PERDIV_OFFSET;
 291         newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
 292         newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
 293         newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
 294         newval |= tc_exp << CKCTL_TCDIV_OFFSET;
 295         newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
 296
 297         return newval;
 298 }
 299
 300 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
 301 {
 302         /* Note: If target frequency is too low, this function will return 4,
 303          * which is invalid value. Caller must check for this value and act
 304          * accordingly.
 305          *
 306          * Note: This function does not check for following limitations set
 307          * by the hardware (all conditions must be true):
 308          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 309          * ARM_CK >= TC_CK
 310          * DSP_CK >= TC_CK
 311          * DSPMMU_CK >= TC_CK
 312          */
 313         unsigned long realrate;
 314         struct clk * parent;
 315         unsigned  dsor_exp;
 316
 317         parent = clk->parent;
 318         if (unlikely(parent == NULL))
 319                 return -EIO;
 320
 321         realrate = parent->rate;
 322         for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
 323                 if (realrate <= rate)
 324                         break;
 325
 326                 realrate /= 2;
 327         }
 328
 329         return dsor_exp;
 330 }
 331
 332 static void omap1_ckctl_recalc(struct clk * clk)
 333 {
 334         int dsor;
 335
 336         /* Calculate divisor encoded as 2-bit exponent */
 337         dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
 338
 339         if (unlikely(clk->rate == clk->parent->rate / dsor))
 340                 return; /* No change, quick exit */
 341         clk->rate = clk->parent->rate / dsor;
 342 }
 343
 344 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk)
 345 {
 346         int dsor;
 347
 348         /* Calculate divisor encoded as 2-bit exponent
 349          *
 350          * The clock control bits are in DSP domain,
 351          * so api_ck is needed for access.
 352          * Note that DSP_CKCTL virt addr = phys addr, so
 353          * we must use __raw_readw() instead of omap_readw().
 354          */
 355         omap1_clk_enable(&api_ck.clk);
 356         dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
 357         omap1_clk_disable(&api_ck.clk);
 358
 359         if (unlikely(clk->rate == clk->parent->rate / dsor))
 360                 return; /* No change, quick exit */
 361         clk->rate = clk->parent->rate / dsor;
 362 }
 363
 364 /* MPU virtual clock functions */
 365 static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
 366 {
 367         /* Find the highest supported frequency <= rate and switch to it */
 368         struct mpu_rate * ptr;
 369
 370         if (clk != &virtual_ck_mpu)
 371                 return -EINVAL;
 372
 373         for (ptr = rate_table; ptr->rate; ptr++) {
 374                 if (ptr->xtal != ck_ref.rate)
 375                         continue;
 376
 377                 /* DPLL1 cannot be reprogrammed without risking system crash */
 378                 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
 379                         continue;
 380
 381                 /* Can check only after xtal frequency check */
 382                 if (ptr->rate <= rate)
 383                         break;
 384         }
 385
 386         if (!ptr->rate)
 387                 return -EINVAL;
 388
 389         /*
 390          * In most cases we should not need to reprogram DPLL.
 391          * Reprogramming the DPLL is tricky, it must be done from SRAM.
 392          * (on 730, bit 13 must always be 1)
 393          */
 394         if (cpu_is_omap730())
 395                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
 396         else
 397                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
 398
 399         ck_dpll1.rate = ptr->pll_rate;
 400         return 0;
 401 }
 402
 403 static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
 404 {
 405         int dsor_exp;
 406         u16 regval;
 407
 408         dsor_exp = calc_dsor_exp(clk, rate);
 409         if (dsor_exp > 3)
 410                 dsor_exp = -EINVAL;
 411         if (dsor_exp < 0)
 412                 return dsor_exp;
 413
 414         regval = __raw_readw(DSP_CKCTL);
 415         regval &= ~(3 << clk->rate_offset);
 416         regval |= dsor_exp << clk->rate_offset;
 417         __raw_writew(regval, DSP_CKCTL);
 418         clk->rate = clk->parent->rate / (1 << dsor_exp);
 419
 420         return 0;
 421 }
 422
 423 static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 424 {
 425         int dsor_exp = calc_dsor_exp(clk, rate);
 426         if (dsor_exp < 0)
 427                 return dsor_exp;
 428         if (dsor_exp > 3)
 429                 dsor_exp = 3;
 430         return clk->parent->rate / (1 << dsor_exp);
 431 }
 432
 433 static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 434 {
 435         int dsor_exp;
 436         u16 regval;
 437
 438         dsor_exp = calc_dsor_exp(clk, rate);
 439         if (dsor_exp > 3)
 440                 dsor_exp = -EINVAL;
 441         if (dsor_exp < 0)
 442                 return dsor_exp;
 443
 444         regval = omap_readw(ARM_CKCTL);
 445         regval &= ~(3 << clk->rate_offset);
 446         regval |= dsor_exp << clk->rate_offset;
 447         regval = verify_ckctl_value(regval);
 448         omap_writew(regval, ARM_CKCTL);
 449         clk->rate = clk->parent->rate / (1 << dsor_exp);
 450         return 0;
 451 }
 452
 453 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate)
 454 {
 455         /* Find the highest supported frequency <= rate */
 456         struct mpu_rate * ptr;
 457         long  highest_rate;
 458
 459         if (clk != &virtual_ck_mpu)
 460                 return -EINVAL;
 461
 462         highest_rate = -EINVAL;
 463
 464         for (ptr = rate_table; ptr->rate; ptr++) {
 465                 if (ptr->xtal != ck_ref.rate)
 466                         continue;
 467
 468                 highest_rate = ptr->rate;
 469
 470                 /* Can check only after xtal frequency check */
 471                 if (ptr->rate <= rate)
 472                         break;
 473         }
 474
 475         return highest_rate;
 476 }
 477
 478 static unsigned calc_ext_dsor(unsigned long rate)
 479 {
 480         unsigned dsor;
 481
 482         /* MCLK and BCLK divisor selection is not linear:
 483          * freq = 96MHz / dsor
 484          *
 485          * RATIO_SEL range: dsor <-> RATIO_SEL
 486          * 0..6: (RATIO_SEL+2) <-> (dsor-2)
 487          * 6..48:  (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
 488          * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
 489          * can not be used.
 490          */
 491         for (dsor = 2; dsor < 96; ++dsor) {
 492                 if ((dsor & 1) && dsor > 8)
 493                         continue;
 494                 if (rate >= 96000000 / dsor)
 495                         break;
 496         }
 497         return dsor;
 498 }
 499
 500 /* Only needed on 1510 */
 501 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
 502 {
 503         unsigned int val;
 504
 505         val = omap_readl(clk->enable_reg);
 506         if (rate == 12000000)
 507                 val &= ~(1 << clk->enable_bit);
 508         else if (rate == 48000000)
 509                 val |= (1 << clk->enable_bit);
 510         else
 511                 return -EINVAL;
 512         omap_writel(val, clk->enable_reg);
 513         clk->rate = rate;
 514
 515         return 0;
 516 }
 517
 518 /* External clock (MCLK & BCLK) functions */
 519 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
 520 {
 521         unsigned dsor;
 522         __u16 ratio_bits;
 523
 524         dsor = calc_ext_dsor(rate);
 525         clk->rate = 96000000 / dsor;
 526         if (dsor > 8)
 527                 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
 528         else
 529                 ratio_bits = (dsor - 2) << 2;
 530
 531         ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
 532         omap_writew(ratio_bits, clk->enable_reg);
 533
 534         return 0;
 535 }
 536
 537 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
 538 {
 539         u32 l;
 540         int div;
 541         unsigned long p_rate;
 542
 543         p_rate = clk->parent->rate;
 544         /* Round towards slower frequency */
 545         div = (p_rate + rate - 1) / rate;
 546         div--;
 547         if (div < 0 || div > 7)
 548                 return -EINVAL;
 549
 550         l = omap_readl(MOD_CONF_CTRL_1);
 551         l &= ~(7 << 17);
 552         l |= div << 17;
 553         omap_writel(l, MOD_CONF_CTRL_1);
 554
 555         clk->rate = p_rate / (div + 1);
 556
 557         return 0;
 558 }
 559
 560 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)
 561 {
 562         return 96000000 / calc_ext_dsor(rate);
 563 }
 564
 565 static void omap1_init_ext_clk(struct clk * clk)
 566 {
 567         unsigned dsor;
 568         __u16 ratio_bits;
 569
 570         /* Determine current rate and ensure clock is based on 96MHz APLL */
 571         ratio_bits = omap_readw(clk->enable_reg) & ~1;
 572         omap_writew(ratio_bits, clk->enable_reg);
 573
 574         ratio_bits = (ratio_bits & 0xfc) >> 2;
 575         if (ratio_bits > 6)
 576                 dsor = (ratio_bits - 6) * 2 + 8;
 577         else
 578                 dsor = ratio_bits + 2;
 579
 580         clk-> rate = 96000000 / dsor;
 581 }
 582
 583 static int omap1_clk_enable(struct clk *clk)
 584 {
 585         int ret = 0;
 586         if (clk->usecount++ == 0) {
 587                 if (likely(clk->parent)) {
 588                         ret = omap1_clk_enable(clk->parent);
 589
 590                         if (unlikely(ret != 0)) {
 591                                 clk->usecount--;
 592                                 return ret;
 593                         }
 594
 595                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
 596                                 omap1_clk_deny_idle(clk->parent);
 597                 }
 598
 599                 ret = clk->ops->enable(clk);
 600
 601                 if (unlikely(ret != 0) && clk->parent) {
 602                         omap1_clk_disable(clk->parent);
 603                         clk->usecount--;
 604                 }
 605         }
 606
 607         return ret;
 608 }
 609
 610 static void omap1_clk_disable(struct clk *clk)
 611 {
 612         if (clk->usecount > 0 && !(--clk->usecount)) {
 613                 clk->ops->disable(clk);
 614                 if (likely(clk->parent)) {
 615                         omap1_clk_disable(clk->parent);
 616                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
 617                                 omap1_clk_allow_idle(clk->parent);
 618                 }
 619         }
 620 }
 621
 622 static int omap1_clk_enable_generic(struct clk *clk)
 623 {
 624         __u16 regval16;
 625         __u32 regval32;
 626
 627         if (unlikely(clk->enable_reg == NULL)) {
 628                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
 629                        clk->name);
 630                 return -EINVAL;
 631         }
 632
 633         if (clk->flags & ENABLE_REG_32BIT) {
 634                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 635                         regval32 = __raw_readl(clk->enable_reg);
 636                         regval32 |= (1 << clk->enable_bit);
 637                         __raw_writel(regval32, clk->enable_reg);
 638                 } else {
 639                         regval32 = omap_readl(clk->enable_reg);
 640                         regval32 |= (1 << clk->enable_bit);
 641                         omap_writel(regval32, clk->enable_reg);
 642                 }
 643         } else {
 644                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 645                         regval16 = __raw_readw(clk->enable_reg);
 646                         regval16 |= (1 << clk->enable_bit);
 647                         __raw_writew(regval16, clk->enable_reg);
 648                 } else {
 649                         regval16 = omap_readw(clk->enable_reg);
 650                         regval16 |= (1 << clk->enable_bit);
 651                         omap_writew(regval16, clk->enable_reg);
 652                 }
 653         }
 654
 655         return 0;
 656 }
 657
 658 static void omap1_clk_disable_generic(struct clk *clk)
 659 {
 660         __u16 regval16;
 661         __u32 regval32;
 662
 663         if (clk->enable_reg == NULL)
 664                 return;
 665
 666         if (clk->flags & ENABLE_REG_32BIT) {
 667                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 668                         regval32 = __raw_readl(clk->enable_reg);
 669                         regval32 &= ~(1 << clk->enable_bit);
 670                         __raw_writel(regval32, clk->enable_reg);
 671                 } else {
 672                         regval32 = omap_readl(clk->enable_reg);
 673                         regval32 &= ~(1 << clk->enable_bit);
 674                         omap_writel(regval32, clk->enable_reg);
 675                 }
 676         } else {
 677                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 678                         regval16 = __raw_readw(clk->enable_reg);
 679                         regval16 &= ~(1 << clk->enable_bit);
 680                         __raw_writew(regval16, clk->enable_reg);
 681                 } else {
 682                         regval16 = omap_readw(clk->enable_reg);
 683                         regval16 &= ~(1 << clk->enable_bit);
 684                         omap_writew(regval16, clk->enable_reg);
 685                 }
 686         }
 687 }
 688
 689 static const struct clkops clkops_generic = {
 690         .enable         = &omap1_clk_enable_generic,
 691         .disable        = &omap1_clk_disable_generic,
 692 };
 693
 694 static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
 695 {
 696         if (clk->flags & RATE_FIXED)
 697                 return clk->rate;
 698
 699         if (clk->round_rate != NULL)
 700                 return clk->round_rate(clk, rate);
 701
 702         return clk->rate;
 703 }
 704
 705 static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
 706 {
 707         int  ret = -EINVAL;
 708
 709         if (clk->set_rate)
 710                 ret = clk->set_rate(clk, rate);
 711         return ret;
 712 }
 713
 714 /*-------------------------------------------------------------------------
 715  * Omap1 clock reset and init functions
 716  *-------------------------------------------------------------------------*/
 717
 718 #ifdef CONFIG_OMAP_RESET_CLOCKS
 719
 720 static void __init omap1_clk_disable_unused(struct clk *clk)
 721 {
 722         __u32 regval32;
 723
 724         /* Clocks in the DSP domain need api_ck. Just assume bootloader
 725          * has not enabled any DSP clocks */
 726         if (clk->enable_reg == DSP_IDLECT2) {
 727                 printk(KERN_INFO "Skipping reset check for DSP domain "
 728                        "clock \"%s\"\n", clk->name);
 729                 return;
 730         }
 731
 732         /* Is the clock already disabled? */
 733         if (clk->flags & ENABLE_REG_32BIT) {
 734                 if (clk->flags & VIRTUAL_IO_ADDRESS)
 735                         regval32 = __raw_readl(clk->enable_reg);
 736                         else
 737                                 regval32 = omap_readl(clk->enable_reg);
 738         } else {
 739                 if (clk->flags & VIRTUAL_IO_ADDRESS)
 740                         regval32 = __raw_readw(clk->enable_reg);
 741                 else
 742                         regval32 = omap_readw(clk->enable_reg);
 743         }
 744
 745         if ((regval32 & (1 << clk->enable_bit)) == 0)
 746                 return;
 747
 748         /* FIXME: This clock seems to be necessary but no-one
 749          * has asked for its activation. */
 750         if (clk == &tc2_ck              /* FIX: pm.c (SRAM), CCP, Camera */
 751             || clk == &ck_dpll1out.clk  /* FIX: SoSSI, SSR */
 752             || clk == &arm_gpio_ck      /* FIX: GPIO code for 1510 */
 753                 ) {
 754                 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
 755                        clk->name);
 756                 return;
 757         }
 758
 759         printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
 760         clk->ops->disable(clk);
 761         printk(" done\n");
 762 }
 763
 764 #else
 765 #define omap1_clk_disable_unused        NULL
 766 #endif
 767
 768 static struct clk_functions omap1_clk_functions = {
 769         .clk_enable             = omap1_clk_enable,
 770         .clk_disable            = omap1_clk_disable,
 771         .clk_round_rate         = omap1_clk_round_rate,
 772         .clk_set_rate           = omap1_clk_set_rate,
 773         .clk_disable_unused     = omap1_clk_disable_unused,
 774 };
 775
 776 int __init omap1_clk_init(void)
 777 {
 778         struct omap_clk *c;
 779         const struct omap_clock_config *info;
 780         int crystal_type = 0; /* Default 12 MHz */
 781         u32 reg, cpu_mask;
 782
 783 #ifdef CONFIG_DEBUG_LL
 784         /* Resets some clocks that may be left on from bootloader,
 785          * but leaves serial clocks on.
 786          */
 787         omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
 788 #endif
 789
 790         /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
 791         reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
 792         omap_writew(reg, SOFT_REQ_REG);
 793         if (!cpu_is_omap15xx())
 794                 omap_writew(0, SOFT_REQ_REG2);
 795
 796         clk_init(&omap1_clk_functions);
 797
 798         /* By default all idlect1 clocks are allowed to idle */
 799         arm_idlect1_mask = ~0;
 800
 801         cpu_mask = 0;
 802         if (cpu_is_omap16xx())
 803                 cpu_mask |= CK_16XX;
 804         if (cpu_is_omap1510())
 805                 cpu_mask |= CK_1510;
 806         if (cpu_is_omap730())
 807                 cpu_mask |= CK_730;
 808         if (cpu_is_omap310())
 809                 cpu_mask |= CK_310;
 810
 811         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 812                 if (c->cpu & cpu_mask) {
 813                         clkdev_add(&c->lk);
 814                         clk_register(c->lk.clk);
 815                 }
 816
 817         info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
 818         if (info != NULL) {
 819                 if (!cpu_is_omap15xx())
 820                         crystal_type = info->system_clock_type;
 821         }
 822
 823 #if defined(CONFIG_ARCH_OMAP730)
 824         ck_ref.rate = 13000000;
 825 #elif defined(CONFIG_ARCH_OMAP16XX)
 826         if (crystal_type == 2)
 827                 ck_ref.rate = 19200000;
 828 #endif
 829
 830         printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
 831                omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
 832                omap_readw(ARM_CKCTL));
 833
 834         /* We want to be in syncronous scalable mode */
 835         omap_writew(0x1000, ARM_SYSST);
 836
 837 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
 838         /* Use values set by bootloader. Determine PLL rate and recalculate
 839          * dependent clocks as if kernel had changed PLL or divisors.
 840          */
 841         {
 842                 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
 843
 844                 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
 845                 if (pll_ctl_val & 0x10) {
 846                         /* PLL enabled, apply multiplier and divisor */
 847                         if (pll_ctl_val & 0xf80)
 848                                 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
 849                         ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
 850                 } else {
 851                         /* PLL disabled, apply bypass divisor */
 852                         switch (pll_ctl_val & 0xc) {
 853                         case 0:
 854                                 break;
 855                         case 0x4:
 856                                 ck_dpll1.rate /= 2;
 857                                 break;
 858                         default:
 859                                 ck_dpll1.rate /= 4;
 860                                 break;
 861                         }
 862                 }
 863         }
 864 #else
 865         /* Find the highest supported frequency and enable it */
 866         if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
 867                 printk(KERN_ERR "System frequencies not set. Check your config.\n");
 868                 /* Guess sane values (60MHz) */
 869                 omap_writew(0x2290, DPLL_CTL);
 870                 omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
 871                 ck_dpll1.rate = 60000000;
 872         }
 873 #endif
 874         propagate_rate(&ck_dpll1);
 875         /* Cache rates for clocks connected to ck_ref (not dpll1) */
 876         propagate_rate(&ck_ref);
 877         printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
 878                 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
 879                ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
 880                ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
 881                arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 882
 883 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
 884         /* Select slicer output as OMAP input clock */
 885         omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
 886 #endif
 887
 888         /* Amstrad Delta wants BCLK high when inactive */
 889         if (machine_is_ams_delta())
 890                 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
 891                                 (1 << SDW_MCLK_INV_BIT),
 892                                 ULPD_CLOCK_CTRL);
 893
 894         /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
 895         /* (on 730, bit 13 must not be cleared) */
 896         if (cpu_is_omap730())
 897                 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
 898         else
 899                 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
 900
 901         /* Put DSP/MPUI into reset until needed */
 902         omap_writew(0, ARM_RSTCT1);
 903         omap_writew(1, ARM_RSTCT2);
 904         omap_writew(0x400, ARM_IDLECT1);
 905
 906         /*
 907          * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
 908          * of the ARM_IDLECT2 register must be set to zero. The power-on
 909          * default value of this bit is one.
 910          */
 911         omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
 912
 913         /*
 914          * Only enable those clocks we will need, let the drivers
 915          * enable other clocks as necessary
 916          */
 917         clk_enable(&armper_ck.clk);
 918         clk_enable(&armxor_ck.clk);
 919         clk_enable(&armtim_ck.clk); /* This should be done by timer code */
 920
 921         if (cpu_is_omap15xx())
 922                 clk_enable(&arm_gpio_ck);
 923
 924         return 0;
 925 }