arch/arm/mach-omap2/cclock3xxx_data.c

   1 /*
   2  * OMAP3 clock data
   3  *
   4  * Copyright (C) 2007-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2011 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * Updated to COMMON clk data format by Rajendra Nayak <rnayak@ti.com>
   9  * With many device clock fixes by Kevin Hilman and Jouni Högander
  10  * DPLL bypass clock support added by Roman Tereshonkov
  11  *
  12  */
  13
  14 /*
  15  * Virtual clocks are introduced as convenient tools.
  16  * They are sources for other clocks and not supposed
  17  * to be requested from drivers directly.
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/clk.h>
  22 #include <linux/clk-private.h>
  23 #include <linux/list.h>
  24 #include <linux/io.h>
  25
  26 #include "soc.h"
  27 #include "iomap.h"
  28 #include "clock.h"
  29 #include "clock3xxx.h"
  30 #include "clock34xx.h"
  31 #include "clock36xx.h"
  32 #include "clock3517.h"
  33 #include "cm3xxx.h"
  34 #include "cm-regbits-34xx.h"
  35 #include "prm3xxx.h"
  36 #include "prm-regbits-34xx.h"
  37 #include "control.h"
  38
  39 /*
  40  * clocks
  41  */
  42
  43 #define OMAP_CM_REGADDR         OMAP34XX_CM_REGADDR
  44
  45 /* Maximum DPLL multiplier, divider values for OMAP3 */
  46 #define OMAP3_MAX_DPLL_MULT             2047
  47 #define OMAP3630_MAX_JTYPE_DPLL_MULT    4095
  48 #define OMAP3_MAX_DPLL_DIV              128
  49
  50 DEFINE_CLK_FIXED_RATE(dummy_apb_pclk, CLK_IS_ROOT, 0x0, 0x0);
  51
  52 DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
  53
  54 DEFINE_CLK_FIXED_RATE(omap_32k_fck, CLK_IS_ROOT, 32768, 0x0);
  55
  56 DEFINE_CLK_FIXED_RATE(pclk_ck, CLK_IS_ROOT, 27000000, 0x0);
  57
  58 DEFINE_CLK_FIXED_RATE(rmii_ck, CLK_IS_ROOT, 50000000, 0x0);
  59
  60 DEFINE_CLK_FIXED_RATE(secure_32k_fck, CLK_IS_ROOT, 32768, 0x0);
  61
  62 DEFINE_CLK_FIXED_RATE(sys_altclk, CLK_IS_ROOT, 0x0, 0x0);
  63
  64 DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0);
  65
  66 DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0);
  67
  68 DEFINE_CLK_FIXED_RATE(virt_16_8m_ck, CLK_IS_ROOT, 16800000, 0x0);
  69
  70 DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
  71
  72 DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
  73
  74 DEFINE_CLK_FIXED_RATE(virt_38_4m_ck, CLK_IS_ROOT, 38400000, 0x0);
  75
  76 static const char *osc_sys_ck_parent_names[] = {
  77         "virt_12m_ck", "virt_13m_ck", "virt_19200000_ck", "virt_26000000_ck",
  78         "virt_38_4m_ck", "virt_16_8m_ck",
  79 };
  80
  81 DEFINE_CLK_MUX(osc_sys_ck, osc_sys_ck_parent_names, NULL, 0x0,
  82                OMAP3430_PRM_CLKSEL, OMAP3430_SYS_CLKIN_SEL_SHIFT,
  83                OMAP3430_SYS_CLKIN_SEL_WIDTH, 0x0, NULL);
  84
  85 DEFINE_CLK_DIVIDER(sys_ck, "osc_sys_ck", &osc_sys_ck, 0x0,
  86                    OMAP3430_PRM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
  87                    OMAP_SYSCLKDIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
  88
  89 static struct dpll_data dpll3_dd = {
  90         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  91         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
  92         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
  93         .clk_bypass     = &sys_ck,
  94         .clk_ref        = &sys_ck,
  95         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
  96         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  97         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
  98         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
  99         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 100         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 101         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 102         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 103         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 104         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 105         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 106         .min_divider    = 1,
 107         .max_divider    = OMAP3_MAX_DPLL_DIV,
 108 };
 109
 110 static struct clk dpll3_ck;
 111
 112 static const char *dpll3_ck_parent_names[] = {
 113         "sys_ck",
 114 };
 115
 116 static const struct clk_ops dpll3_ck_ops = {
 117         .init           = &omap2_init_clk_clkdm,
 118         .get_parent     = &omap2_init_dpll_parent,
 119         .recalc_rate    = &omap3_dpll_recalc,
 120         .round_rate     = &omap2_dpll_round_rate,
 121 };
 122
 123 static struct clk_hw_omap dpll3_ck_hw = {
 124         .hw = {
 125                 .clk = &dpll3_ck,
 126         },
 127         .ops            = &clkhwops_omap3_dpll,
 128         .dpll_data      = &dpll3_dd,
 129         .clkdm_name     = "dpll3_clkdm",
 130 };
 131
 132 DEFINE_STRUCT_CLK(dpll3_ck, dpll3_ck_parent_names, dpll3_ck_ops);
 133
 134 DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck, 0x0,
 135                    OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 136                    OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT,
 137                    OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH,
 138                    CLK_DIVIDER_ONE_BASED, NULL);
 139
 140 static struct clk core_ck;
 141
 142 static const char *core_ck_parent_names[] = {
 143         "dpll3_m2_ck",
 144 };
 145
 146 static const struct clk_ops core_ck_ops = {};
 147
 148 DEFINE_STRUCT_CLK_HW_OMAP(core_ck, NULL);
 149 DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
 150
 151 DEFINE_CLK_DIVIDER(l3_ick, "core_ck", &core_ck, 0x0,
 152                    OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 153                    OMAP3430_CLKSEL_L3_SHIFT, OMAP3430_CLKSEL_L3_WIDTH,
 154                    CLK_DIVIDER_ONE_BASED, NULL);
 155
 156 DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick, 0x0,
 157                    OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 158                    OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH,
 159                    CLK_DIVIDER_ONE_BASED, NULL);
 160
 161 static struct clk security_l4_ick2;
 162
 163 static const char *security_l4_ick2_parent_names[] = {
 164         "l4_ick",
 165 };
 166
 167 DEFINE_STRUCT_CLK_HW_OMAP(security_l4_ick2, NULL);
 168 DEFINE_STRUCT_CLK(security_l4_ick2, security_l4_ick2_parent_names, core_ck_ops);
 169
 170 static struct clk aes1_ick;
 171
 172 static const char *aes1_ick_parent_names[] = {
 173         "security_l4_ick2",
 174 };
 175
 176 static const struct clk_ops aes1_ick_ops = {
 177         .enable         = &omap2_dflt_clk_enable,
 178         .disable        = &omap2_dflt_clk_disable,
 179         .is_enabled     = &omap2_dflt_clk_is_enabled,
 180 };
 181
 182 static struct clk_hw_omap aes1_ick_hw = {
 183         .hw = {
 184                 .clk = &aes1_ick,
 185         },
 186         .ops            = &clkhwops_iclk_wait,
 187         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 188         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
 189 };
 190
 191 DEFINE_STRUCT_CLK(aes1_ick, aes1_ick_parent_names, aes1_ick_ops);
 192
 193 static struct clk core_l4_ick;
 194
 195 static const struct clk_ops core_l4_ick_ops = {
 196         .init           = &omap2_init_clk_clkdm,
 197 };
 198
 199 DEFINE_STRUCT_CLK_HW_OMAP(core_l4_ick, "core_l4_clkdm");
 200 DEFINE_STRUCT_CLK(core_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
 201
 202 static struct clk aes2_ick;
 203
 204 static const char *aes2_ick_parent_names[] = {
 205         "core_l4_ick",
 206 };
 207
 208 static const struct clk_ops aes2_ick_ops = {
 209         .init           = &omap2_init_clk_clkdm,
 210         .enable         = &omap2_dflt_clk_enable,
 211         .disable        = &omap2_dflt_clk_disable,
 212         .is_enabled     = &omap2_dflt_clk_is_enabled,
 213 };
 214
 215 static struct clk_hw_omap aes2_ick_hw = {
 216         .hw = {
 217                 .clk = &aes2_ick,
 218         },
 219         .ops            = &clkhwops_iclk_wait,
 220         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 221         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
 222         .clkdm_name     = "core_l4_clkdm",
 223 };
 224
 225 DEFINE_STRUCT_CLK(aes2_ick, aes2_ick_parent_names, aes2_ick_ops);
 226
 227 static struct clk dpll1_fck;
 228
 229 static struct dpll_data dpll1_dd = {
 230         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 231         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 232         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 233         .clk_bypass     = &dpll1_fck,
 234         .clk_ref        = &sys_ck,
 235         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 236         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 237         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 238         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 239         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 240         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 241         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 242         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 243         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 244         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 245         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 246         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 247         .min_divider    = 1,
 248         .max_divider    = OMAP3_MAX_DPLL_DIV,
 249 };
 250
 251 static struct clk dpll1_ck;
 252
 253 static const struct clk_ops dpll1_ck_ops = {
 254         .init           = &omap2_init_clk_clkdm,
 255         .enable         = &omap3_noncore_dpll_enable,
 256         .disable        = &omap3_noncore_dpll_disable,
 257         .get_parent     = &omap2_init_dpll_parent,
 258         .recalc_rate    = &omap3_dpll_recalc,
 259         .set_rate       = &omap3_noncore_dpll_set_rate,
 260         .set_parent     = &omap3_noncore_dpll_set_parent,
 261         .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
 262         .determine_rate = &omap3_noncore_dpll_determine_rate,
 263         .round_rate     = &omap2_dpll_round_rate,
 264 };
 265
 266 static struct clk_hw_omap dpll1_ck_hw = {
 267         .hw = {
 268                 .clk = &dpll1_ck,
 269         },
 270         .ops            = &clkhwops_omap3_dpll,
 271         .dpll_data      = &dpll1_dd,
 272         .clkdm_name     = "dpll1_clkdm",
 273 };
 274
 275 DEFINE_STRUCT_CLK(dpll1_ck, dpll3_ck_parent_names, dpll1_ck_ops);
 276
 277 DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck, "dpll1_ck", &dpll1_ck, 0x0, 2, 1);
 278
 279 DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck, 0x0,
 280                    OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 281                    OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT,
 282                    OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH,
 283                    CLK_DIVIDER_ONE_BASED, NULL);
 284
 285 static struct clk mpu_ck;
 286
 287 static const char *mpu_ck_parent_names[] = {
 288         "dpll1_x2m2_ck",
 289 };
 290
 291 DEFINE_STRUCT_CLK_HW_OMAP(mpu_ck, "mpu_clkdm");
 292 DEFINE_STRUCT_CLK(mpu_ck, mpu_ck_parent_names, core_l4_ick_ops);
 293
 294 DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck, 0x0,
 295                    OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 296                    OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH,
 297                    0x0, NULL);
 298
 299 static struct clk cam_ick;
 300
 301 static struct clk_hw_omap cam_ick_hw = {
 302         .hw = {
 303                 .clk = &cam_ick,
 304         },
 305         .ops            = &clkhwops_iclk,
 306         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
 307         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
 308         .clkdm_name     = "cam_clkdm",
 309 };
 310
 311 DEFINE_STRUCT_CLK(cam_ick, security_l4_ick2_parent_names, aes2_ick_ops);
 312
 313 /* DPLL4 */
 314 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 315 /* Type: DPLL */
 316 static struct dpll_data dpll4_dd;
 317
 318 static struct dpll_data dpll4_dd_34xx __initdata = {
 319         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 320         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 321         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 322         .clk_bypass     = &sys_ck,
 323         .clk_ref        = &sys_ck,
 324         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 325         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 326         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 327         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 328         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 329         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 330         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 331         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 332         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 333         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 334         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 335         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 336         .min_divider    = 1,
 337         .max_divider    = OMAP3_MAX_DPLL_DIV,
 338 };
 339
 340 static struct dpll_data dpll4_dd_3630 __initdata = {
 341         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 342         .mult_mask      = OMAP3630_PERIPH_DPLL_MULT_MASK,
 343         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 344         .clk_bypass     = &sys_ck,
 345         .clk_ref        = &sys_ck,
 346         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 347         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 348         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 349         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 350         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 351         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 352         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 353         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 354         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 355         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 356         .dco_mask       = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
 357         .sddiv_mask     = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
 358         .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
 359         .min_divider    = 1,
 360         .max_divider    = OMAP3_MAX_DPLL_DIV,
 361         .flags          = DPLL_J_TYPE
 362 };
 363
 364 static struct clk dpll4_ck;
 365
 366 static const struct clk_ops dpll4_ck_ops = {
 367         .init           = &omap2_init_clk_clkdm,
 368         .enable         = &omap3_noncore_dpll_enable,
 369         .disable        = &omap3_noncore_dpll_disable,
 370         .get_parent     = &omap2_init_dpll_parent,
 371         .recalc_rate    = &omap3_dpll_recalc,
 372         .set_rate       = &omap3_dpll4_set_rate,
 373         .set_parent     = &omap3_noncore_dpll_set_parent,
 374         .set_rate_and_parent    = &omap3_dpll4_set_rate_and_parent,
 375         .determine_rate = &omap3_noncore_dpll_determine_rate,
 376         .round_rate     = &omap2_dpll_round_rate,
 377 };
 378
 379 static struct clk_hw_omap dpll4_ck_hw = {
 380         .hw = {
 381                 .clk = &dpll4_ck,
 382         },
 383         .dpll_data      = &dpll4_dd,
 384         .ops            = &clkhwops_omap3_dpll,
 385         .clkdm_name     = "dpll4_clkdm",
 386 };
 387
 388 DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops);
 389
 390 static const struct clk_div_table dpll4_mx_ck_div_table[] = {
 391         { .div = 1, .val = 1 },
 392         { .div = 2, .val = 2 },
 393         { .div = 3, .val = 3 },
 394         { .div = 4, .val = 4 },
 395         { .div = 5, .val = 5 },
 396         { .div = 6, .val = 6 },
 397         { .div = 7, .val = 7 },
 398         { .div = 8, .val = 8 },
 399         { .div = 9, .val = 9 },
 400         { .div = 10, .val = 10 },
 401         { .div = 11, .val = 11 },
 402         { .div = 12, .val = 12 },
 403         { .div = 13, .val = 13 },
 404         { .div = 14, .val = 14 },
 405         { .div = 15, .val = 15 },
 406         { .div = 16, .val = 16 },
 407         { .div = 17, .val = 17 },
 408         { .div = 18, .val = 18 },
 409         { .div = 19, .val = 19 },
 410         { .div = 20, .val = 20 },
 411         { .div = 21, .val = 21 },
 412         { .div = 22, .val = 22 },
 413         { .div = 23, .val = 23 },
 414         { .div = 24, .val = 24 },
 415         { .div = 25, .val = 25 },
 416         { .div = 26, .val = 26 },
 417         { .div = 27, .val = 27 },
 418         { .div = 28, .val = 28 },
 419         { .div = 29, .val = 29 },
 420         { .div = 30, .val = 30 },
 421         { .div = 31, .val = 31 },
 422         { .div = 32, .val = 32 },
 423         { .div = 0 },
 424 };
 425
 426 DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0,
 427                    OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 428                    OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH,
 429                    CLK_DIVIDER_ONE_BASED, NULL);
 430
 431 static struct clk dpll4_m5x2_ck;
 432
 433 static const char *dpll4_m5x2_ck_parent_names[] = {
 434         "dpll4_m5_ck",
 435 };
 436
 437 static const struct clk_ops dpll4_m5x2_ck_ops = {
 438         .init           = &omap2_init_clk_clkdm,
 439         .enable         = &omap2_dflt_clk_enable,
 440         .disable        = &omap2_dflt_clk_disable,
 441         .is_enabled     = &omap2_dflt_clk_is_enabled,
 442         .set_rate       = &omap3_clkoutx2_set_rate,
 443         .recalc_rate    = &omap3_clkoutx2_recalc,
 444         .round_rate     = &omap3_clkoutx2_round_rate,
 445 };
 446
 447 static const struct clk_ops dpll4_m5x2_ck_3630_ops = {
 448         .init           = &omap2_init_clk_clkdm,
 449         .enable         = &omap36xx_pwrdn_clk_enable_with_hsdiv_restore,
 450         .disable        = &omap2_dflt_clk_disable,
 451         .recalc_rate    = &omap3_clkoutx2_recalc,
 452 };
 453
 454 static struct clk_hw_omap dpll4_m5x2_ck_hw = {
 455         .hw = {
 456                 .clk = &dpll4_m5x2_ck,
 457         },
 458         .ops            = &clkhwops_wait,
 459         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 460         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 461         .flags          = INVERT_ENABLE,
 462         .clkdm_name     = "dpll4_clkdm",
 463 };
 464
 465 DEFINE_STRUCT_CLK_FLAGS(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names,
 466                         dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);
 467
 468 static struct clk dpll4_m5x2_ck_3630 = {
 469         .name           = "dpll4_m5x2_ck",
 470         .hw             = &dpll4_m5x2_ck_hw.hw,
 471         .parent_names   = dpll4_m5x2_ck_parent_names,
 472         .num_parents    = ARRAY_SIZE(dpll4_m5x2_ck_parent_names),
 473         .ops            = &dpll4_m5x2_ck_3630_ops,
 474         .flags          = CLK_SET_RATE_PARENT,
 475 };
 476
 477 static struct clk cam_mclk;
 478
 479 static const char *cam_mclk_parent_names[] = {
 480         "dpll4_m5x2_ck",
 481 };
 482
 483 static struct clk_hw_omap cam_mclk_hw = {
 484         .hw = {
 485                 .clk = &cam_mclk,
 486         },
 487         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
 488         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
 489         .clkdm_name     = "cam_clkdm",
 490 };
 491
 492 static struct clk cam_mclk = {
 493         .name           = "cam_mclk",
 494         .hw             = &cam_mclk_hw.hw,
 495         .parent_names   = cam_mclk_parent_names,
 496         .num_parents    = ARRAY_SIZE(cam_mclk_parent_names),
 497         .ops            = &aes2_ick_ops,
 498         .flags          = CLK_SET_RATE_PARENT,
 499 };
 500
 501 static const struct clksel_rate clkout2_src_core_rates[] = {
 502         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 503         { .div = 0 }
 504 };
 505
 506 static const struct clksel_rate clkout2_src_sys_rates[] = {
 507         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 508         { .div = 0 }
 509 };
 510
 511 static const struct clksel_rate clkout2_src_96m_rates[] = {
 512         { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
 513         { .div = 0 }
 514 };
 515
 516 DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck, 0x0,
 517                    OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 518                    OMAP3430_DIV_96M_SHIFT, OMAP3630_DIV_96M_WIDTH,
 519                    CLK_DIVIDER_ONE_BASED, NULL);
 520
 521 static struct clk dpll4_m2x2_ck;
 522
 523 static const char *dpll4_m2x2_ck_parent_names[] = {
 524         "dpll4_m2_ck",
 525 };
 526
 527 static struct clk_hw_omap dpll4_m2x2_ck_hw = {
 528         .hw = {
 529                 .clk = &dpll4_m2x2_ck,
 530         },
 531         .ops            = &clkhwops_wait,
 532         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 533         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 534         .flags          = INVERT_ENABLE,
 535         .clkdm_name     = "dpll4_clkdm",
 536 };
 537
 538 DEFINE_STRUCT_CLK(dpll4_m2x2_ck, dpll4_m2x2_ck_parent_names, dpll4_m5x2_ck_ops);
 539
 540 static struct clk dpll4_m2x2_ck_3630 = {
 541         .name           = "dpll4_m2x2_ck",
 542         .hw             = &dpll4_m2x2_ck_hw.hw,
 543         .parent_names   = dpll4_m2x2_ck_parent_names,
 544         .num_parents    = ARRAY_SIZE(dpll4_m2x2_ck_parent_names),
 545         .ops            = &dpll4_m5x2_ck_3630_ops,
 546 };
 547
 548 static struct clk omap_96m_alwon_fck;
 549
 550 static const char *omap_96m_alwon_fck_parent_names[] = {
 551         "dpll4_m2x2_ck",
 552 };
 553
 554 DEFINE_STRUCT_CLK_HW_OMAP(omap_96m_alwon_fck, NULL);
 555 DEFINE_STRUCT_CLK(omap_96m_alwon_fck, omap_96m_alwon_fck_parent_names,
 556                   core_ck_ops);
 557
 558 static struct clk cm_96m_fck;
 559
 560 static const char *cm_96m_fck_parent_names[] = {
 561         "omap_96m_alwon_fck",
 562 };
 563
 564 DEFINE_STRUCT_CLK_HW_OMAP(cm_96m_fck, NULL);
 565 DEFINE_STRUCT_CLK(cm_96m_fck, cm_96m_fck_parent_names, core_ck_ops);
 566
 567 static const struct clksel_rate clkout2_src_54m_rates[] = {
 568         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
 569         { .div = 0 }
 570 };
 571
 572 DEFINE_CLK_DIVIDER_TABLE(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0,
 573                    OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 574                    OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH,
 575                    0, dpll4_mx_ck_div_table, NULL);
 576
 577 static struct clk dpll4_m3x2_ck;
 578
 579 static const char *dpll4_m3x2_ck_parent_names[] = {
 580         "dpll4_m3_ck",
 581 };
 582
 583 static struct clk_hw_omap dpll4_m3x2_ck_hw = {
 584         .hw = {
 585                 .clk = &dpll4_m3x2_ck,
 586         },
 587         .ops            = &clkhwops_wait,
 588         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 589         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 590         .flags          = INVERT_ENABLE,
 591         .clkdm_name     = "dpll4_clkdm",
 592 };
 593
 594 DEFINE_STRUCT_CLK(dpll4_m3x2_ck, dpll4_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
 595
 596 static struct clk dpll4_m3x2_ck_3630 = {
 597         .name           = "dpll4_m3x2_ck",
 598         .hw             = &dpll4_m3x2_ck_hw.hw,
 599         .parent_names   = dpll4_m3x2_ck_parent_names,
 600         .num_parents    = ARRAY_SIZE(dpll4_m3x2_ck_parent_names),
 601         .ops            = &dpll4_m5x2_ck_3630_ops,
 602 };
 603
 604 static const char *omap_54m_fck_parent_names[] = {
 605         "dpll4_m3x2_ck", "sys_altclk",
 606 };
 607
 608 DEFINE_CLK_MUX(omap_54m_fck, omap_54m_fck_parent_names, NULL, 0x0,
 609                OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP3430_SOURCE_54M_SHIFT,
 610                OMAP3430_SOURCE_54M_WIDTH, 0x0, NULL);
 611
 612 static const struct clksel clkout2_src_clksel[] = {
 613         { .parent = &core_ck, .rates = clkout2_src_core_rates },
 614         { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
 615         { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
 616         { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
 617         { .parent = NULL },
 618 };
 619
 620 static const char *clkout2_src_ck_parent_names[] = {
 621         "core_ck", "sys_ck", "cm_96m_fck", "omap_54m_fck",
 622 };
 623
 624 static const struct clk_ops clkout2_src_ck_ops = {
 625         .init           = &omap2_init_clk_clkdm,
 626         .enable         = &omap2_dflt_clk_enable,
 627         .disable        = &omap2_dflt_clk_disable,
 628         .is_enabled     = &omap2_dflt_clk_is_enabled,
 629         .recalc_rate    = &omap2_clksel_recalc,
 630         .get_parent     = &omap2_clksel_find_parent_index,
 631         .set_parent     = &omap2_clksel_set_parent,
 632 };
 633
 634 DEFINE_CLK_OMAP_MUX_GATE(clkout2_src_ck, "core_clkdm",
 635                          clkout2_src_clksel, OMAP3430_CM_CLKOUT_CTRL,
 636                          OMAP3430_CLKOUT2SOURCE_MASK,
 637                          OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_EN_SHIFT,
 638                          NULL, clkout2_src_ck_parent_names, clkout2_src_ck_ops);
 639
 640 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 641         { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
 642         { .div = 0 }
 643 };
 644
 645 static const struct clksel_rate omap_48m_alt_rates[] = {
 646         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 647         { .div = 0 }
 648 };
 649
 650 static const struct clksel omap_48m_clksel[] = {
 651         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 652         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 653         { .parent = NULL },
 654 };
 655
 656 static const char *omap_48m_fck_parent_names[] = {
 657         "cm_96m_fck", "sys_altclk",
 658 };
 659
 660 static struct clk omap_48m_fck;
 661
 662 static const struct clk_ops omap_48m_fck_ops = {
 663         .recalc_rate    = &omap2_clksel_recalc,
 664         .get_parent     = &omap2_clksel_find_parent_index,
 665         .set_parent     = &omap2_clksel_set_parent,
 666 };
 667
 668 static struct clk_hw_omap omap_48m_fck_hw = {
 669         .hw = {
 670                 .clk = &omap_48m_fck,
 671         },
 672         .clksel         = omap_48m_clksel,
 673         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 674         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 675 };
 676
 677 DEFINE_STRUCT_CLK(omap_48m_fck, omap_48m_fck_parent_names, omap_48m_fck_ops);
 678
 679 DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck, 0x0, 1, 4);
 680
 681 static struct clk core_12m_fck;
 682
 683 static const char *core_12m_fck_parent_names[] = {
 684         "omap_12m_fck",
 685 };
 686
 687 DEFINE_STRUCT_CLK_HW_OMAP(core_12m_fck, "core_l4_clkdm");
 688 DEFINE_STRUCT_CLK(core_12m_fck, core_12m_fck_parent_names, core_l4_ick_ops);
 689
 690 static struct clk core_48m_fck;
 691
 692 static const char *core_48m_fck_parent_names[] = {
 693         "omap_48m_fck",
 694 };
 695
 696 DEFINE_STRUCT_CLK_HW_OMAP(core_48m_fck, "core_l4_clkdm");
 697 DEFINE_STRUCT_CLK(core_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
 698
 699 static const char *omap_96m_fck_parent_names[] = {
 700         "cm_96m_fck", "sys_ck",
 701 };
 702
 703 DEFINE_CLK_MUX(omap_96m_fck, omap_96m_fck_parent_names, NULL, 0x0,
 704                OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 705                OMAP3430_SOURCE_96M_SHIFT, OMAP3430_SOURCE_96M_WIDTH, 0x0, NULL);
 706
 707 static struct clk core_96m_fck;
 708
 709 static const char *core_96m_fck_parent_names[] = {
 710         "omap_96m_fck",
 711 };
 712
 713 DEFINE_STRUCT_CLK_HW_OMAP(core_96m_fck, "core_l4_clkdm");
 714 DEFINE_STRUCT_CLK(core_96m_fck, core_96m_fck_parent_names, core_l4_ick_ops);
 715
 716 static struct clk core_l3_ick;
 717
 718 static const char *core_l3_ick_parent_names[] = {
 719         "l3_ick",
 720 };
 721
 722 DEFINE_STRUCT_CLK_HW_OMAP(core_l3_ick, "core_l3_clkdm");
 723 DEFINE_STRUCT_CLK(core_l3_ick, core_l3_ick_parent_names, core_l4_ick_ops);
 724
 725 DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck, 0x0, 2, 1);
 726
 727 static struct clk corex2_fck;
 728
 729 static const char *corex2_fck_parent_names[] = {
 730         "dpll3_m2x2_ck",
 731 };
 732
 733 DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL);
 734 DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops);
 735
 736 static struct clk cpefuse_fck;
 737
 738 static struct clk_hw_omap cpefuse_fck_hw = {
 739         .hw = {
 740                 .clk = &cpefuse_fck,
 741         },
 742         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
 743         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
 744         .clkdm_name     = "core_l4_clkdm",
 745 };
 746
 747 DEFINE_STRUCT_CLK(cpefuse_fck, dpll3_ck_parent_names, aes2_ick_ops);
 748
 749 static struct clk csi2_96m_fck;
 750
 751 static const char *csi2_96m_fck_parent_names[] = {
 752         "core_96m_fck",
 753 };
 754
 755 static struct clk_hw_omap csi2_96m_fck_hw = {
 756         .hw = {
 757                 .clk = &csi2_96m_fck,
 758         },
 759         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
 760         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
 761         .clkdm_name     = "cam_clkdm",
 762 };
 763
 764 DEFINE_STRUCT_CLK(csi2_96m_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
 765
 766 static struct clk d2d_26m_fck;
 767
 768 static struct clk_hw_omap d2d_26m_fck_hw = {
 769         .hw = {
 770                 .clk = &d2d_26m_fck,
 771         },
 772         .ops            = &clkhwops_wait,
 773         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 774         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
 775         .clkdm_name     = "d2d_clkdm",
 776 };
 777
 778 DEFINE_STRUCT_CLK(d2d_26m_fck, dpll3_ck_parent_names, aes2_ick_ops);
 779
 780 static struct clk des1_ick;
 781
 782 static struct clk_hw_omap des1_ick_hw = {
 783         .hw = {
 784                 .clk = &des1_ick,
 785         },
 786         .ops            = &clkhwops_iclk_wait,
 787         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 788         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
 789 };
 790
 791 DEFINE_STRUCT_CLK(des1_ick, aes1_ick_parent_names, aes1_ick_ops);
 792
 793 static struct clk des2_ick;
 794
 795 static struct clk_hw_omap des2_ick_hw = {
 796         .hw = {
 797                 .clk = &des2_ick,
 798         },
 799         .ops            = &clkhwops_iclk_wait,
 800         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 801         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
 802         .clkdm_name     = "core_l4_clkdm",
 803 };
 804
 805 DEFINE_STRUCT_CLK(des2_ick, aes2_ick_parent_names, aes2_ick_ops);
 806
 807 DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck, 0x0,
 808                    OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 809                    OMAP3430_MPU_CLK_SRC_SHIFT, OMAP3430_MPU_CLK_SRC_WIDTH,
 810                    CLK_DIVIDER_ONE_BASED, NULL);
 811
 812 static struct clk dpll2_fck;
 813
 814 static struct dpll_data dpll2_dd = {
 815         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 816         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 817         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 818         .clk_bypass     = &dpll2_fck,
 819         .clk_ref        = &sys_ck,
 820         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 821         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 822         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 823         .modes          = ((1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 824                            (1 << DPLL_LOW_POWER_BYPASS)),
 825         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 826         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 827         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 828         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 829         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 830         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 831         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 832         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 833         .min_divider    = 1,
 834         .max_divider    = OMAP3_MAX_DPLL_DIV,
 835 };
 836
 837 static struct clk dpll2_ck;
 838
 839 static struct clk_hw_omap dpll2_ck_hw = {
 840         .hw = {
 841                 .clk = &dpll2_ck,
 842         },
 843         .ops            = &clkhwops_omap3_dpll,
 844         .dpll_data      = &dpll2_dd,
 845         .clkdm_name     = "dpll2_clkdm",
 846 };
 847
 848 DEFINE_STRUCT_CLK(dpll2_ck, dpll3_ck_parent_names, dpll1_ck_ops);
 849
 850 DEFINE_CLK_DIVIDER(dpll2_fck, "core_ck", &core_ck, 0x0,
 851                    OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 852                    OMAP3430_IVA2_CLK_SRC_SHIFT, OMAP3430_IVA2_CLK_SRC_WIDTH,
 853                    CLK_DIVIDER_ONE_BASED, NULL);
 854
 855 DEFINE_CLK_DIVIDER(dpll2_m2_ck, "dpll2_ck", &dpll2_ck, 0x0,
 856                    OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),
 857                    OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT,
 858                    OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH,
 859                    CLK_DIVIDER_ONE_BASED, NULL);
 860
 861 DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck, 0x0,
 862                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 863                    OMAP3430_DIV_DPLL3_SHIFT, OMAP3430_DIV_DPLL3_WIDTH,
 864                    CLK_DIVIDER_ONE_BASED, NULL);
 865
 866 static struct clk dpll3_m3x2_ck;
 867
 868 static const char *dpll3_m3x2_ck_parent_names[] = {
 869         "dpll3_m3_ck",
 870 };
 871
 872 static struct clk_hw_omap dpll3_m3x2_ck_hw = {
 873         .hw = {
 874                 .clk = &dpll3_m3x2_ck,
 875         },
 876         .ops            = &clkhwops_wait,
 877         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 878         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 879         .flags          = INVERT_ENABLE,
 880         .clkdm_name     = "dpll3_clkdm",
 881 };
 882
 883 DEFINE_STRUCT_CLK(dpll3_m3x2_ck, dpll3_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
 884
 885 static struct clk dpll3_m3x2_ck_3630 = {
 886         .name           = "dpll3_m3x2_ck",
 887         .hw             = &dpll3_m3x2_ck_hw.hw,
 888         .parent_names   = dpll3_m3x2_ck_parent_names,
 889         .num_parents    = ARRAY_SIZE(dpll3_m3x2_ck_parent_names),
 890         .ops            = &dpll4_m5x2_ck_3630_ops,
 891 };
 892
 893 DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck, 0x0, 2, 1);
 894
 895 DEFINE_CLK_DIVIDER_TABLE(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0,
 896                    OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 897                    OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH,
 898                    0, dpll4_mx_ck_div_table, NULL);
 899
 900 static struct clk dpll4_m4x2_ck;
 901
 902 static const char *dpll4_m4x2_ck_parent_names[] = {
 903         "dpll4_m4_ck",
 904 };
 905
 906 static struct clk_hw_omap dpll4_m4x2_ck_hw = {
 907         .hw = {
 908                 .clk = &dpll4_m4x2_ck,
 909         },
 910         .ops            = &clkhwops_wait,
 911         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 912         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 913         .flags          = INVERT_ENABLE,
 914         .clkdm_name     = "dpll4_clkdm",
 915 };
 916
 917 DEFINE_STRUCT_CLK_FLAGS(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names,
 918                 dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);
 919
 920 static struct clk dpll4_m4x2_ck_3630 = {
 921         .name           = "dpll4_m4x2_ck",
 922         .hw             = &dpll4_m4x2_ck_hw.hw,
 923         .parent_names   = dpll4_m4x2_ck_parent_names,
 924         .num_parents    = ARRAY_SIZE(dpll4_m4x2_ck_parent_names),
 925         .ops            = &dpll4_m5x2_ck_3630_ops,
 926         .flags          = CLK_SET_RATE_PARENT,
 927 };
 928
 929 DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0,
 930                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 931                    OMAP3430_DIV_DPLL4_SHIFT, OMAP3630_DIV_DPLL4_WIDTH,
 932                    CLK_DIVIDER_ONE_BASED, NULL);
 933
 934 static struct clk dpll4_m6x2_ck;
 935
 936 static const char *dpll4_m6x2_ck_parent_names[] = {
 937         "dpll4_m6_ck",
 938 };
 939
 940 static struct clk_hw_omap dpll4_m6x2_ck_hw = {
 941         .hw = {
 942                 .clk = &dpll4_m6x2_ck,
 943         },
 944         .ops            = &clkhwops_wait,
 945         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 946         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 947         .flags          = INVERT_ENABLE,
 948         .clkdm_name     = "dpll4_clkdm",
 949 };
 950
 951 DEFINE_STRUCT_CLK(dpll4_m6x2_ck, dpll4_m6x2_ck_parent_names, dpll4_m5x2_ck_ops);
 952
 953 static struct clk dpll4_m6x2_ck_3630 = {
 954         .name           = "dpll4_m6x2_ck",
 955         .hw             = &dpll4_m6x2_ck_hw.hw,
 956         .parent_names   = dpll4_m6x2_ck_parent_names,
 957         .num_parents    = ARRAY_SIZE(dpll4_m6x2_ck_parent_names),
 958         .ops            = &dpll4_m5x2_ck_3630_ops,
 959 };
 960
 961 DEFINE_CLK_FIXED_FACTOR(dpll4_x2_ck, "dpll4_ck", &dpll4_ck, 0x0, 2, 1);
 962
 963 static struct dpll_data dpll5_dd = {
 964         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 965         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 966         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 967         .clk_bypass     = &sys_ck,
 968         .clk_ref        = &sys_ck,
 969         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 970         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 971         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 972         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 973         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 974         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 975         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 976         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 977         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 978         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 979         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 980         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 981         .min_divider    = 1,
 982         .max_divider    = OMAP3_MAX_DPLL_DIV,
 983 };
 984
 985 static struct clk dpll5_ck;
 986
 987 static struct clk_hw_omap dpll5_ck_hw = {
 988         .hw = {
 989                 .clk = &dpll5_ck,
 990         },
 991         .ops            = &clkhwops_omap3_dpll,
 992         .dpll_data      = &dpll5_dd,
 993         .clkdm_name     = "dpll5_clkdm",
 994 };
 995
 996 DEFINE_STRUCT_CLK(dpll5_ck, dpll3_ck_parent_names, dpll1_ck_ops);
 997
 998 DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck, 0x0,
 999                    OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
1000                    OMAP3430ES2_DIV_120M_SHIFT, OMAP3430ES2_DIV_120M_WIDTH,
1001                    CLK_DIVIDER_ONE_BASED, NULL);
1002
1003 static struct clk dss1_alwon_fck_3430es1;
1004
1005 static const char *dss1_alwon_fck_3430es1_parent_names[] = {
1006         "dpll4_m4x2_ck",
1007 };
1008
1009 static struct clk_hw_omap dss1_alwon_fck_3430es1_hw = {
1010         .hw = {
1011                 .clk = &dss1_alwon_fck_3430es1,
1012         },
1013         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1014         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
1015         .clkdm_name     = "dss_clkdm",
1016 };
1017
1018 DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es1,
1019                 dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops,
1020                 CLK_SET_RATE_PARENT);
1021
1022 static struct clk dss1_alwon_fck_3430es2;
1023
1024 static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = {
1025         .hw = {
1026                 .clk = &dss1_alwon_fck_3430es2,
1027         },
1028         .ops            = &clkhwops_omap3430es2_dss_usbhost_wait,
1029         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1030         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
1031         .clkdm_name     = "dss_clkdm",
1032 };
1033
1034 DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es2,
1035                 dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops,
1036                 CLK_SET_RATE_PARENT);
1037
1038 static struct clk dss2_alwon_fck;
1039
1040 static struct clk_hw_omap dss2_alwon_fck_hw = {
1041         .hw = {
1042                 .clk = &dss2_alwon_fck,
1043         },
1044         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1045         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
1046         .clkdm_name     = "dss_clkdm",
1047 };
1048
1049 DEFINE_STRUCT_CLK(dss2_alwon_fck, dpll3_ck_parent_names, aes2_ick_ops);
1050
1051 static struct clk dss_96m_fck;
1052
1053 static struct clk_hw_omap dss_96m_fck_hw = {
1054         .hw = {
1055                 .clk = &dss_96m_fck,
1056         },
1057         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1058         .enable_bit     = OMAP3430_EN_TV_SHIFT,
1059         .clkdm_name     = "dss_clkdm",
1060 };
1061
1062 DEFINE_STRUCT_CLK(dss_96m_fck, core_96m_fck_parent_names, aes2_ick_ops);
1063
1064 static struct clk dss_ick_3430es1;
1065
1066 static struct clk_hw_omap dss_ick_3430es1_hw = {
1067         .hw = {
1068                 .clk = &dss_ick_3430es1,
1069         },
1070         .ops            = &clkhwops_iclk,
1071         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1072         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1073         .clkdm_name     = "dss_clkdm",
1074 };
1075
1076 DEFINE_STRUCT_CLK(dss_ick_3430es1, security_l4_ick2_parent_names, aes2_ick_ops);
1077
1078 static struct clk dss_ick_3430es2;
1079
1080 static struct clk_hw_omap dss_ick_3430es2_hw = {
1081         .hw = {
1082                 .clk = &dss_ick_3430es2,
1083         },
1084         .ops            = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
1085         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1086         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1087         .clkdm_name     = "dss_clkdm",
1088 };
1089
1090 DEFINE_STRUCT_CLK(dss_ick_3430es2, security_l4_ick2_parent_names, aes2_ick_ops);
1091
1092 static struct clk dss_tv_fck;
1093
1094 static const char *dss_tv_fck_parent_names[] = {
1095         "omap_54m_fck",
1096 };
1097
1098 static struct clk_hw_omap dss_tv_fck_hw = {
1099         .hw = {
1100                 .clk = &dss_tv_fck,
1101         },
1102         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1103         .enable_bit     = OMAP3430_EN_TV_SHIFT,
1104         .clkdm_name     = "dss_clkdm",
1105 };
1106
1107 DEFINE_STRUCT_CLK(dss_tv_fck, dss_tv_fck_parent_names, aes2_ick_ops);
1108
1109 static struct clk emac_fck;
1110
1111 static const char *emac_fck_parent_names[] = {
1112         "rmii_ck",
1113 };
1114
1115 static struct clk_hw_omap emac_fck_hw = {
1116         .hw = {
1117                 .clk = &emac_fck,
1118         },
1119         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1120         .enable_bit     = AM35XX_CPGMAC_FCLK_SHIFT,
1121 };
1122
1123 DEFINE_STRUCT_CLK(emac_fck, emac_fck_parent_names, aes1_ick_ops);
1124
1125 static struct clk ipss_ick;
1126
1127 static const char *ipss_ick_parent_names[] = {
1128         "core_l3_ick",
1129 };
1130
1131 static struct clk_hw_omap ipss_ick_hw = {
1132         .hw = {
1133                 .clk = &ipss_ick,
1134         },
1135         .ops            = &clkhwops_am35xx_ipss_wait,
1136         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1137         .enable_bit     = AM35XX_EN_IPSS_SHIFT,
1138         .clkdm_name     = "core_l3_clkdm",
1139 };
1140
1141 DEFINE_STRUCT_CLK(ipss_ick, ipss_ick_parent_names, aes2_ick_ops);
1142
1143 static struct clk emac_ick;
1144
1145 static const char *emac_ick_parent_names[] = {
1146         "ipss_ick",
1147 };
1148
1149 static struct clk_hw_omap emac_ick_hw = {
1150         .hw = {
1151                 .clk = &emac_ick,
1152         },
1153         .ops            = &clkhwops_am35xx_ipss_module_wait,
1154         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1155         .enable_bit     = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
1156         .clkdm_name     = "core_l3_clkdm",
1157 };
1158
1159 DEFINE_STRUCT_CLK(emac_ick, emac_ick_parent_names, aes2_ick_ops);
1160
1161 static struct clk emu_core_alwon_ck;
1162
1163 static const char *emu_core_alwon_ck_parent_names[] = {
1164         "dpll3_m3x2_ck",
1165 };
1166
1167 DEFINE_STRUCT_CLK_HW_OMAP(emu_core_alwon_ck, "dpll3_clkdm");
1168 DEFINE_STRUCT_CLK(emu_core_alwon_ck, emu_core_alwon_ck_parent_names,
1169                   core_l4_ick_ops);
1170
1171 static struct clk emu_mpu_alwon_ck;
1172
1173 static const char *emu_mpu_alwon_ck_parent_names[] = {
1174         "mpu_ck",
1175 };
1176
1177 DEFINE_STRUCT_CLK_HW_OMAP(emu_mpu_alwon_ck, NULL);
1178 DEFINE_STRUCT_CLK(emu_mpu_alwon_ck, emu_mpu_alwon_ck_parent_names, core_ck_ops);
1179
1180 static struct clk emu_per_alwon_ck;
1181
1182 static const char *emu_per_alwon_ck_parent_names[] = {
1183         "dpll4_m6x2_ck",
1184 };
1185
1186 DEFINE_STRUCT_CLK_HW_OMAP(emu_per_alwon_ck, "dpll4_clkdm");
1187 DEFINE_STRUCT_CLK(emu_per_alwon_ck, emu_per_alwon_ck_parent_names,
1188                   core_l4_ick_ops);
1189
1190 static const char *emu_src_ck_parent_names[] = {
1191         "sys_ck", "emu_core_alwon_ck", "emu_per_alwon_ck", "emu_mpu_alwon_ck",
1192 };
1193
1194 static const struct clksel_rate emu_src_sys_rates[] = {
1195         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1196         { .div = 0 },
1197 };
1198
1199 static const struct clksel_rate emu_src_core_rates[] = {
1200         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1201         { .div = 0 },
1202 };
1203
1204 static const struct clksel_rate emu_src_per_rates[] = {
1205         { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
1206         { .div = 0 },
1207 };
1208
1209 static const struct clksel_rate emu_src_mpu_rates[] = {
1210         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1211         { .div = 0 },
1212 };
1213
1214 static const struct clksel emu_src_clksel[] = {
1215         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
1216         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
1217         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
1218         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
1219         { .parent = NULL },
1220 };
1221
1222 static const struct clk_ops emu_src_ck_ops = {
1223         .init           = &omap2_init_clk_clkdm,
1224         .recalc_rate    = &omap2_clksel_recalc,
1225         .get_parent     = &omap2_clksel_find_parent_index,
1226         .set_parent     = &omap2_clksel_set_parent,
1227         .enable         = &omap2_clkops_enable_clkdm,
1228         .disable        = &omap2_clkops_disable_clkdm,
1229 };
1230
1231 static struct clk emu_src_ck;
1232
1233 static struct clk_hw_omap emu_src_ck_hw = {
1234         .hw = {
1235                 .clk = &emu_src_ck,
1236         },
1237         .clksel         = emu_src_clksel,
1238         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
1239         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
1240         .clkdm_name     = "emu_clkdm",
1241 };
1242
1243 DEFINE_STRUCT_CLK(emu_src_ck, emu_src_ck_parent_names, emu_src_ck_ops);
1244
1245 DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
1246                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
1247                    OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH,
1248                    CLK_DIVIDER_ONE_BASED, NULL);
1249
1250 static struct clk fac_ick;
1251
1252 static struct clk_hw_omap fac_ick_hw = {
1253         .hw = {
1254                 .clk = &fac_ick,
1255         },
1256         .ops            = &clkhwops_iclk_wait,
1257         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1258         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1259         .clkdm_name     = "core_l4_clkdm",
1260 };
1261
1262 DEFINE_STRUCT_CLK(fac_ick, aes2_ick_parent_names, aes2_ick_ops);
1263
1264 static struct clk fshostusb_fck;
1265
1266 static const char *fshostusb_fck_parent_names[] = {
1267         "core_48m_fck",
1268 };
1269
1270 static struct clk_hw_omap fshostusb_fck_hw = {
1271         .hw = {
1272                 .clk = &fshostusb_fck,
1273         },
1274         .ops            = &clkhwops_wait,
1275         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1276         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1277         .clkdm_name     = "core_l4_clkdm",
1278 };
1279
1280 DEFINE_STRUCT_CLK(fshostusb_fck, fshostusb_fck_parent_names, aes2_ick_ops);
1281
1282 static struct clk gfx_l3_ck;
1283
1284 static struct clk_hw_omap gfx_l3_ck_hw = {
1285         .hw = {
1286                 .clk = &gfx_l3_ck,
1287         },
1288         .ops            = &clkhwops_wait,
1289         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1290         .enable_bit     = OMAP_EN_GFX_SHIFT,
1291         .clkdm_name     = "gfx_3430es1_clkdm",
1292 };
1293
1294 DEFINE_STRUCT_CLK(gfx_l3_ck, core_l3_ick_parent_names, aes1_ick_ops);
1295
1296 DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick, 0x0,
1297                    OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1298                    OMAP_CLKSEL_GFX_SHIFT, OMAP_CLKSEL_GFX_WIDTH,
1299                    CLK_DIVIDER_ONE_BASED, NULL);
1300
1301 static struct clk gfx_cg1_ck;
1302
1303 static const char *gfx_cg1_ck_parent_names[] = {
1304         "gfx_l3_fck",
1305 };
1306
1307 static struct clk_hw_omap gfx_cg1_ck_hw = {
1308         .hw = {
1309                 .clk = &gfx_cg1_ck,
1310         },
1311         .ops            = &clkhwops_wait,
1312         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1313         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1314         .clkdm_name     = "gfx_3430es1_clkdm",
1315 };
1316
1317 DEFINE_STRUCT_CLK(gfx_cg1_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
1318
1319 static struct clk gfx_cg2_ck;
1320
1321 static struct clk_hw_omap gfx_cg2_ck_hw = {
1322         .hw = {
1323                 .clk = &gfx_cg2_ck,
1324         },
1325         .ops            = &clkhwops_wait,
1326         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1327         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1328         .clkdm_name     = "gfx_3430es1_clkdm",
1329 };
1330
1331 DEFINE_STRUCT_CLK(gfx_cg2_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
1332
1333 static struct clk gfx_l3_ick;
1334
1335 static const char *gfx_l3_ick_parent_names[] = {
1336         "gfx_l3_ck",
1337 };
1338
1339 DEFINE_STRUCT_CLK_HW_OMAP(gfx_l3_ick, "gfx_3430es1_clkdm");
1340 DEFINE_STRUCT_CLK(gfx_l3_ick, gfx_l3_ick_parent_names, core_l4_ick_ops);
1341
1342 static struct clk wkup_32k_fck;
1343
1344 static const char *wkup_32k_fck_parent_names[] = {
1345         "omap_32k_fck",
1346 };
1347
1348 DEFINE_STRUCT_CLK_HW_OMAP(wkup_32k_fck, "wkup_clkdm");
1349 DEFINE_STRUCT_CLK(wkup_32k_fck, wkup_32k_fck_parent_names, core_l4_ick_ops);
1350
1351 static struct clk gpio1_dbck;
1352
1353 static const char *gpio1_dbck_parent_names[] = {
1354         "wkup_32k_fck",
1355 };
1356
1357 static struct clk_hw_omap gpio1_dbck_hw = {
1358         .hw = {
1359                 .clk = &gpio1_dbck,
1360         },
1361         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1362         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
1363         .clkdm_name     = "wkup_clkdm",
1364 };
1365
1366 DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops);
1367
1368 static struct clk wkup_l4_ick;
1369
1370 DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm");
1371 DEFINE_STRUCT_CLK(wkup_l4_ick, dpll3_ck_parent_names, core_l4_ick_ops);
1372
1373 static struct clk gpio1_ick;
1374
1375 static const char *gpio1_ick_parent_names[] = {
1376         "wkup_l4_ick",
1377 };
1378
1379 static struct clk_hw_omap gpio1_ick_hw = {
1380         .hw = {
1381                 .clk = &gpio1_ick,
1382         },
1383         .ops            = &clkhwops_iclk_wait,
1384         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1385         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
1386         .clkdm_name     = "wkup_clkdm",
1387 };
1388
1389 DEFINE_STRUCT_CLK(gpio1_ick, gpio1_ick_parent_names, aes2_ick_ops);
1390
1391 static struct clk per_32k_alwon_fck;
1392
1393 DEFINE_STRUCT_CLK_HW_OMAP(per_32k_alwon_fck, "per_clkdm");
1394 DEFINE_STRUCT_CLK(per_32k_alwon_fck, wkup_32k_fck_parent_names,
1395                   core_l4_ick_ops);
1396
1397 static struct clk gpio2_dbck;
1398
1399 static const char *gpio2_dbck_parent_names[] = {
1400         "per_32k_alwon_fck",
1401 };
1402
1403 static struct clk_hw_omap gpio2_dbck_hw = {
1404         .hw = {
1405                 .clk = &gpio2_dbck,
1406         },
1407         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1408         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
1409         .clkdm_name     = "per_clkdm",
1410 };
1411
1412 DEFINE_STRUCT_CLK(gpio2_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1413
1414 static struct clk per_l4_ick;
1415
1416 DEFINE_STRUCT_CLK_HW_OMAP(per_l4_ick, "per_clkdm");
1417 DEFINE_STRUCT_CLK(per_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
1418
1419 static struct clk gpio2_ick;
1420
1421 static const char *gpio2_ick_parent_names[] = {
1422         "per_l4_ick",
1423 };
1424
1425 static struct clk_hw_omap gpio2_ick_hw = {
1426         .hw = {
1427                 .clk = &gpio2_ick,
1428         },
1429         .ops            = &clkhwops_iclk_wait,
1430         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1431         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
1432         .clkdm_name     = "per_clkdm",
1433 };
1434
1435 DEFINE_STRUCT_CLK(gpio2_ick, gpio2_ick_parent_names, aes2_ick_ops);
1436
1437 static struct clk gpio3_dbck;
1438
1439 static struct clk_hw_omap gpio3_dbck_hw = {
1440         .hw = {
1441                 .clk = &gpio3_dbck,
1442         },
1443         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1444         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
1445         .clkdm_name     = "per_clkdm",
1446 };
1447
1448 DEFINE_STRUCT_CLK(gpio3_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1449
1450 static struct clk gpio3_ick;
1451
1452 static struct clk_hw_omap gpio3_ick_hw = {
1453         .hw = {
1454                 .clk = &gpio3_ick,
1455         },
1456         .ops            = &clkhwops_iclk_wait,
1457         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1458         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
1459         .clkdm_name     = "per_clkdm",
1460 };
1461
1462 DEFINE_STRUCT_CLK(gpio3_ick, gpio2_ick_parent_names, aes2_ick_ops);
1463
1464 static struct clk gpio4_dbck;
1465
1466 static struct clk_hw_omap gpio4_dbck_hw = {
1467         .hw = {
1468                 .clk = &gpio4_dbck,
1469         },
1470         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1471         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
1472         .clkdm_name     = "per_clkdm",
1473 };
1474
1475 DEFINE_STRUCT_CLK(gpio4_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1476
1477 static struct clk gpio4_ick;
1478
1479 static struct clk_hw_omap gpio4_ick_hw = {
1480         .hw = {
1481                 .clk = &gpio4_ick,
1482         },
1483         .ops            = &clkhwops_iclk_wait,
1484         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1485         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
1486         .clkdm_name     = "per_clkdm",
1487 };
1488
1489 DEFINE_STRUCT_CLK(gpio4_ick, gpio2_ick_parent_names, aes2_ick_ops);
1490
1491 static struct clk gpio5_dbck;
1492
1493 static struct clk_hw_omap gpio5_dbck_hw = {
1494         .hw = {
1495                 .clk = &gpio5_dbck,
1496         },
1497         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1498         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
1499         .clkdm_name     = "per_clkdm",
1500 };
1501
1502 DEFINE_STRUCT_CLK(gpio5_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1503
1504 static struct clk gpio5_ick;
1505
1506 static struct clk_hw_omap gpio5_ick_hw = {
1507         .hw = {
1508                 .clk = &gpio5_ick,
1509         },
1510         .ops            = &clkhwops_iclk_wait,
1511         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1512         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
1513         .clkdm_name     = "per_clkdm",
1514 };
1515
1516 DEFINE_STRUCT_CLK(gpio5_ick, gpio2_ick_parent_names, aes2_ick_ops);
1517
1518 static struct clk gpio6_dbck;
1519
1520 static struct clk_hw_omap gpio6_dbck_hw = {
1521         .hw = {
1522                 .clk = &gpio6_dbck,
1523         },
1524         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1525         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
1526         .clkdm_name     = "per_clkdm",
1527 };
1528
1529 DEFINE_STRUCT_CLK(gpio6_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1530
1531 static struct clk gpio6_ick;
1532
1533 static struct clk_hw_omap gpio6_ick_hw = {
1534         .hw = {
1535                 .clk = &gpio6_ick,
1536         },
1537         .ops            = &clkhwops_iclk_wait,
1538         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1539         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
1540         .clkdm_name     = "per_clkdm",
1541 };
1542
1543 DEFINE_STRUCT_CLK(gpio6_ick, gpio2_ick_parent_names, aes2_ick_ops);
1544
1545 static struct clk gpmc_fck;
1546
1547 static struct clk_hw_omap gpmc_fck_hw = {
1548         .hw = {
1549                 .clk = &gpmc_fck,
1550         },
1551         .flags          = ENABLE_ON_INIT,
1552         .clkdm_name     = "core_l3_clkdm",
1553 };
1554
1555 DEFINE_STRUCT_CLK(gpmc_fck, ipss_ick_parent_names, core_l4_ick_ops);
1556
1557 static const struct clksel omap343x_gpt_clksel[] = {
1558         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1559         { .parent = &sys_ck, .rates = gpt_sys_rates },
1560         { .parent = NULL },
1561 };
1562
1563 static const char *gpt10_fck_parent_names[] = {
1564         "omap_32k_fck", "sys_ck",
1565 };
1566
1567 DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap343x_gpt_clksel,
1568                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1569                          OMAP3430_CLKSEL_GPT10_MASK,
1570                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1571                          OMAP3430_EN_GPT10_SHIFT, &clkhwops_wait,
1572                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1573
1574 static struct clk gpt10_ick;
1575
1576 static struct clk_hw_omap gpt10_ick_hw = {
1577         .hw = {
1578                 .clk = &gpt10_ick,
1579         },
1580         .ops            = &clkhwops_iclk_wait,
1581         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1582         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1583         .clkdm_name     = "core_l4_clkdm",
1584 };
1585
1586 DEFINE_STRUCT_CLK(gpt10_ick, aes2_ick_parent_names, aes2_ick_ops);
1587
1588 DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap343x_gpt_clksel,
1589                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1590                          OMAP3430_CLKSEL_GPT11_MASK,
1591                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1592                          OMAP3430_EN_GPT11_SHIFT, &clkhwops_wait,
1593                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1594
1595 static struct clk gpt11_ick;
1596
1597 static struct clk_hw_omap gpt11_ick_hw = {
1598         .hw = {
1599                 .clk = &gpt11_ick,
1600         },
1601         .ops            = &clkhwops_iclk_wait,
1602         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1603         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1604         .clkdm_name     = "core_l4_clkdm",
1605 };
1606
1607 DEFINE_STRUCT_CLK(gpt11_ick, aes2_ick_parent_names, aes2_ick_ops);
1608
1609 static struct clk gpt12_fck;
1610
1611 static const char *gpt12_fck_parent_names[] = {
1612         "secure_32k_fck",
1613 };
1614
1615 DEFINE_STRUCT_CLK_HW_OMAP(gpt12_fck, "wkup_clkdm");
1616 DEFINE_STRUCT_CLK(gpt12_fck, gpt12_fck_parent_names, core_l4_ick_ops);
1617
1618 static struct clk gpt12_ick;
1619
1620 static struct clk_hw_omap gpt12_ick_hw = {
1621         .hw = {
1622                 .clk = &gpt12_ick,
1623         },
1624         .ops            = &clkhwops_iclk_wait,
1625         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1626         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
1627         .clkdm_name     = "wkup_clkdm",
1628 };
1629
1630 DEFINE_STRUCT_CLK(gpt12_ick, gpio1_ick_parent_names, aes2_ick_ops);
1631
1632 DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "wkup_clkdm", omap343x_gpt_clksel,
1633                          OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1634                          OMAP3430_CLKSEL_GPT1_MASK,
1635                          OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1636                          OMAP3430_EN_GPT1_SHIFT, &clkhwops_wait,
1637                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1638
1639 static struct clk gpt1_ick;
1640
1641 static struct clk_hw_omap gpt1_ick_hw = {
1642         .hw = {
1643                 .clk = &gpt1_ick,
1644         },
1645         .ops            = &clkhwops_iclk_wait,
1646         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1647         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
1648         .clkdm_name     = "wkup_clkdm",
1649 };
1650
1651 DEFINE_STRUCT_CLK(gpt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
1652
1653 DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "per_clkdm", omap343x_gpt_clksel,
1654                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1655                          OMAP3430_CLKSEL_GPT2_MASK,
1656                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1657                          OMAP3430_EN_GPT2_SHIFT, &clkhwops_wait,
1658                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1659
1660 static struct clk gpt2_ick;
1661
1662 static struct clk_hw_omap gpt2_ick_hw = {
1663         .hw = {
1664                 .clk = &gpt2_ick,
1665         },
1666         .ops            = &clkhwops_iclk_wait,
1667         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1668         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
1669         .clkdm_name     = "per_clkdm",
1670 };
1671
1672 DEFINE_STRUCT_CLK(gpt2_ick, gpio2_ick_parent_names, aes2_ick_ops);
1673
1674 DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "per_clkdm", omap343x_gpt_clksel,
1675                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1676                          OMAP3430_CLKSEL_GPT3_MASK,
1677                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1678                          OMAP3430_EN_GPT3_SHIFT, &clkhwops_wait,
1679                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1680
1681 static struct clk gpt3_ick;
1682
1683 static struct clk_hw_omap gpt3_ick_hw = {
1684         .hw = {
1685                 .clk = &gpt3_ick,
1686         },
1687         .ops            = &clkhwops_iclk_wait,
1688         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1689         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
1690         .clkdm_name     = "per_clkdm",
1691 };
1692
1693 DEFINE_STRUCT_CLK(gpt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
1694
1695 DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "per_clkdm", omap343x_gpt_clksel,
1696                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1697                          OMAP3430_CLKSEL_GPT4_MASK,
1698                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1699                          OMAP3430_EN_GPT4_SHIFT, &clkhwops_wait,
1700                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1701
1702 static struct clk gpt4_ick;
1703
1704 static struct clk_hw_omap gpt4_ick_hw = {
1705         .hw = {
1706                 .clk = &gpt4_ick,
1707         },
1708         .ops            = &clkhwops_iclk_wait,
1709         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1710         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
1711         .clkdm_name     = "per_clkdm",
1712 };
1713
1714 DEFINE_STRUCT_CLK(gpt4_ick, gpio2_ick_parent_names, aes2_ick_ops);
1715
1716 DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "per_clkdm", omap343x_gpt_clksel,
1717                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1718                          OMAP3430_CLKSEL_GPT5_MASK,
1719                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1720                          OMAP3430_EN_GPT5_SHIFT, &clkhwops_wait,
1721                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1722
1723 static struct clk gpt5_ick;
1724
1725 static struct clk_hw_omap gpt5_ick_hw = {
1726         .hw = {
1727                 .clk = &gpt5_ick,
1728         },
1729         .ops            = &clkhwops_iclk_wait,
1730         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1731         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
1732         .clkdm_name     = "per_clkdm",
1733 };
1734
1735 DEFINE_STRUCT_CLK(gpt5_ick, gpio2_ick_parent_names, aes2_ick_ops);
1736
1737 DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "per_clkdm", omap343x_gpt_clksel,
1738                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1739                          OMAP3430_CLKSEL_GPT6_MASK,
1740                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1741                          OMAP3430_EN_GPT6_SHIFT, &clkhwops_wait,
1742                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1743
1744 static struct clk gpt6_ick;
1745
1746 static struct clk_hw_omap gpt6_ick_hw = {
1747         .hw = {
1748                 .clk = &gpt6_ick,
1749         },
1750         .ops            = &clkhwops_iclk_wait,
1751         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1752         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
1753         .clkdm_name     = "per_clkdm",
1754 };
1755
1756 DEFINE_STRUCT_CLK(gpt6_ick, gpio2_ick_parent_names, aes2_ick_ops);
1757
1758 DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "per_clkdm", omap343x_gpt_clksel,
1759                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1760                          OMAP3430_CLKSEL_GPT7_MASK,
1761                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1762                          OMAP3430_EN_GPT7_SHIFT, &clkhwops_wait,
1763                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1764
1765 static struct clk gpt7_ick;
1766
1767 static struct clk_hw_omap gpt7_ick_hw = {
1768         .hw = {
1769                 .clk = &gpt7_ick,
1770         },
1771         .ops            = &clkhwops_iclk_wait,
1772         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1773         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
1774         .clkdm_name     = "per_clkdm",
1775 };
1776
1777 DEFINE_STRUCT_CLK(gpt7_ick, gpio2_ick_parent_names, aes2_ick_ops);
1778
1779 DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "per_clkdm", omap343x_gpt_clksel,
1780                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1781                          OMAP3430_CLKSEL_GPT8_MASK,
1782                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1783                          OMAP3430_EN_GPT8_SHIFT, &clkhwops_wait,
1784                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1785
1786 static struct clk gpt8_ick;
1787
1788 static struct clk_hw_omap gpt8_ick_hw = {
1789         .hw = {
1790                 .clk = &gpt8_ick,
1791         },
1792         .ops            = &clkhwops_iclk_wait,
1793         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1794         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
1795         .clkdm_name     = "per_clkdm",
1796 };
1797
1798 DEFINE_STRUCT_CLK(gpt8_ick, gpio2_ick_parent_names, aes2_ick_ops);
1799
1800 DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "per_clkdm", omap343x_gpt_clksel,
1801                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1802                          OMAP3430_CLKSEL_GPT9_MASK,
1803                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1804                          OMAP3430_EN_GPT9_SHIFT, &clkhwops_wait,
1805                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1806
1807 static struct clk gpt9_ick;
1808
1809 static struct clk_hw_omap gpt9_ick_hw = {
1810         .hw = {
1811                 .clk = &gpt9_ick,
1812         },
1813         .ops            = &clkhwops_iclk_wait,
1814         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1815         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
1816         .clkdm_name     = "per_clkdm",
1817 };
1818
1819 DEFINE_STRUCT_CLK(gpt9_ick, gpio2_ick_parent_names, aes2_ick_ops);
1820
1821 static struct clk hdq_fck;
1822
1823 static const char *hdq_fck_parent_names[] = {
1824         "core_12m_fck",
1825 };
1826
1827 static struct clk_hw_omap hdq_fck_hw = {
1828         .hw = {
1829                 .clk = &hdq_fck,
1830         },
1831         .ops            = &clkhwops_wait,
1832         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1833         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1834         .clkdm_name     = "core_l4_clkdm",
1835 };
1836
1837 DEFINE_STRUCT_CLK(hdq_fck, hdq_fck_parent_names, aes2_ick_ops);
1838
1839 static struct clk hdq_ick;
1840
1841 static struct clk_hw_omap hdq_ick_hw = {
1842         .hw = {
1843                 .clk = &hdq_ick,
1844         },
1845         .ops            = &clkhwops_iclk_wait,
1846         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1847         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1848         .clkdm_name     = "core_l4_clkdm",
1849 };
1850
1851 DEFINE_STRUCT_CLK(hdq_ick, aes2_ick_parent_names, aes2_ick_ops);
1852
1853 static struct clk hecc_ck;
1854
1855 static struct clk_hw_omap hecc_ck_hw = {
1856         .hw = {
1857                 .clk = &hecc_ck,
1858         },
1859         .ops            = &clkhwops_am35xx_ipss_module_wait,
1860         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1861         .enable_bit     = AM35XX_HECC_VBUSP_CLK_SHIFT,
1862         .clkdm_name     = "core_l3_clkdm",
1863 };
1864
1865 DEFINE_STRUCT_CLK(hecc_ck, dpll3_ck_parent_names, aes2_ick_ops);
1866
1867 static struct clk hsotgusb_fck_am35xx;
1868
1869 static struct clk_hw_omap hsotgusb_fck_am35xx_hw = {
1870         .hw = {
1871                 .clk = &hsotgusb_fck_am35xx,
1872         },
1873         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1874         .enable_bit     = AM35XX_USBOTG_FCLK_SHIFT,
1875         .clkdm_name     = "core_l3_clkdm",
1876 };
1877
1878 DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, dpll3_ck_parent_names, aes2_ick_ops);
1879
1880 static struct clk hsotgusb_ick_3430es1;
1881
1882 static struct clk_hw_omap hsotgusb_ick_3430es1_hw = {
1883         .hw = {
1884                 .clk = &hsotgusb_ick_3430es1,
1885         },
1886         .ops            = &clkhwops_iclk,
1887         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1888         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1889         .clkdm_name     = "core_l3_clkdm",
1890 };
1891
1892 DEFINE_STRUCT_CLK(hsotgusb_ick_3430es1, ipss_ick_parent_names, aes2_ick_ops);
1893
1894 static struct clk hsotgusb_ick_3430es2;
1895
1896 static struct clk_hw_omap hsotgusb_ick_3430es2_hw = {
1897         .hw = {
1898                 .clk = &hsotgusb_ick_3430es2,
1899         },
1900         .ops            = &clkhwops_omap3430es2_iclk_hsotgusb_wait,
1901         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1902         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1903         .clkdm_name     = "core_l3_clkdm",
1904 };
1905
1906 DEFINE_STRUCT_CLK(hsotgusb_ick_3430es2, ipss_ick_parent_names, aes2_ick_ops);
1907
1908 static struct clk hsotgusb_ick_am35xx;
1909
1910 static struct clk_hw_omap hsotgusb_ick_am35xx_hw = {
1911         .hw = {
1912                 .clk = &hsotgusb_ick_am35xx,
1913         },
1914         .ops            = &clkhwops_am35xx_ipss_module_wait,
1915         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1916         .enable_bit     = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
1917         .clkdm_name     = "core_l3_clkdm",
1918 };
1919
1920 DEFINE_STRUCT_CLK(hsotgusb_ick_am35xx, emac_ick_parent_names, aes2_ick_ops);
1921
1922 static struct clk i2c1_fck;
1923
1924 static struct clk_hw_omap i2c1_fck_hw = {
1925         .hw = {
1926                 .clk = &i2c1_fck,
1927         },
1928         .ops            = &clkhwops_wait,
1929         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1930         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1931         .clkdm_name     = "core_l4_clkdm",
1932 };
1933
1934 DEFINE_STRUCT_CLK(i2c1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1935
1936 static struct clk i2c1_ick;
1937
1938 static struct clk_hw_omap i2c1_ick_hw = {
1939         .hw = {
1940                 .clk = &i2c1_ick,
1941         },
1942         .ops            = &clkhwops_iclk_wait,
1943         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1944         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1945         .clkdm_name     = "core_l4_clkdm",
1946 };
1947
1948 DEFINE_STRUCT_CLK(i2c1_ick, aes2_ick_parent_names, aes2_ick_ops);
1949
1950 static struct clk i2c2_fck;
1951
1952 static struct clk_hw_omap i2c2_fck_hw = {
1953         .hw = {
1954                 .clk = &i2c2_fck,
1955         },
1956         .ops            = &clkhwops_wait,
1957         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1958         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1959         .clkdm_name     = "core_l4_clkdm",
1960 };
1961
1962 DEFINE_STRUCT_CLK(i2c2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1963
1964 static struct clk i2c2_ick;
1965
1966 static struct clk_hw_omap i2c2_ick_hw = {
1967         .hw = {
1968                 .clk = &i2c2_ick,
1969         },
1970         .ops            = &clkhwops_iclk_wait,
1971         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1972         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1973         .clkdm_name     = "core_l4_clkdm",
1974 };
1975
1976 DEFINE_STRUCT_CLK(i2c2_ick, aes2_ick_parent_names, aes2_ick_ops);
1977
1978 static struct clk i2c3_fck;
1979
1980 static struct clk_hw_omap i2c3_fck_hw = {
1981         .hw = {
1982                 .clk = &i2c3_fck,
1983         },
1984         .ops            = &clkhwops_wait,
1985         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1986         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1987         .clkdm_name     = "core_l4_clkdm",
1988 };
1989
1990 DEFINE_STRUCT_CLK(i2c3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1991
1992 static struct clk i2c3_ick;
1993
1994 static struct clk_hw_omap i2c3_ick_hw = {
1995         .hw = {
1996                 .clk = &i2c3_ick,
1997         },
1998         .ops            = &clkhwops_iclk_wait,
1999         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2000         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
2001         .clkdm_name     = "core_l4_clkdm",
2002 };
2003
2004 DEFINE_STRUCT_CLK(i2c3_ick, aes2_ick_parent_names, aes2_ick_ops);
2005
2006 static struct clk icr_ick;
2007
2008 static struct clk_hw_omap icr_ick_hw = {
2009         .hw = {
2010                 .clk = &icr_ick,
2011         },
2012         .ops            = &clkhwops_iclk_wait,
2013         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2014         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
2015         .clkdm_name     = "core_l4_clkdm",
2016 };
2017
2018 DEFINE_STRUCT_CLK(icr_ick, aes2_ick_parent_names, aes2_ick_ops);
2019
2020 static struct clk iva2_ck;
2021
2022 static const char *iva2_ck_parent_names[] = {
2023         "dpll2_m2_ck",
2024 };
2025
2026 static struct clk_hw_omap iva2_ck_hw = {
2027         .hw = {
2028                 .clk = &iva2_ck,
2029         },
2030         .ops            = &clkhwops_wait,
2031         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
2032         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
2033         .clkdm_name     = "iva2_clkdm",
2034 };
2035
2036 DEFINE_STRUCT_CLK(iva2_ck, iva2_ck_parent_names, aes2_ick_ops);
2037
2038 static struct clk mad2d_ick;
2039
2040 static struct clk_hw_omap mad2d_ick_hw = {
2041         .hw = {
2042                 .clk = &mad2d_ick,
2043         },
2044         .ops            = &clkhwops_iclk_wait,
2045         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2046         .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
2047         .clkdm_name     = "d2d_clkdm",
2048 };
2049
2050 DEFINE_STRUCT_CLK(mad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
2051
2052 static struct clk mailboxes_ick;
2053
2054 static struct clk_hw_omap mailboxes_ick_hw = {
2055         .hw = {
2056                 .clk = &mailboxes_ick,
2057         },
2058         .ops            = &clkhwops_iclk_wait,
2059         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2060         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2061         .clkdm_name     = "core_l4_clkdm",
2062 };
2063
2064 DEFINE_STRUCT_CLK(mailboxes_ick, aes2_ick_parent_names, aes2_ick_ops);
2065
2066 static const struct clksel_rate common_mcbsp_96m_rates[] = {
2067         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2068         { .div = 0 }
2069 };
2070
2071 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
2072         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2073         { .div = 0 }
2074 };
2075
2076 static const struct clksel mcbsp_15_clksel[] = {
2077         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2078         { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2079         { .parent = NULL },
2080 };
2081
2082 static const char *mcbsp1_fck_parent_names[] = {
2083         "core_96m_fck", "mcbsp_clks",
2084 };
2085
2086 DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_15_clksel,
2087                          OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2088                          OMAP2_MCBSP1_CLKS_MASK,
2089                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2090                          OMAP3430_EN_MCBSP1_SHIFT, &clkhwops_wait,
2091                          mcbsp1_fck_parent_names, clkout2_src_ck_ops);
2092
2093 static struct clk mcbsp1_ick;
2094
2095 static struct clk_hw_omap mcbsp1_ick_hw = {
2096         .hw = {
2097                 .clk = &mcbsp1_ick,
2098         },
2099         .ops            = &clkhwops_iclk_wait,
2100         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2101         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2102         .clkdm_name     = "core_l4_clkdm",
2103 };
2104
2105 DEFINE_STRUCT_CLK(mcbsp1_ick, aes2_ick_parent_names, aes2_ick_ops);
2106
2107 static struct clk per_96m_fck;
2108
2109 DEFINE_STRUCT_CLK_HW_OMAP(per_96m_fck, "per_clkdm");
2110 DEFINE_STRUCT_CLK(per_96m_fck, cm_96m_fck_parent_names, core_l4_ick_ops);
2111
2112 static const struct clksel mcbsp_234_clksel[] = {
2113         { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2114         { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2115         { .parent = NULL },
2116 };
2117
2118 static const char *mcbsp2_fck_parent_names[] = {
2119         "per_96m_fck", "mcbsp_clks",
2120 };
2121
2122 DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "per_clkdm", mcbsp_234_clksel,
2123                          OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2124                          OMAP2_MCBSP2_CLKS_MASK,
2125                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2126                          OMAP3430_EN_MCBSP2_SHIFT, &clkhwops_wait,
2127                          mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2128
2129 static struct clk mcbsp2_ick;
2130
2131 static struct clk_hw_omap mcbsp2_ick_hw = {
2132         .hw = {
2133                 .clk = &mcbsp2_ick,
2134         },
2135         .ops            = &clkhwops_iclk_wait,
2136         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2137         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2138         .clkdm_name     = "per_clkdm",
2139 };
2140
2141 DEFINE_STRUCT_CLK(mcbsp2_ick, gpio2_ick_parent_names, aes2_ick_ops);
2142
2143 DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "per_clkdm", mcbsp_234_clksel,
2144                          OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2145                          OMAP2_MCBSP3_CLKS_MASK,
2146                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2147                          OMAP3430_EN_MCBSP3_SHIFT, &clkhwops_wait,
2148                          mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2149
2150 static struct clk mcbsp3_ick;
2151
2152 static struct clk_hw_omap mcbsp3_ick_hw = {
2153         .hw = {
2154                 .clk = &mcbsp3_ick,
2155         },
2156         .ops            = &clkhwops_iclk_wait,
2157         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2158         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2159         .clkdm_name     = "per_clkdm",
2160 };
2161
2162 DEFINE_STRUCT_CLK(mcbsp3_ick, gpio2_ick_parent_names, aes2_ick_ops);
2163
2164 DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "per_clkdm", mcbsp_234_clksel,
2165                          OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2166                          OMAP2_MCBSP4_CLKS_MASK,
2167                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2168                          OMAP3430_EN_MCBSP4_SHIFT, &clkhwops_wait,
2169                          mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2170
2171 static struct clk mcbsp4_ick;
2172
2173 static struct clk_hw_omap mcbsp4_ick_hw = {
2174         .hw = {
2175                 .clk = &mcbsp4_ick,
2176         },
2177         .ops            = &clkhwops_iclk_wait,
2178         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2179         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2180         .clkdm_name     = "per_clkdm",
2181 };
2182
2183 DEFINE_STRUCT_CLK(mcbsp4_ick, gpio2_ick_parent_names, aes2_ick_ops);
2184
2185 DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_15_clksel,
2186                          OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2187                          OMAP2_MCBSP5_CLKS_MASK,
2188                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2189                          OMAP3430_EN_MCBSP5_SHIFT, &clkhwops_wait,
2190                          mcbsp1_fck_parent_names, clkout2_src_ck_ops);
2191
2192 static struct clk mcbsp5_ick;
2193
2194 static struct clk_hw_omap mcbsp5_ick_hw = {
2195         .hw = {
2196                 .clk = &mcbsp5_ick,
2197         },
2198         .ops            = &clkhwops_iclk_wait,
2199         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2200         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2201         .clkdm_name     = "core_l4_clkdm",
2202 };
2203
2204 DEFINE_STRUCT_CLK(mcbsp5_ick, aes2_ick_parent_names, aes2_ick_ops);
2205
2206 static struct clk mcspi1_fck;
2207
2208 static struct clk_hw_omap mcspi1_fck_hw = {
2209         .hw = {
2210                 .clk = &mcspi1_fck,
2211         },
2212         .ops            = &clkhwops_wait,
2213         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2214         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
2215         .clkdm_name     = "core_l4_clkdm",
2216 };
2217
2218 DEFINE_STRUCT_CLK(mcspi1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2219
2220 static struct clk mcspi1_ick;
2221
2222 static struct clk_hw_omap mcspi1_ick_hw = {
2223         .hw = {
2224                 .clk = &mcspi1_ick,
2225         },
2226         .ops            = &clkhwops_iclk_wait,
2227         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2228         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
2229         .clkdm_name     = "core_l4_clkdm",
2230 };
2231
2232 DEFINE_STRUCT_CLK(mcspi1_ick, aes2_ick_parent_names, aes2_ick_ops);
2233
2234 static struct clk mcspi2_fck;
2235
2236 static struct clk_hw_omap mcspi2_fck_hw = {
2237         .hw = {
2238                 .clk = &mcspi2_fck,
2239         },
2240         .ops            = &clkhwops_wait,
2241         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2242         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
2243         .clkdm_name     = "core_l4_clkdm",
2244 };
2245
2246 DEFINE_STRUCT_CLK(mcspi2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2247
2248 static struct clk mcspi2_ick;
2249
2250 static struct clk_hw_omap mcspi2_ick_hw = {
2251         .hw = {
2252                 .clk = &mcspi2_ick,
2253         },
2254         .ops            = &clkhwops_iclk_wait,
2255         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2256         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
2257         .clkdm_name     = "core_l4_clkdm",
2258 };
2259
2260 DEFINE_STRUCT_CLK(mcspi2_ick, aes2_ick_parent_names, aes2_ick_ops);
2261
2262 static struct clk mcspi3_fck;
2263
2264 static struct clk_hw_omap mcspi3_fck_hw = {
2265         .hw = {
2266                 .clk = &mcspi3_fck,
2267         },
2268         .ops            = &clkhwops_wait,
2269         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2270         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
2271         .clkdm_name     = "core_l4_clkdm",
2272 };
2273
2274 DEFINE_STRUCT_CLK(mcspi3_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2275
2276 static struct clk mcspi3_ick;
2277
2278 static struct clk_hw_omap mcspi3_ick_hw = {
2279         .hw = {
2280                 .clk = &mcspi3_ick,
2281         },
2282         .ops            = &clkhwops_iclk_wait,
2283         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2284         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
2285         .clkdm_name     = "core_l4_clkdm",
2286 };
2287
2288 DEFINE_STRUCT_CLK(mcspi3_ick, aes2_ick_parent_names, aes2_ick_ops);
2289
2290 static struct clk mcspi4_fck;
2291
2292 static struct clk_hw_omap mcspi4_fck_hw = {
2293         .hw = {
2294                 .clk = &mcspi4_fck,
2295         },
2296         .ops            = &clkhwops_wait,
2297         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2298         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
2299         .clkdm_name     = "core_l4_clkdm",
2300 };
2301
2302 DEFINE_STRUCT_CLK(mcspi4_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2303
2304 static struct clk mcspi4_ick;
2305
2306 static struct clk_hw_omap mcspi4_ick_hw = {
2307         .hw = {
2308                 .clk = &mcspi4_ick,
2309         },
2310         .ops            = &clkhwops_iclk_wait,
2311         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2312         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
2313         .clkdm_name     = "core_l4_clkdm",
2314 };
2315
2316 DEFINE_STRUCT_CLK(mcspi4_ick, aes2_ick_parent_names, aes2_ick_ops);
2317
2318 static struct clk mmchs1_fck;
2319
2320 static struct clk_hw_omap mmchs1_fck_hw = {
2321         .hw = {
2322                 .clk = &mmchs1_fck,
2323         },
2324         .ops            = &clkhwops_wait,
2325         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2326         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
2327         .clkdm_name     = "core_l4_clkdm",
2328 };
2329
2330 DEFINE_STRUCT_CLK(mmchs1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2331
2332 static struct clk mmchs1_ick;
2333
2334 static struct clk_hw_omap mmchs1_ick_hw = {
2335         .hw = {
2336                 .clk = &mmchs1_ick,
2337         },
2338         .ops            = &clkhwops_iclk_wait,
2339         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2340         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
2341         .clkdm_name     = "core_l4_clkdm",
2342 };
2343
2344 DEFINE_STRUCT_CLK(mmchs1_ick, aes2_ick_parent_names, aes2_ick_ops);
2345
2346 static struct clk mmchs2_fck;
2347
2348 static struct clk_hw_omap mmchs2_fck_hw = {
2349         .hw = {
2350                 .clk = &mmchs2_fck,
2351         },
2352         .ops            = &clkhwops_wait,
2353         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2354         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
2355         .clkdm_name     = "core_l4_clkdm",
2356 };
2357
2358 DEFINE_STRUCT_CLK(mmchs2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2359
2360 static struct clk mmchs2_ick;
2361
2362 static struct clk_hw_omap mmchs2_ick_hw = {
2363         .hw = {
2364                 .clk = &mmchs2_ick,
2365         },
2366         .ops            = &clkhwops_iclk_wait,
2367         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2368         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
2369         .clkdm_name     = "core_l4_clkdm",
2370 };
2371
2372 DEFINE_STRUCT_CLK(mmchs2_ick, aes2_ick_parent_names, aes2_ick_ops);
2373
2374 static struct clk mmchs3_fck;
2375
2376 static struct clk_hw_omap mmchs3_fck_hw = {
2377         .hw = {
2378                 .clk = &mmchs3_fck,
2379         },
2380         .ops            = &clkhwops_wait,
2381         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2382         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
2383         .clkdm_name     = "core_l4_clkdm",
2384 };
2385
2386 DEFINE_STRUCT_CLK(mmchs3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2387
2388 static struct clk mmchs3_ick;
2389
2390 static struct clk_hw_omap mmchs3_ick_hw = {
2391         .hw = {
2392                 .clk = &mmchs3_ick,
2393         },
2394         .ops            = &clkhwops_iclk_wait,
2395         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2396         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
2397         .clkdm_name     = "core_l4_clkdm",
2398 };
2399
2400 DEFINE_STRUCT_CLK(mmchs3_ick, aes2_ick_parent_names, aes2_ick_ops);
2401
2402 static struct clk modem_fck;
2403
2404 static struct clk_hw_omap modem_fck_hw = {
2405         .hw = {
2406                 .clk = &modem_fck,
2407         },
2408         .ops            = &clkhwops_iclk_wait,
2409         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2410         .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
2411         .clkdm_name     = "d2d_clkdm",
2412 };
2413
2414 DEFINE_STRUCT_CLK(modem_fck, dpll3_ck_parent_names, aes2_ick_ops);
2415
2416 static struct clk mspro_fck;
2417
2418 static struct clk_hw_omap mspro_fck_hw = {
2419         .hw = {
2420                 .clk = &mspro_fck,
2421         },
2422         .ops            = &clkhwops_wait,
2423         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2424         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
2425         .clkdm_name     = "core_l4_clkdm",
2426 };
2427
2428 DEFINE_STRUCT_CLK(mspro_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2429
2430 static struct clk mspro_ick;
2431
2432 static struct clk_hw_omap mspro_ick_hw = {
2433         .hw = {
2434                 .clk = &mspro_ick,
2435         },
2436         .ops            = &clkhwops_iclk_wait,
2437         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2438         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
2439         .clkdm_name     = "core_l4_clkdm",
2440 };
2441
2442 DEFINE_STRUCT_CLK(mspro_ick, aes2_ick_parent_names, aes2_ick_ops);
2443
2444 static struct clk omap_192m_alwon_fck;
2445
2446 DEFINE_STRUCT_CLK_HW_OMAP(omap_192m_alwon_fck, NULL);
2447 DEFINE_STRUCT_CLK(omap_192m_alwon_fck, omap_96m_alwon_fck_parent_names,
2448                   core_ck_ops);
2449
2450 static struct clk omap_32ksync_ick;
2451
2452 static struct clk_hw_omap omap_32ksync_ick_hw = {
2453         .hw = {
2454                 .clk = &omap_32ksync_ick,
2455         },
2456         .ops            = &clkhwops_iclk_wait,
2457         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2458         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2459         .clkdm_name     = "wkup_clkdm",
2460 };
2461
2462 DEFINE_STRUCT_CLK(omap_32ksync_ick, gpio1_ick_parent_names, aes2_ick_ops);
2463
2464 static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
2465         { .div = 1, .val = 1, .flags = RATE_IN_36XX },
2466         { .div = 2, .val = 2, .flags = RATE_IN_36XX },
2467         { .div = 0 }
2468 };
2469
2470 static const struct clksel omap_96m_alwon_fck_clksel[] = {
2471         { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
2472         { .parent = NULL }
2473 };
2474
2475 static struct clk omap_96m_alwon_fck_3630;
2476
2477 static const char *omap_96m_alwon_fck_3630_parent_names[] = {
2478         "omap_192m_alwon_fck",
2479 };
2480
2481 static const struct clk_ops omap_96m_alwon_fck_3630_ops = {
2482         .set_rate       = &omap2_clksel_set_rate,
2483         .recalc_rate    = &omap2_clksel_recalc,
2484         .round_rate     = &omap2_clksel_round_rate,
2485 };
2486
2487 static struct clk_hw_omap omap_96m_alwon_fck_3630_hw = {
2488         .hw = {
2489                 .clk = &omap_96m_alwon_fck_3630,
2490         },
2491         .clksel         = omap_96m_alwon_fck_clksel,
2492         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2493         .clksel_mask    = OMAP3630_CLKSEL_96M_MASK,
2494 };
2495
2496 static struct clk omap_96m_alwon_fck_3630 = {
2497         .name   = "omap_96m_alwon_fck",
2498         .hw     = &omap_96m_alwon_fck_3630_hw.hw,
2499         .parent_names   = omap_96m_alwon_fck_3630_parent_names,
2500         .num_parents    = ARRAY_SIZE(omap_96m_alwon_fck_3630_parent_names),
2501         .ops    = &omap_96m_alwon_fck_3630_ops,
2502 };
2503
2504 static struct clk omapctrl_ick;
2505
2506 static struct clk_hw_omap omapctrl_ick_hw = {
2507         .hw = {
2508                 .clk = &omapctrl_ick,
2509         },
2510         .ops            = &clkhwops_iclk_wait,
2511         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2512         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2513         .flags          = ENABLE_ON_INIT,
2514         .clkdm_name     = "core_l4_clkdm",
2515 };
2516
2517 DEFINE_STRUCT_CLK(omapctrl_ick, aes2_ick_parent_names, aes2_ick_ops);
2518
2519 DEFINE_CLK_DIVIDER(pclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
2520                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2521                    OMAP3430_CLKSEL_PCLK_SHIFT, OMAP3430_CLKSEL_PCLK_WIDTH,
2522                    CLK_DIVIDER_ONE_BASED, NULL);
2523
2524 DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck, 0x0,
2525                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2526                    OMAP3430_CLKSEL_PCLKX2_SHIFT, OMAP3430_CLKSEL_PCLKX2_WIDTH,
2527                    CLK_DIVIDER_ONE_BASED, NULL);
2528
2529 static struct clk per_48m_fck;
2530
2531 DEFINE_STRUCT_CLK_HW_OMAP(per_48m_fck, "per_clkdm");
2532 DEFINE_STRUCT_CLK(per_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
2533
2534 static struct clk security_l3_ick;
2535
2536 DEFINE_STRUCT_CLK_HW_OMAP(security_l3_ick, NULL);
2537 DEFINE_STRUCT_CLK(security_l3_ick, core_l3_ick_parent_names, core_ck_ops);
2538
2539 static struct clk pka_ick;
2540
2541 static const char *pka_ick_parent_names[] = {
2542         "security_l3_ick",
2543 };
2544
2545 static struct clk_hw_omap pka_ick_hw = {
2546         .hw = {
2547                 .clk = &pka_ick,
2548         },
2549         .ops            = &clkhwops_iclk_wait,
2550         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2551         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
2552 };
2553
2554 DEFINE_STRUCT_CLK(pka_ick, pka_ick_parent_names, aes1_ick_ops);
2555
2556 DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick, 0x0,
2557                    OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2558                    OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH,
2559                    CLK_DIVIDER_ONE_BASED, NULL);
2560
2561 static struct clk rng_ick;
2562
2563 static struct clk_hw_omap rng_ick_hw = {
2564         .hw = {
2565                 .clk = &rng_ick,
2566         },
2567         .ops            = &clkhwops_iclk_wait,
2568         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2569         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2570 };
2571
2572 DEFINE_STRUCT_CLK(rng_ick, aes1_ick_parent_names, aes1_ick_ops);
2573
2574 static struct clk sad2d_ick;
2575
2576 static struct clk_hw_omap sad2d_ick_hw = {
2577         .hw = {
2578                 .clk = &sad2d_ick,
2579         },
2580         .ops            = &clkhwops_iclk_wait,
2581         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2582         .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
2583         .clkdm_name     = "d2d_clkdm",
2584 };
2585
2586 DEFINE_STRUCT_CLK(sad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
2587
2588 static struct clk sdrc_ick;
2589
2590 static struct clk_hw_omap sdrc_ick_hw = {
2591         .hw = {
2592                 .clk = &sdrc_ick,
2593         },
2594         .ops            = &clkhwops_wait,
2595         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2596         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
2597         .flags          = ENABLE_ON_INIT,
2598         .clkdm_name     = "core_l3_clkdm",
2599 };
2600
2601 DEFINE_STRUCT_CLK(sdrc_ick, ipss_ick_parent_names, aes2_ick_ops);
2602
2603 static const struct clksel_rate sgx_core_rates[] = {
2604         { .div = 2, .val = 5, .flags = RATE_IN_36XX },
2605         { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
2606         { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
2607         { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
2608         { .div = 0 }
2609 };
2610
2611 static const struct clksel_rate sgx_96m_rates[] = {
2612         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2613         { .div = 0 }
2614 };
2615
2616 static const struct clksel_rate sgx_192m_rates[] = {
2617         { .div = 1, .val = 4, .flags = RATE_IN_36XX },
2618         { .div = 0 }
2619 };
2620
2621 static const struct clksel_rate sgx_corex2_rates[] = {
2622         { .div = 3, .val = 6, .flags = RATE_IN_36XX },
2623         { .div = 5, .val = 7, .flags = RATE_IN_36XX },
2624         { .div = 0 }
2625 };
2626
2627 static const struct clksel sgx_clksel[] = {
2628         { .parent = &core_ck, .rates = sgx_core_rates },
2629         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
2630         { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
2631         { .parent = &corex2_fck, .rates = sgx_corex2_rates },
2632         { .parent = NULL },
2633 };
2634
2635 static const char *sgx_fck_parent_names[] = {
2636         "core_ck", "cm_96m_fck", "omap_192m_alwon_fck", "corex2_fck",
2637 };
2638
2639 static struct clk sgx_fck;
2640
2641 static const struct clk_ops sgx_fck_ops = {
2642         .init           = &omap2_init_clk_clkdm,
2643         .enable         = &omap2_dflt_clk_enable,
2644         .disable        = &omap2_dflt_clk_disable,
2645         .is_enabled     = &omap2_dflt_clk_is_enabled,
2646         .recalc_rate    = &omap2_clksel_recalc,
2647         .set_rate       = &omap2_clksel_set_rate,
2648         .round_rate     = &omap2_clksel_round_rate,
2649         .get_parent     = &omap2_clksel_find_parent_index,
2650         .set_parent     = &omap2_clksel_set_parent,
2651 };
2652
2653 DEFINE_CLK_OMAP_MUX_GATE(sgx_fck, "sgx_clkdm", sgx_clksel,
2654                          OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
2655                          OMAP3430ES2_CLKSEL_SGX_MASK,
2656                          OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
2657                          OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
2658                          &clkhwops_wait, sgx_fck_parent_names, sgx_fck_ops);
2659
2660 static struct clk sgx_ick;
2661
2662 static struct clk_hw_omap sgx_ick_hw = {
2663         .hw = {
2664                 .clk = &sgx_ick,
2665         },
2666         .ops            = &clkhwops_wait,
2667         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
2668         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
2669         .clkdm_name     = "sgx_clkdm",
2670 };
2671
2672 DEFINE_STRUCT_CLK(sgx_ick, core_l3_ick_parent_names, aes2_ick_ops);
2673
2674 static struct clk sha11_ick;
2675
2676 static struct clk_hw_omap sha11_ick_hw = {
2677         .hw = {
2678                 .clk = &sha11_ick,
2679         },
2680         .ops            = &clkhwops_iclk_wait,
2681         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2682         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2683 };
2684
2685 DEFINE_STRUCT_CLK(sha11_ick, aes1_ick_parent_names, aes1_ick_ops);
2686
2687 static struct clk sha12_ick;
2688
2689 static struct clk_hw_omap sha12_ick_hw = {
2690         .hw = {
2691                 .clk = &sha12_ick,
2692         },
2693         .ops            = &clkhwops_iclk_wait,
2694         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2695         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
2696         .clkdm_name     = "core_l4_clkdm",
2697 };
2698
2699 DEFINE_STRUCT_CLK(sha12_ick, aes2_ick_parent_names, aes2_ick_ops);
2700
2701 static struct clk sr1_fck;
2702
2703 static struct clk_hw_omap sr1_fck_hw = {
2704         .hw = {
2705                 .clk = &sr1_fck,
2706         },
2707         .ops            = &clkhwops_wait,
2708         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2709         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
2710         .clkdm_name     = "wkup_clkdm",
2711 };
2712
2713 DEFINE_STRUCT_CLK(sr1_fck, dpll3_ck_parent_names, aes2_ick_ops);
2714
2715 static struct clk sr2_fck;
2716
2717 static struct clk_hw_omap sr2_fck_hw = {
2718         .hw = {
2719                 .clk = &sr2_fck,
2720         },
2721         .ops            = &clkhwops_wait,
2722         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2723         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
2724         .clkdm_name     = "wkup_clkdm",
2725 };
2726
2727 DEFINE_STRUCT_CLK(sr2_fck, dpll3_ck_parent_names, aes2_ick_ops);
2728
2729 static struct clk sr_l4_ick;
2730
2731 DEFINE_STRUCT_CLK_HW_OMAP(sr_l4_ick, "core_l4_clkdm");
2732 DEFINE_STRUCT_CLK(sr_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
2733
2734 static struct clk ssi_l4_ick;
2735
2736 DEFINE_STRUCT_CLK_HW_OMAP(ssi_l4_ick, "core_l4_clkdm");
2737 DEFINE_STRUCT_CLK(ssi_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
2738
2739 static struct clk ssi_ick_3430es1;
2740
2741 static const char *ssi_ick_3430es1_parent_names[] = {
2742         "ssi_l4_ick",
2743 };
2744
2745 static struct clk_hw_omap ssi_ick_3430es1_hw = {
2746         .hw = {
2747                 .clk = &ssi_ick_3430es1,
2748         },
2749         .ops            = &clkhwops_iclk,
2750         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2751         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2752         .clkdm_name     = "core_l4_clkdm",
2753 };
2754
2755 DEFINE_STRUCT_CLK(ssi_ick_3430es1, ssi_ick_3430es1_parent_names, aes2_ick_ops);
2756
2757 static struct clk ssi_ick_3430es2;
2758
2759 static struct clk_hw_omap ssi_ick_3430es2_hw = {
2760         .hw = {
2761                 .clk = &ssi_ick_3430es2,
2762         },
2763         .ops            = &clkhwops_omap3430es2_iclk_ssi_wait,
2764         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2765         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2766         .clkdm_name     = "core_l4_clkdm",
2767 };
2768
2769 DEFINE_STRUCT_CLK(ssi_ick_3430es2, ssi_ick_3430es1_parent_names, aes2_ick_ops);
2770
2771 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
2772         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2773         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2774         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2775         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2776         { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
2777         { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
2778         { .div = 0 }
2779 };
2780
2781 static const struct clksel ssi_ssr_clksel[] = {
2782         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
2783         { .parent = NULL },
2784 };
2785
2786 static const char *ssi_ssr_fck_3430es1_parent_names[] = {
2787         "corex2_fck",
2788 };
2789
2790 static const struct clk_ops ssi_ssr_fck_3430es1_ops = {
2791         .init           = &omap2_init_clk_clkdm,
2792         .enable         = &omap2_dflt_clk_enable,
2793         .disable        = &omap2_dflt_clk_disable,
2794         .is_enabled     = &omap2_dflt_clk_is_enabled,
2795         .recalc_rate    = &omap2_clksel_recalc,
2796         .set_rate       = &omap2_clksel_set_rate,
2797         .round_rate     = &omap2_clksel_round_rate,
2798 };
2799
2800 DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es1, "core_l4_clkdm",
2801                          ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2802                          OMAP3430_CLKSEL_SSI_MASK,
2803                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2804                          OMAP3430_EN_SSI_SHIFT,
2805                          NULL, ssi_ssr_fck_3430es1_parent_names,
2806                          ssi_ssr_fck_3430es1_ops);
2807
2808 DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es2, "core_l4_clkdm",
2809                          ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2810                          OMAP3430_CLKSEL_SSI_MASK,
2811                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2812                          OMAP3430_EN_SSI_SHIFT,
2813                          NULL, ssi_ssr_fck_3430es1_parent_names,
2814                          ssi_ssr_fck_3430es1_ops);
2815
2816 DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1, "ssi_ssr_fck_3430es1",
2817                         &ssi_ssr_fck_3430es1, 0x0, 1, 2);
2818
2819 DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2, "ssi_ssr_fck_3430es2",
2820                         &ssi_ssr_fck_3430es2, 0x0, 1, 2);
2821
2822 static struct clk sys_clkout1;
2823
2824 static const char *sys_clkout1_parent_names[] = {
2825         "osc_sys_ck",
2826 };
2827
2828 static struct clk_hw_omap sys_clkout1_hw = {
2829         .hw = {
2830                 .clk = &sys_clkout1,
2831         },
2832         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
2833         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
2834 };
2835
2836 DEFINE_STRUCT_CLK(sys_clkout1, sys_clkout1_parent_names, aes1_ick_ops);
2837
2838 DEFINE_CLK_DIVIDER(sys_clkout2, "clkout2_src_ck", &clkout2_src_ck, 0x0,
2839                    OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_DIV_SHIFT,
2840                    OMAP3430_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
2841
2842 DEFINE_CLK_MUX(traceclk_src_fck, emu_src_ck_parent_names, NULL, 0x0,
2843                OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2844                OMAP3430_TRACE_MUX_CTRL_SHIFT, OMAP3430_TRACE_MUX_CTRL_WIDTH,
2845                0x0, NULL);
2846
2847 DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck, 0x0,
2848                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2849                    OMAP3430_CLKSEL_TRACECLK_SHIFT,
2850                    OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
2851
2852 static struct clk ts_fck;
2853
2854 static struct clk_hw_omap ts_fck_hw = {
2855         .hw = {
2856                 .clk = &ts_fck,
2857         },
2858         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
2859         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
2860         .clkdm_name     = "core_l4_clkdm",
2861 };
2862
2863 DEFINE_STRUCT_CLK(ts_fck, wkup_32k_fck_parent_names, aes2_ick_ops);
2864
2865 static struct clk uart1_fck;
2866
2867 static struct clk_hw_omap uart1_fck_hw = {
2868         .hw = {
2869                 .clk = &uart1_fck,
2870         },
2871         .ops            = &clkhwops_wait,
2872         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2873         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
2874         .clkdm_name     = "core_l4_clkdm",
2875 };
2876
2877 DEFINE_STRUCT_CLK(uart1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2878
2879 static struct clk uart1_ick;
2880
2881 static struct clk_hw_omap uart1_ick_hw = {
2882         .hw = {
2883                 .clk = &uart1_ick,
2884         },
2885         .ops            = &clkhwops_iclk_wait,
2886         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2887         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
2888         .clkdm_name     = "core_l4_clkdm",
2889 };
2890
2891 DEFINE_STRUCT_CLK(uart1_ick, aes2_ick_parent_names, aes2_ick_ops);
2892
2893 static struct clk uart2_fck;
2894
2895 static struct clk_hw_omap uart2_fck_hw = {
2896         .hw = {
2897                 .clk = &uart2_fck,
2898         },
2899         .ops            = &clkhwops_wait,
2900         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2901         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
2902         .clkdm_name     = "core_l4_clkdm",
2903 };
2904
2905 DEFINE_STRUCT_CLK(uart2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2906
2907 static struct clk uart2_ick;
2908
2909 static struct clk_hw_omap uart2_ick_hw = {
2910         .hw = {
2911                 .clk = &uart2_ick,
2912         },
2913         .ops            = &clkhwops_iclk_wait,
2914         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2915         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
2916         .clkdm_name     = "core_l4_clkdm",
2917 };
2918
2919 DEFINE_STRUCT_CLK(uart2_ick, aes2_ick_parent_names, aes2_ick_ops);
2920
2921 static struct clk uart3_fck;
2922
2923 static const char *uart3_fck_parent_names[] = {
2924         "per_48m_fck",
2925 };
2926
2927 static struct clk_hw_omap uart3_fck_hw = {
2928         .hw = {
2929                 .clk = &uart3_fck,
2930         },
2931         .ops            = &clkhwops_wait,
2932         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2933         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2934         .clkdm_name     = "per_clkdm",
2935 };
2936
2937 DEFINE_STRUCT_CLK(uart3_fck, uart3_fck_parent_names, aes2_ick_ops);
2938
2939 static struct clk uart3_ick;
2940
2941 static struct clk_hw_omap uart3_ick_hw = {
2942         .hw = {
2943                 .clk = &uart3_ick,
2944         },
2945         .ops            = &clkhwops_iclk_wait,
2946         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2947         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2948         .clkdm_name     = "per_clkdm",
2949 };
2950
2951 DEFINE_STRUCT_CLK(uart3_ick, gpio2_ick_parent_names, aes2_ick_ops);
2952
2953 static struct clk uart4_fck;
2954
2955 static struct clk_hw_omap uart4_fck_hw = {
2956         .hw = {
2957                 .clk = &uart4_fck,
2958         },
2959         .ops            = &clkhwops_wait,
2960         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2961         .enable_bit     = OMAP3630_EN_UART4_SHIFT,
2962         .clkdm_name     = "per_clkdm",
2963 };
2964
2965 DEFINE_STRUCT_CLK(uart4_fck, uart3_fck_parent_names, aes2_ick_ops);
2966
2967 static struct clk uart4_fck_am35xx;
2968
2969 static struct clk_hw_omap uart4_fck_am35xx_hw = {
2970         .hw = {
2971                 .clk = &uart4_fck_am35xx,
2972         },
2973         .ops            = &clkhwops_wait,
2974         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2975         .enable_bit     = AM35XX_EN_UART4_SHIFT,
2976         .clkdm_name     = "core_l4_clkdm",
2977 };
2978
2979 DEFINE_STRUCT_CLK(uart4_fck_am35xx, fshostusb_fck_parent_names, aes2_ick_ops);
2980
2981 static struct clk uart4_ick;
2982
2983 static struct clk_hw_omap uart4_ick_hw = {
2984         .hw = {
2985                 .clk = &uart4_ick,
2986         },
2987         .ops            = &clkhwops_iclk_wait,
2988         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2989         .enable_bit     = OMAP3630_EN_UART4_SHIFT,
2990         .clkdm_name     = "per_clkdm",
2991 };
2992
2993 DEFINE_STRUCT_CLK(uart4_ick, gpio2_ick_parent_names, aes2_ick_ops);
2994
2995 static struct clk uart4_ick_am35xx;
2996
2997 static struct clk_hw_omap uart4_ick_am35xx_hw = {
2998         .hw = {
2999                 .clk = &uart4_ick_am35xx,
3000         },
3001         .ops            = &clkhwops_iclk_wait,
3002         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3003         .enable_bit     = AM35XX_EN_UART4_SHIFT,
3004         .clkdm_name     = "core_l4_clkdm",
3005 };
3006
3007 DEFINE_STRUCT_CLK(uart4_ick_am35xx, aes2_ick_parent_names, aes2_ick_ops);
3008
3009 static const struct clksel_rate div2_rates[] = {
3010         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3011         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3012         { .div = 0 }
3013 };
3014
3015 static const struct clksel usb_l4_clksel[] = {
3016         { .parent = &l4_ick, .rates = div2_rates },
3017         { .parent = NULL },
3018 };
3019
3020 static const char *usb_l4_ick_parent_names[] = {
3021         "l4_ick",
3022 };
3023
3024 DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_clksel,
3025                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
3026                          OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
3027                          OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3028                          OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
3029                          &clkhwops_iclk_wait, usb_l4_ick_parent_names,
3030                          ssi_ssr_fck_3430es1_ops);
3031
3032 static struct clk usbhost_120m_fck;
3033
3034 static const char *usbhost_120m_fck_parent_names[] = {
3035         "dpll5_m2_ck",
3036 };
3037
3038 static struct clk_hw_omap usbhost_120m_fck_hw = {
3039         .hw = {
3040                 .clk = &usbhost_120m_fck,
3041         },
3042         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
3043         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
3044         .clkdm_name     = "usbhost_clkdm",
3045 };
3046
3047 DEFINE_STRUCT_CLK(usbhost_120m_fck, usbhost_120m_fck_parent_names,
3048                   aes2_ick_ops);
3049
3050 static struct clk usbhost_48m_fck;
3051
3052 static struct clk_hw_omap usbhost_48m_fck_hw = {
3053         .hw = {
3054                 .clk = &usbhost_48m_fck,
3055         },
3056         .ops            = &clkhwops_omap3430es2_dss_usbhost_wait,
3057         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
3058         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
3059         .clkdm_name     = "usbhost_clkdm",
3060 };
3061
3062 DEFINE_STRUCT_CLK(usbhost_48m_fck, core_48m_fck_parent_names, aes2_ick_ops);
3063
3064 static struct clk usbhost_ick;
3065
3066 static struct clk_hw_omap usbhost_ick_hw = {
3067         .hw = {
3068                 .clk = &usbhost_ick,
3069         },
3070         .ops            = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
3071         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
3072         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
3073         .clkdm_name     = "usbhost_clkdm",
3074 };
3075
3076 DEFINE_STRUCT_CLK(usbhost_ick, security_l4_ick2_parent_names, aes2_ick_ops);
3077
3078 static struct clk usbtll_fck;
3079
3080 static struct clk_hw_omap usbtll_fck_hw = {
3081         .hw = {
3082                 .clk = &usbtll_fck,
3083         },
3084         .ops            = &clkhwops_wait,
3085         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
3086         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
3087         .clkdm_name     = "core_l4_clkdm",
3088 };
3089
3090 DEFINE_STRUCT_CLK(usbtll_fck, usbhost_120m_fck_parent_names, aes2_ick_ops);
3091
3092 static struct clk usbtll_ick;
3093
3094 static struct clk_hw_omap usbtll_ick_hw = {
3095         .hw = {
3096                 .clk = &usbtll_ick,
3097         },
3098         .ops            = &clkhwops_iclk_wait,
3099         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
3100         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
3101         .clkdm_name     = "core_l4_clkdm",
3102 };
3103
3104 DEFINE_STRUCT_CLK(usbtll_ick, aes2_ick_parent_names, aes2_ick_ops);
3105
3106 static const struct clksel_rate usim_96m_rates[] = {
3107         { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
3108         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3109         { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
3110         { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
3111         { .div = 0 }
3112 };
3113
3114 static const struct clksel_rate usim_120m_rates[] = {
3115         { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
3116         { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
3117         { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
3118         { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
3119         { .div = 0 }
3120 };
3121
3122 static const struct clksel usim_clksel[] = {
3123         { .parent = &omap_96m_fck, .rates = usim_96m_rates },
3124         { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
3125         { .parent = &sys_ck, .rates = div2_rates },
3126         { .parent = NULL },
3127 };
3128
3129 static const char *usim_fck_parent_names[] = {
3130         "omap_96m_fck", "dpll5_m2_ck", "sys_ck",
3131 };
3132
3133 static struct clk usim_fck;
3134
3135 static const struct clk_ops usim_fck_ops = {
3136         .enable         = &omap2_dflt_clk_enable,
3137         .disable        = &omap2_dflt_clk_disable,
3138         .is_enabled     = &omap2_dflt_clk_is_enabled,
3139         .recalc_rate    = &omap2_clksel_recalc,
3140         .get_parent     = &omap2_clksel_find_parent_index,
3141         .set_parent     = &omap2_clksel_set_parent,
3142 };
3143
3144 DEFINE_CLK_OMAP_MUX_GATE(usim_fck, NULL, usim_clksel,
3145                          OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
3146                          OMAP3430ES2_CLKSEL_USIMOCP_MASK,
3147                          OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3148                          OMAP3430ES2_EN_USIMOCP_SHIFT, &clkhwops_wait,
3149                          usim_fck_parent_names, usim_fck_ops);
3150
3151 static struct clk usim_ick;
3152
3153 static struct clk_hw_omap usim_ick_hw = {
3154         .hw = {
3155                 .clk = &usim_ick,
3156         },
3157         .ops            = &clkhwops_iclk_wait,
3158         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3159         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
3160         .clkdm_name     = "wkup_clkdm",
3161 };
3162
3163 DEFINE_STRUCT_CLK(usim_ick, gpio1_ick_parent_names, aes2_ick_ops);
3164
3165 static struct clk vpfe_fck;
3166
3167 static const char *vpfe_fck_parent_names[] = {
3168         "pclk_ck",
3169 };
3170
3171 static struct clk_hw_omap vpfe_fck_hw = {
3172         .hw = {
3173                 .clk = &vpfe_fck,
3174         },
3175         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3176         .enable_bit     = AM35XX_VPFE_FCLK_SHIFT,
3177 };
3178
3179 DEFINE_STRUCT_CLK(vpfe_fck, vpfe_fck_parent_names, aes1_ick_ops);
3180
3181 static struct clk vpfe_ick;
3182
3183 static struct clk_hw_omap vpfe_ick_hw = {
3184         .hw = {
3185                 .clk = &vpfe_ick,
3186         },
3187         .ops            = &clkhwops_am35xx_ipss_module_wait,
3188         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3189         .enable_bit     = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3190         .clkdm_name     = "core_l3_clkdm",
3191 };
3192
3193 DEFINE_STRUCT_CLK(vpfe_ick, emac_ick_parent_names, aes2_ick_ops);
3194
3195 static struct clk wdt1_fck;
3196
3197 DEFINE_STRUCT_CLK_HW_OMAP(wdt1_fck, "wkup_clkdm");
3198 DEFINE_STRUCT_CLK(wdt1_fck, gpt12_fck_parent_names, core_l4_ick_ops);
3199
3200 static struct clk wdt1_ick;
3201
3202 static struct clk_hw_omap wdt1_ick_hw = {
3203         .hw = {
3204                 .clk = &wdt1_ick,
3205         },
3206         .ops            = &clkhwops_iclk_wait,
3207         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3208         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
3209         .clkdm_name     = "wkup_clkdm",
3210 };
3211
3212 DEFINE_STRUCT_CLK(wdt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
3213
3214 static struct clk wdt2_fck;
3215
3216 static struct clk_hw_omap wdt2_fck_hw = {
3217         .hw = {
3218                 .clk = &wdt2_fck,
3219         },
3220         .ops            = &clkhwops_wait,
3221         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3222         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
3223         .clkdm_name     = "wkup_clkdm",
3224 };
3225
3226 DEFINE_STRUCT_CLK(wdt2_fck, gpio1_dbck_parent_names, aes2_ick_ops);
3227
3228 static struct clk wdt2_ick;
3229
3230 static struct clk_hw_omap wdt2_ick_hw = {
3231         .hw = {
3232                 .clk = &wdt2_ick,
3233         },
3234         .ops            = &clkhwops_iclk_wait,
3235         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3236         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
3237         .clkdm_name     = "wkup_clkdm",
3238 };
3239
3240 DEFINE_STRUCT_CLK(wdt2_ick, gpio1_ick_parent_names, aes2_ick_ops);
3241
3242 static struct clk wdt3_fck;
3243
3244 static struct clk_hw_omap wdt3_fck_hw = {
3245         .hw = {
3246                 .clk = &wdt3_fck,
3247         },
3248         .ops            = &clkhwops_wait,
3249         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
3250         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
3251         .clkdm_name     = "per_clkdm",
3252 };
3253
3254 DEFINE_STRUCT_CLK(wdt3_fck, gpio2_dbck_parent_names, aes2_ick_ops);
3255
3256 static struct clk wdt3_ick;
3257
3258 static struct clk_hw_omap wdt3_ick_hw = {
3259         .hw = {
3260                 .clk = &wdt3_ick,
3261         },
3262         .ops            = &clkhwops_iclk_wait,
3263         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
3264         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
3265         .clkdm_name     = "per_clkdm",
3266 };
3267
3268 DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
3269
3270 /*
3271  * clocks specific to omap3430es1
3272  */
3273 static struct omap_clk omap3430es1_clks[] = {
3274         CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck),
3275         CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck),
3276         CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick),
3277         CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck),
3278         CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck),
3279         CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck),
3280         CLK(NULL,       "fshostusb_fck", &fshostusb_fck),
3281         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1),
3282         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1),
3283         CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es1),
3284         CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es1),
3285         CLK(NULL,       "fac_ick",      &fac_ick),
3286         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1),
3287         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick),
3288         CLK(NULL,       "dss1_alwon_fck",       &dss1_alwon_fck_3430es1),
3289         CLK("omapdss_dss",      "ick",          &dss_ick_3430es1),
3290         CLK(NULL,       "dss_ick",              &dss_ick_3430es1),
3291 };
3292
3293 /*
3294  * clocks specific to am35xx
3295  */
3296 static struct omap_clk am35xx_clks[] = {
3297         CLK(NULL,       "ipss_ick",     &ipss_ick),
3298         CLK(NULL,       "rmii_ck",      &rmii_ck),
3299         CLK(NULL,       "pclk_ck",      &pclk_ck),
3300         CLK(NULL,       "emac_ick",     &emac_ick),
3301         CLK(NULL,       "emac_fck",     &emac_fck),
3302         CLK("davinci_emac.0",   NULL,   &emac_ick),
3303         CLK("davinci_mdio.0",   NULL,   &emac_fck),
3304         CLK("vpfe-capture",     "master",       &vpfe_ick),
3305         CLK("vpfe-capture",     "slave",        &vpfe_fck),
3306         CLK(NULL,       "hsotgusb_ick",         &hsotgusb_ick_am35xx),
3307         CLK(NULL,       "hsotgusb_fck",         &hsotgusb_fck_am35xx),
3308         CLK(NULL,       "hecc_ck",      &hecc_ck),
3309         CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx),
3310         CLK(NULL,       "uart4_fck",    &uart4_fck_am35xx),
3311 };
3312
3313 /*
3314  * clocks specific to omap36xx
3315  */
3316 static struct omap_clk omap36xx_clks[] = {
3317         CLK(NULL,       "omap_192m_alwon_fck", &omap_192m_alwon_fck),
3318         CLK(NULL,       "uart4_fck",    &uart4_fck),
3319 };
3320
3321 /*
3322  * clocks common to omap36xx omap34xx
3323  */
3324 static struct omap_clk omap34xx_omap36xx_clks[] = {
3325         CLK(NULL,       "aes1_ick",     &aes1_ick),
3326         CLK("omap_rng", "ick",          &rng_ick),
3327         CLK("omap3-rom-rng",    "ick",  &rng_ick),
3328         CLK(NULL,       "sha11_ick",    &sha11_ick),
3329         CLK(NULL,       "des1_ick",     &des1_ick),
3330         CLK(NULL,       "cam_mclk",     &cam_mclk),
3331         CLK(NULL,       "cam_ick",      &cam_ick),
3332         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck),
3333         CLK(NULL,       "security_l3_ick", &security_l3_ick),
3334         CLK(NULL,       "pka_ick",      &pka_ick),
3335         CLK(NULL,       "icr_ick",      &icr_ick),
3336         CLK("omap-aes", "ick",  &aes2_ick),
3337         CLK("omap-sham",        "ick",  &sha12_ick),
3338         CLK(NULL,       "des2_ick",     &des2_ick),
3339         CLK(NULL,       "mspro_ick",    &mspro_ick),
3340         CLK(NULL,       "mailboxes_ick", &mailboxes_ick),
3341         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick),
3342         CLK(NULL,       "sr1_fck",      &sr1_fck),
3343         CLK(NULL,       "sr2_fck",      &sr2_fck),
3344         CLK(NULL,       "sr_l4_ick",    &sr_l4_ick),
3345         CLK(NULL,       "security_l4_ick2", &security_l4_ick2),
3346         CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick),
3347         CLK(NULL,       "dpll2_fck",    &dpll2_fck),
3348         CLK(NULL,       "iva2_ck",      &iva2_ck),
3349         CLK(NULL,       "modem_fck",    &modem_fck),
3350         CLK(NULL,       "sad2d_ick",    &sad2d_ick),
3351         CLK(NULL,       "mad2d_ick",    &mad2d_ick),
3352         CLK(NULL,       "mspro_fck",    &mspro_fck),
3353         CLK(NULL,       "dpll2_ck",     &dpll2_ck),
3354         CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck),
3355 };
3356
3357 /*
3358  * clocks common to omap36xx and omap3430es2plus
3359  */
3360 static struct omap_clk omap36xx_omap3430es2plus_clks[] = {
3361         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2),
3362         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2),
3363         CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es2),
3364         CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es2),
3365         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2),
3366         CLK(NULL,       "usim_fck",     &usim_fck),
3367         CLK(NULL,       "usim_ick",     &usim_ick),
3368 };
3369
3370 /*
3371  * clocks common to am35xx omap36xx and omap3430es2plus
3372  */
3373 static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
3374         CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck),
3375         CLK(NULL,       "dpll5_ck",     &dpll5_ck),
3376         CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck),
3377         CLK(NULL,       "sgx_fck",      &sgx_fck),
3378         CLK(NULL,       "sgx_ick",      &sgx_ick),
3379         CLK(NULL,       "cpefuse_fck",  &cpefuse_fck),
3380         CLK(NULL,       "ts_fck",       &ts_fck),
3381         CLK(NULL,       "usbtll_fck",   &usbtll_fck),
3382         CLK(NULL,       "usbtll_ick",   &usbtll_ick),
3383         CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick),
3384         CLK(NULL,       "mmchs3_ick",   &mmchs3_ick),
3385         CLK(NULL,       "mmchs3_fck",   &mmchs3_fck),
3386         CLK(NULL,       "dss1_alwon_fck",       &dss1_alwon_fck_3430es2),
3387         CLK("omapdss_dss",      "ick",          &dss_ick_3430es2),
3388         CLK(NULL,       "dss_ick",              &dss_ick_3430es2),
3389         CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck),
3390         CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck),
3391         CLK(NULL,       "usbhost_ick",  &usbhost_ick),
3392 };
3393
3394 /*
3395  * common clocks
3396  */
3397 static struct omap_clk omap3xxx_clks[] = {
3398         CLK(NULL,       "apb_pclk",     &dummy_apb_pclk),
3399         CLK(NULL,       "omap_32k_fck", &omap_32k_fck),
3400         CLK(NULL,       "virt_12m_ck",  &virt_12m_ck),
3401         CLK(NULL,       "virt_13m_ck",  &virt_13m_ck),
3402         CLK(NULL,       "virt_19200000_ck", &virt_19200000_ck),
3403         CLK(NULL,       "virt_26000000_ck", &virt_26000000_ck),
3404         CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck),
3405         CLK(NULL,       "osc_sys_ck",   &osc_sys_ck),
3406         CLK("twl",      "fck",          &osc_sys_ck),
3407         CLK(NULL,       "sys_ck",       &sys_ck),
3408         CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck),
3409         CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck),
3410         CLK(NULL,       "sys_altclk",   &sys_altclk),
3411         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks),
3412         CLK(NULL,       "sys_clkout1",  &sys_clkout1),
3413         CLK(NULL,       "dpll1_ck",     &dpll1_ck),
3414         CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck),
3415         CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck),
3416         CLK(NULL,       "dpll3_ck",     &dpll3_ck),
3417         CLK(NULL,       "core_ck",      &core_ck),
3418         CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck),
3419         CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck),
3420         CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck),
3421         CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck),
3422         CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck),
3423         CLK(NULL,       "dpll4_ck",     &dpll4_ck),
3424         CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck),
3425         CLK(NULL,       "omap_96m_fck", &omap_96m_fck),
3426         CLK(NULL,       "cm_96m_fck",   &cm_96m_fck),
3427         CLK(NULL,       "omap_54m_fck", &omap_54m_fck),
3428         CLK(NULL,       "omap_48m_fck", &omap_48m_fck),
3429         CLK(NULL,       "omap_12m_fck", &omap_12m_fck),
3430         CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck),
3431         CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck),
3432         CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck),
3433         CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck),
3434         CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck),
3435         CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck),
3436         CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck),
3437         CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck),
3438         CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck),
3439         CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck),
3440         CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck),
3441         CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck),
3442         CLK(NULL,       "sys_clkout2",  &sys_clkout2),
3443         CLK(NULL,       "corex2_fck",   &corex2_fck),
3444         CLK(NULL,       "dpll1_fck",    &dpll1_fck),
3445         CLK(NULL,       "mpu_ck",       &mpu_ck),
3446         CLK(NULL,       "arm_fck",      &arm_fck),
3447         CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck),
3448         CLK(NULL,       "l3_ick",       &l3_ick),
3449         CLK(NULL,       "l4_ick",       &l4_ick),
3450         CLK(NULL,       "rm_ick",       &rm_ick),
3451         CLK(NULL,       "gpt10_fck",    &gpt10_fck),
3452         CLK(NULL,       "gpt11_fck",    &gpt11_fck),
3453         CLK(NULL,       "core_96m_fck", &core_96m_fck),
3454         CLK(NULL,       "mmchs2_fck",   &mmchs2_fck),
3455         CLK(NULL,       "mmchs1_fck",   &mmchs1_fck),
3456         CLK(NULL,       "i2c3_fck",     &i2c3_fck),
3457         CLK(NULL,       "i2c2_fck",     &i2c2_fck),
3458         CLK(NULL,       "i2c1_fck",     &i2c1_fck),
3459         CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck),
3460         CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck),
3461         CLK(NULL,       "core_48m_fck", &core_48m_fck),
3462         CLK(NULL,       "mcspi4_fck",   &mcspi4_fck),
3463         CLK(NULL,       "mcspi3_fck",   &mcspi3_fck),
3464         CLK(NULL,       "mcspi2_fck",   &mcspi2_fck),
3465         CLK(NULL,       "mcspi1_fck",   &mcspi1_fck),
3466         CLK(NULL,       "uart2_fck",    &uart2_fck),
3467         CLK(NULL,       "uart1_fck",    &uart1_fck),
3468         CLK(NULL,       "core_12m_fck", &core_12m_fck),
3469         CLK("omap_hdq.0",       "fck",  &hdq_fck),
3470         CLK(NULL,       "hdq_fck",      &hdq_fck),
3471         CLK(NULL,       "core_l3_ick",  &core_l3_ick),
3472         CLK(NULL,       "sdrc_ick",     &sdrc_ick),
3473         CLK(NULL,       "gpmc_fck",     &gpmc_fck),
3474         CLK(NULL,       "core_l4_ick",  &core_l4_ick),
3475         CLK("omap_hsmmc.1",     "ick",  &mmchs2_ick),
3476         CLK("omap_hsmmc.0",     "ick",  &mmchs1_ick),
3477         CLK(NULL,       "mmchs2_ick",   &mmchs2_ick),
3478         CLK(NULL,       "mmchs1_ick",   &mmchs1_ick),
3479         CLK("omap_hdq.0", "ick",        &hdq_ick),
3480         CLK(NULL,       "hdq_ick",      &hdq_ick),
3481         CLK("omap2_mcspi.4", "ick",     &mcspi4_ick),
3482         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick),
3483         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick),
3484         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick),
3485         CLK(NULL,       "mcspi4_ick",   &mcspi4_ick),
3486         CLK(NULL,       "mcspi3_ick",   &mcspi3_ick),
3487         CLK(NULL,       "mcspi2_ick",   &mcspi2_ick),
3488         CLK(NULL,       "mcspi1_ick",   &mcspi1_ick),
3489         CLK("omap_i2c.3", "ick",        &i2c3_ick),
3490         CLK("omap_i2c.2", "ick",        &i2c2_ick),
3491         CLK("omap_i2c.1", "ick",        &i2c1_ick),
3492         CLK(NULL,       "i2c3_ick",     &i2c3_ick),
3493         CLK(NULL,       "i2c2_ick",     &i2c2_ick),
3494         CLK(NULL,       "i2c1_ick",     &i2c1_ick),
3495         CLK(NULL,       "uart2_ick",    &uart2_ick),
3496         CLK(NULL,       "uart1_ick",    &uart1_ick),
3497         CLK(NULL,       "gpt11_ick",    &gpt11_ick),
3498         CLK(NULL,       "gpt10_ick",    &gpt10_ick),
3499         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick),
3500         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick),
3501         CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick),
3502         CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick),
3503         CLK(NULL,       "omapctrl_ick", &omapctrl_ick),
3504         CLK(NULL,       "dss_tv_fck",   &dss_tv_fck),
3505         CLK(NULL,       "dss_96m_fck",  &dss_96m_fck),
3506         CLK(NULL,       "dss2_alwon_fck",       &dss2_alwon_fck),
3507         CLK(NULL,       "init_60m_fclk",        &dummy_ck),
3508         CLK(NULL,       "gpt1_fck",     &gpt1_fck),
3509         CLK(NULL,       "aes2_ick",     &aes2_ick),
3510         CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck),
3511         CLK(NULL,       "gpio1_dbck",   &gpio1_dbck),
3512         CLK(NULL,       "sha12_ick",    &sha12_ick),
3513         CLK(NULL,       "wdt2_fck",             &wdt2_fck),
3514         CLK("omap_wdt", "ick",          &wdt2_ick),
3515         CLK(NULL,       "wdt2_ick",     &wdt2_ick),
3516         CLK(NULL,       "wdt1_ick",     &wdt1_ick),
3517         CLK(NULL,       "gpio1_ick",    &gpio1_ick),
3518         CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick),
3519         CLK(NULL,       "gpt12_ick",    &gpt12_ick),
3520         CLK(NULL,       "gpt1_ick",     &gpt1_ick),
3521         CLK(NULL,       "per_96m_fck",  &per_96m_fck),
3522         CLK(NULL,       "per_48m_fck",  &per_48m_fck),
3523         CLK(NULL,       "uart3_fck",    &uart3_fck),
3524         CLK(NULL,       "gpt2_fck",     &gpt2_fck),
3525         CLK(NULL,       "gpt3_fck",     &gpt3_fck),
3526         CLK(NULL,       "gpt4_fck",     &gpt4_fck),
3527         CLK(NULL,       "gpt5_fck",     &gpt5_fck),
3528         CLK(NULL,       "gpt6_fck",     &gpt6_fck),
3529         CLK(NULL,       "gpt7_fck",     &gpt7_fck),
3530         CLK(NULL,       "gpt8_fck",     &gpt8_fck),
3531         CLK(NULL,       "gpt9_fck",     &gpt9_fck),
3532         CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck),
3533         CLK(NULL,       "gpio6_dbck",   &gpio6_dbck),
3534         CLK(NULL,       "gpio5_dbck",   &gpio5_dbck),
3535         CLK(NULL,       "gpio4_dbck",   &gpio4_dbck),
3536         CLK(NULL,       "gpio3_dbck",   &gpio3_dbck),
3537         CLK(NULL,       "gpio2_dbck",   &gpio2_dbck),
3538         CLK(NULL,       "wdt3_fck",     &wdt3_fck),
3539         CLK(NULL,       "per_l4_ick",   &per_l4_ick),
3540         CLK(NULL,       "gpio6_ick",    &gpio6_ick),
3541         CLK(NULL,       "gpio5_ick",    &gpio5_ick),
3542         CLK(NULL,       "gpio4_ick",    &gpio4_ick),
3543         CLK(NULL,       "gpio3_ick",    &gpio3_ick),
3544         CLK(NULL,       "gpio2_ick",    &gpio2_ick),
3545         CLK(NULL,       "wdt3_ick",     &wdt3_ick),
3546         CLK(NULL,       "uart3_ick",    &uart3_ick),
3547         CLK(NULL,       "uart4_ick",    &uart4_ick),
3548         CLK(NULL,       "gpt9_ick",     &gpt9_ick),
3549         CLK(NULL,       "gpt8_ick",     &gpt8_ick),
3550         CLK(NULL,       "gpt7_ick",     &gpt7_ick),
3551         CLK(NULL,       "gpt6_ick",     &gpt6_ick),
3552         CLK(NULL,       "gpt5_ick",     &gpt5_ick),
3553         CLK(NULL,       "gpt4_ick",     &gpt4_ick),
3554         CLK(NULL,       "gpt3_ick",     &gpt3_ick),
3555         CLK(NULL,       "gpt2_ick",     &gpt2_ick),
3556         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick),
3557         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick),
3558         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick),
3559         CLK(NULL,       "mcbsp4_ick",   &mcbsp2_ick),
3560         CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick),
3561         CLK(NULL,       "mcbsp2_ick",   &mcbsp4_ick),
3562         CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck),
3563         CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck),
3564         CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck),
3565         CLK("etb",      "emu_src_ck",   &emu_src_ck),
3566         CLK(NULL,       "emu_src_ck",   &emu_src_ck),
3567         CLK(NULL,       "pclk_fck",     &pclk_fck),
3568         CLK(NULL,       "pclkx2_fck",   &pclkx2_fck),
3569         CLK(NULL,       "atclk_fck",    &atclk_fck),
3570         CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck),
3571         CLK(NULL,       "traceclk_fck", &traceclk_fck),
3572         CLK(NULL,       "secure_32k_fck", &secure_32k_fck),
3573         CLK(NULL,       "gpt12_fck",    &gpt12_fck),
3574         CLK(NULL,       "wdt1_fck",     &wdt1_fck),
3575         CLK(NULL,       "timer_32k_ck", &omap_32k_fck),
3576         CLK(NULL,       "timer_sys_ck", &sys_ck),
3577         CLK(NULL,       "cpufreq_ck",   &dpll1_ck),
3578 };
3579
3580 static const char *enable_init_clks[] = {
3581         "sdrc_ick",
3582         "gpmc_fck",
3583         "omapctrl_ick",
3584 };
3585
3586 int __init omap3xxx_clk_init(void)
3587 {
3588         if (omap3_has_192mhz_clk())
3589                 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3590
3591         if (cpu_is_omap3630()) {
3592                 dpll3_m3x2_ck = dpll3_m3x2_ck_3630;
3593                 dpll4_m2x2_ck = dpll4_m2x2_ck_3630;
3594                 dpll4_m3x2_ck = dpll4_m3x2_ck_3630;
3595                 dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
3596                 dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
3597                 dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
3598         }
3599
3600         /*
3601          * XXX This type of dynamic rewriting of the clock tree is
3602          * deprecated and should be revised soon.
3603          */
3604         if (cpu_is_omap3630())
3605                 dpll4_dd = dpll4_dd_3630;
3606         else
3607                 dpll4_dd = dpll4_dd_34xx;
3608
3609
3610         /*
3611          * 3505 must be tested before 3517, since 3517 returns true
3612          * for both AM3517 chips and AM3517 family chips, which
3613          * includes 3505.  Unfortunately there's no obvious family
3614          * test for 3517/3505 :-(
3615          */
3616         if (soc_is_am35xx()) {
3617                 cpu_mask = RATE_IN_34XX;
3618                 omap_clocks_register(am35xx_clks, ARRAY_SIZE(am35xx_clks));
3619                 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3620                                      ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3621                 omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
3622         } else if (cpu_is_omap3630()) {
3623                 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3624                 omap_clocks_register(omap36xx_clks, ARRAY_SIZE(omap36xx_clks));
3625                 omap_clocks_register(omap36xx_omap3430es2plus_clks,
3626                                      ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
3627                 omap_clocks_register(omap34xx_omap36xx_clks,
3628                                      ARRAY_SIZE(omap34xx_omap36xx_clks));
3629                 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3630                                      ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3631                 omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
3632         } else if (soc_is_am33xx()) {
3633                 cpu_mask = RATE_IN_AM33XX;
3634         } else if (cpu_is_ti814x()) {
3635                 cpu_mask = RATE_IN_TI814X;
3636         } else if (cpu_is_omap34xx()) {
3637                 if (omap_rev() == OMAP3430_REV_ES1_0) {
3638                         cpu_mask = RATE_IN_3430ES1;
3639                         omap_clocks_register(omap3430es1_clks,
3640                                              ARRAY_SIZE(omap3430es1_clks));
3641                         omap_clocks_register(omap34xx_omap36xx_clks,
3642                                              ARRAY_SIZE(omap34xx_omap36xx_clks));
3643                         omap_clocks_register(omap3xxx_clks,
3644                                              ARRAY_SIZE(omap3xxx_clks));
3645                 } else {
3646                         /*
3647                          * Assume that anything that we haven't matched yet
3648                          * has 3430ES2-type clocks.
3649                          */
3650                         cpu_mask = RATE_IN_3430ES2PLUS;
3651                         omap_clocks_register(omap34xx_omap36xx_clks,
3652                                              ARRAY_SIZE(omap34xx_omap36xx_clks));
3653                         omap_clocks_register(omap36xx_omap3430es2plus_clks,
3654                                              ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
3655                         omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3656                                              ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3657                         omap_clocks_register(omap3xxx_clks,
3658                                              ARRAY_SIZE(omap3xxx_clks));
3659                 }
3660         } else {
3661                 WARN(1, "clock: could not identify OMAP3 variant\n");
3662         }
3663
3664                 omap2_clk_disable_autoidle_all();
3665
3666         omap2_clk_enable_init_clocks(enable_init_clks,
3667                                      ARRAY_SIZE(enable_init_clks));
3668
3669         pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3670                 (clk_get_rate(&osc_sys_ck) / 1000000),
3671                 (clk_get_rate(&osc_sys_ck) / 100000) % 10,
3672                 (clk_get_rate(&core_ck) / 1000000),
3673                 (clk_get_rate(&arm_fck) / 1000000));
3674
3675         /*
3676          * Lock DPLL5 -- here only until other device init code can
3677          * handle this
3678          */
3679         if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
3680                 omap3_clk_lock_dpll5();
3681
3682         /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3683         sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3684         arm_fck_p = clk_get(NULL, "arm_fck");
3685
3686         return 0;
3687 }