arch/arm/mach-omap2/clock44xx_data.c

   1 /*
   2  * OMAP4 Clock data
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley (paul@pwsan.com)
   8  * Rajendra Nayak (rnayak@ti.com)
   9  * Benoit Cousson (b-cousson@ti.com)
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  *
  21  * XXX Some of the ES1 clocks have been removed/changed; once support
  22  * is added for discriminating clocks by ES level, these should be added back
  23  * in.
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/clk.h>
  29 #include <plat/control.h>
  30 #include <plat/clkdev_omap.h>
  31
  32 #include "clock.h"
  33 #include "clock44xx.h"
  34 #include "cm.h"
  35 #include "cm-regbits-44xx.h"
  36 #include "prm.h"
  37 #include "prm-regbits-44xx.h"
  38
  39 /* Root clocks */
  40
  41 static struct clk extalt_clkin_ck = {
  42         .name           = "extalt_clkin_ck",
  43         .rate           = 59000000,
  44         .ops            = &clkops_null,
  45 };
  46
  47 static struct clk pad_clks_ck = {
  48         .name           = "pad_clks_ck",
  49         .rate           = 12000000,
  50         .ops            = &clkops_null,
  51 };
  52
  53 static struct clk pad_slimbus_core_clks_ck = {
  54         .name           = "pad_slimbus_core_clks_ck",
  55         .rate           = 12000000,
  56         .ops            = &clkops_null,
  57 };
  58
  59 static struct clk secure_32k_clk_src_ck = {
  60         .name           = "secure_32k_clk_src_ck",
  61         .rate           = 32768,
  62         .ops            = &clkops_null,
  63 };
  64
  65 static struct clk slimbus_clk = {
  66         .name           = "slimbus_clk",
  67         .rate           = 12000000,
  68         .ops            = &clkops_null,
  69 };
  70
  71 static struct clk sys_32k_ck = {
  72         .name           = "sys_32k_ck",
  73         .rate           = 32768,
  74         .ops            = &clkops_null,
  75 };
  76
  77 static struct clk virt_12000000_ck = {
  78         .name           = "virt_12000000_ck",
  79         .ops            = &clkops_null,
  80         .rate           = 12000000,
  81 };
  82
  83 static struct clk virt_13000000_ck = {
  84         .name           = "virt_13000000_ck",
  85         .ops            = &clkops_null,
  86         .rate           = 13000000,
  87 };
  88
  89 static struct clk virt_16800000_ck = {
  90         .name           = "virt_16800000_ck",
  91         .ops            = &clkops_null,
  92         .rate           = 16800000,
  93 };
  94
  95 static struct clk virt_19200000_ck = {
  96         .name           = "virt_19200000_ck",
  97         .ops            = &clkops_null,
  98         .rate           = 19200000,
  99 };
 100
 101 static struct clk virt_26000000_ck = {
 102         .name           = "virt_26000000_ck",
 103         .ops            = &clkops_null,
 104         .rate           = 26000000,
 105 };
 106
 107 static struct clk virt_27000000_ck = {
 108         .name           = "virt_27000000_ck",
 109         .ops            = &clkops_null,
 110         .rate           = 27000000,
 111 };
 112
 113 static struct clk virt_38400000_ck = {
 114         .name           = "virt_38400000_ck",
 115         .ops            = &clkops_null,
 116         .rate           = 38400000,
 117 };
 118
 119 static const struct clksel_rate div_1_0_rates[] = {
 120         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 121         { .div = 0 },
 122 };
 123
 124 static const struct clksel_rate div_1_1_rates[] = {
 125         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
 126         { .div = 0 },
 127 };
 128
 129 static const struct clksel_rate div_1_2_rates[] = {
 130         { .div = 1, .val = 2, .flags = RATE_IN_4430 },
 131         { .div = 0 },
 132 };
 133
 134 static const struct clksel_rate div_1_3_rates[] = {
 135         { .div = 1, .val = 3, .flags = RATE_IN_4430 },
 136         { .div = 0 },
 137 };
 138
 139 static const struct clksel_rate div_1_4_rates[] = {
 140         { .div = 1, .val = 4, .flags = RATE_IN_4430 },
 141         { .div = 0 },
 142 };
 143
 144 static const struct clksel_rate div_1_5_rates[] = {
 145         { .div = 1, .val = 5, .flags = RATE_IN_4430 },
 146         { .div = 0 },
 147 };
 148
 149 static const struct clksel_rate div_1_6_rates[] = {
 150         { .div = 1, .val = 6, .flags = RATE_IN_4430 },
 151         { .div = 0 },
 152 };
 153
 154 static const struct clksel_rate div_1_7_rates[] = {
 155         { .div = 1, .val = 7, .flags = RATE_IN_4430 },
 156         { .div = 0 },
 157 };
 158
 159 static const struct clksel sys_clkin_sel[] = {
 160         { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
 161         { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
 162         { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
 163         { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
 164         { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
 165         { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
 166         { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
 167         { .parent = NULL },
 168 };
 169
 170 static struct clk sys_clkin_ck = {
 171         .name           = "sys_clkin_ck",
 172         .rate           = 38400000,
 173         .clksel         = sys_clkin_sel,
 174         .init           = &omap2_init_clksel_parent,
 175         .clksel_reg     = OMAP4430_CM_SYS_CLKSEL,
 176         .clksel_mask    = OMAP4430_SYS_CLKSEL_MASK,
 177         .ops            = &clkops_null,
 178         .recalc         = &omap2_clksel_recalc,
 179 };
 180
 181 static struct clk tie_low_clock_ck = {
 182         .name           = "tie_low_clock_ck",
 183         .rate           = 0,
 184         .ops            = &clkops_null,
 185 };
 186
 187 static struct clk utmi_phy_clkout_ck = {
 188         .name           = "utmi_phy_clkout_ck",
 189         .rate           = 60000000,
 190         .ops            = &clkops_null,
 191 };
 192
 193 static struct clk xclk60mhsp1_ck = {
 194         .name           = "xclk60mhsp1_ck",
 195         .rate           = 60000000,
 196         .ops            = &clkops_null,
 197 };
 198
 199 static struct clk xclk60mhsp2_ck = {
 200         .name           = "xclk60mhsp2_ck",
 201         .rate           = 60000000,
 202         .ops            = &clkops_null,
 203 };
 204
 205 static struct clk xclk60motg_ck = {
 206         .name           = "xclk60motg_ck",
 207         .rate           = 60000000,
 208         .ops            = &clkops_null,
 209 };
 210
 211 /* Module clocks and DPLL outputs */
 212
 213 static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
 214         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 215         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
 216         { .parent = NULL },
 217 };
 218
 219 static struct clk abe_dpll_bypass_clk_mux_ck = {
 220         .name           = "abe_dpll_bypass_clk_mux_ck",
 221         .parent         = &sys_clkin_ck,
 222         .ops            = &clkops_null,
 223         .recalc         = &followparent_recalc,
 224 };
 225
 226 static struct clk abe_dpll_refclk_mux_ck = {
 227         .name           = "abe_dpll_refclk_mux_ck",
 228         .parent         = &sys_clkin_ck,
 229         .clksel         = abe_dpll_bypass_clk_mux_sel,
 230         .init           = &omap2_init_clksel_parent,
 231         .clksel_reg     = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
 232         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
 233         .ops            = &clkops_null,
 234         .recalc         = &omap2_clksel_recalc,
 235 };
 236
 237 /* DPLL_ABE */
 238 static struct dpll_data dpll_abe_dd = {
 239         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
 240         .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
 241         .clk_ref        = &abe_dpll_refclk_mux_ck,
 242         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
 243         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 244         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
 245         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
 246         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 247         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 248         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 249         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 250         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 251         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 252         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 253         .min_divider    = 1,
 254 };
 255
 256
 257 static struct clk dpll_abe_ck = {
 258         .name           = "dpll_abe_ck",
 259         .parent         = &abe_dpll_refclk_mux_ck,
 260         .dpll_data      = &dpll_abe_dd,
 261         .init           = &omap2_init_dpll_parent,
 262         .ops            = &clkops_omap3_noncore_dpll_ops,
 263         .recalc         = &omap3_dpll_recalc,
 264         .round_rate     = &omap2_dpll_round_rate,
 265         .set_rate       = &omap3_noncore_dpll_set_rate,
 266 };
 267
 268 static struct clk dpll_abe_m2x2_ck = {
 269         .name           = "dpll_abe_m2x2_ck",
 270         .parent         = &dpll_abe_ck,
 271         .ops            = &clkops_null,
 272         .recalc         = &followparent_recalc,
 273 };
 274
 275 static struct clk abe_24m_fclk = {
 276         .name           = "abe_24m_fclk",
 277         .parent         = &dpll_abe_m2x2_ck,
 278         .ops            = &clkops_null,
 279         .recalc         = &followparent_recalc,
 280 };
 281
 282 static const struct clksel_rate div3_1to4_rates[] = {
 283         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 284         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 285         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 286         { .div = 0 },
 287 };
 288
 289 static const struct clksel abe_clk_div[] = {
 290         { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
 291         { .parent = NULL },
 292 };
 293
 294 static struct clk abe_clk = {
 295         .name           = "abe_clk",
 296         .parent         = &dpll_abe_m2x2_ck,
 297         .clksel         = abe_clk_div,
 298         .clksel_reg     = OMAP4430_CM_CLKSEL_ABE,
 299         .clksel_mask    = OMAP4430_CLKSEL_OPP_MASK,
 300         .ops            = &clkops_null,
 301         .recalc         = &omap2_clksel_recalc,
 302         .round_rate     = &omap2_clksel_round_rate,
 303         .set_rate       = &omap2_clksel_set_rate,
 304 };
 305
 306 static const struct clksel_rate div2_1to2_rates[] = {
 307         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 308         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 309         { .div = 0 },
 310 };
 311
 312 static const struct clksel aess_fclk_div[] = {
 313         { .parent = &abe_clk, .rates = div2_1to2_rates },
 314         { .parent = NULL },
 315 };
 316
 317 static struct clk aess_fclk = {
 318         .name           = "aess_fclk",
 319         .parent         = &abe_clk,
 320         .clksel         = aess_fclk_div,
 321         .clksel_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
 322         .clksel_mask    = OMAP4430_CLKSEL_AESS_FCLK_MASK,
 323         .ops            = &clkops_null,
 324         .recalc         = &omap2_clksel_recalc,
 325         .round_rate     = &omap2_clksel_round_rate,
 326         .set_rate       = &omap2_clksel_set_rate,
 327 };
 328
 329 static const struct clksel_rate div31_1to31_rates[] = {
 330         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
 331         { .div = 2, .val = 2, .flags = RATE_IN_4430 },
 332         { .div = 3, .val = 3, .flags = RATE_IN_4430 },
 333         { .div = 4, .val = 4, .flags = RATE_IN_4430 },
 334         { .div = 5, .val = 5, .flags = RATE_IN_4430 },
 335         { .div = 6, .val = 6, .flags = RATE_IN_4430 },
 336         { .div = 7, .val = 7, .flags = RATE_IN_4430 },
 337         { .div = 8, .val = 8, .flags = RATE_IN_4430 },
 338         { .div = 9, .val = 9, .flags = RATE_IN_4430 },
 339         { .div = 10, .val = 10, .flags = RATE_IN_4430 },
 340         { .div = 11, .val = 11, .flags = RATE_IN_4430 },
 341         { .div = 12, .val = 12, .flags = RATE_IN_4430 },
 342         { .div = 13, .val = 13, .flags = RATE_IN_4430 },
 343         { .div = 14, .val = 14, .flags = RATE_IN_4430 },
 344         { .div = 15, .val = 15, .flags = RATE_IN_4430 },
 345         { .div = 16, .val = 16, .flags = RATE_IN_4430 },
 346         { .div = 17, .val = 17, .flags = RATE_IN_4430 },
 347         { .div = 18, .val = 18, .flags = RATE_IN_4430 },
 348         { .div = 19, .val = 19, .flags = RATE_IN_4430 },
 349         { .div = 20, .val = 20, .flags = RATE_IN_4430 },
 350         { .div = 21, .val = 21, .flags = RATE_IN_4430 },
 351         { .div = 22, .val = 22, .flags = RATE_IN_4430 },
 352         { .div = 23, .val = 23, .flags = RATE_IN_4430 },
 353         { .div = 24, .val = 24, .flags = RATE_IN_4430 },
 354         { .div = 25, .val = 25, .flags = RATE_IN_4430 },
 355         { .div = 26, .val = 26, .flags = RATE_IN_4430 },
 356         { .div = 27, .val = 27, .flags = RATE_IN_4430 },
 357         { .div = 28, .val = 28, .flags = RATE_IN_4430 },
 358         { .div = 29, .val = 29, .flags = RATE_IN_4430 },
 359         { .div = 30, .val = 30, .flags = RATE_IN_4430 },
 360         { .div = 31, .val = 31, .flags = RATE_IN_4430 },
 361         { .div = 0 },
 362 };
 363
 364 static const struct clksel dpll_abe_m3_div[] = {
 365         { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
 366         { .parent = NULL },
 367 };
 368
 369 static struct clk dpll_abe_m3_ck = {
 370         .name           = "dpll_abe_m3_ck",
 371         .parent         = &dpll_abe_ck,
 372         .clksel         = dpll_abe_m3_div,
 373         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_ABE,
 374         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 375         .ops            = &clkops_null,
 376         .recalc         = &omap2_clksel_recalc,
 377         .round_rate     = &omap2_clksel_round_rate,
 378         .set_rate       = &omap2_clksel_set_rate,
 379 };
 380
 381 static const struct clksel core_hsd_byp_clk_mux_sel[] = {
 382         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 383         { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates },
 384         { .parent = NULL },
 385 };
 386
 387 static struct clk core_hsd_byp_clk_mux_ck = {
 388         .name           = "core_hsd_byp_clk_mux_ck",
 389         .parent         = &sys_clkin_ck,
 390         .clksel         = core_hsd_byp_clk_mux_sel,
 391         .init           = &omap2_init_clksel_parent,
 392         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_CORE,
 393         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 394         .ops            = &clkops_null,
 395         .recalc         = &omap2_clksel_recalc,
 396 };
 397
 398 /* DPLL_CORE */
 399 static struct dpll_data dpll_core_dd = {
 400         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
 401         .clk_bypass     = &core_hsd_byp_clk_mux_ck,
 402         .clk_ref        = &sys_clkin_ck,
 403         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
 404         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 405         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
 406         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
 407         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 408         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 409         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 410         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 411         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 412         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 413         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 414         .min_divider    = 1,
 415 };
 416
 417
 418 static struct clk dpll_core_ck = {
 419         .name           = "dpll_core_ck",
 420         .parent         = &sys_clkin_ck,
 421         .dpll_data      = &dpll_core_dd,
 422         .init           = &omap2_init_dpll_parent,
 423         .ops            = &clkops_null,
 424         .recalc         = &omap3_dpll_recalc,
 425 };
 426
 427 static const struct clksel dpll_core_m6_div[] = {
 428         { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
 429         { .parent = NULL },
 430 };
 431
 432 static struct clk dpll_core_m6_ck = {
 433         .name           = "dpll_core_m6_ck",
 434         .parent         = &dpll_core_ck,
 435         .clksel         = dpll_core_m6_div,
 436         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_CORE,
 437         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 438         .ops            = &clkops_null,
 439         .recalc         = &omap2_clksel_recalc,
 440         .round_rate     = &omap2_clksel_round_rate,
 441         .set_rate       = &omap2_clksel_set_rate,
 442 };
 443
 444 static const struct clksel dbgclk_mux_sel[] = {
 445         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 446         { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
 447         { .parent = NULL },
 448 };
 449
 450 static struct clk dbgclk_mux_ck = {
 451         .name           = "dbgclk_mux_ck",
 452         .parent         = &sys_clkin_ck,
 453         .ops            = &clkops_null,
 454         .recalc         = &followparent_recalc,
 455 };
 456
 457 static struct clk dpll_core_m2_ck = {
 458         .name           = "dpll_core_m2_ck",
 459         .parent         = &dpll_core_ck,
 460         .clksel         = dpll_core_m6_div,
 461         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_CORE,
 462         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 463         .ops            = &clkops_null,
 464         .recalc         = &omap2_clksel_recalc,
 465         .round_rate     = &omap2_clksel_round_rate,
 466         .set_rate       = &omap2_clksel_set_rate,
 467 };
 468
 469 static struct clk ddrphy_ck = {
 470         .name           = "ddrphy_ck",
 471         .parent         = &dpll_core_m2_ck,
 472         .ops            = &clkops_null,
 473         .recalc         = &followparent_recalc,
 474 };
 475
 476 static struct clk dpll_core_m5_ck = {
 477         .name           = "dpll_core_m5_ck",
 478         .parent         = &dpll_core_ck,
 479         .clksel         = dpll_core_m6_div,
 480         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_CORE,
 481         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 482         .ops            = &clkops_null,
 483         .recalc         = &omap2_clksel_recalc,
 484         .round_rate     = &omap2_clksel_round_rate,
 485         .set_rate       = &omap2_clksel_set_rate,
 486 };
 487
 488 static const struct clksel div_core_div[] = {
 489         { .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates },
 490         { .parent = NULL },
 491 };
 492
 493 static struct clk div_core_ck = {
 494         .name           = "div_core_ck",
 495         .parent         = &dpll_core_m5_ck,
 496         .clksel         = div_core_div,
 497         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
 498         .clksel_mask    = OMAP4430_CLKSEL_CORE_MASK,
 499         .ops            = &clkops_null,
 500         .recalc         = &omap2_clksel_recalc,
 501         .round_rate     = &omap2_clksel_round_rate,
 502         .set_rate       = &omap2_clksel_set_rate,
 503 };
 504
 505 static const struct clksel_rate div4_1to8_rates[] = {
 506         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 507         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 508         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 509         { .div = 8, .val = 3, .flags = RATE_IN_4430 },
 510         { .div = 0 },
 511 };
 512
 513 static const struct clksel div_iva_hs_clk_div[] = {
 514         { .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates },
 515         { .parent = NULL },
 516 };
 517
 518 static struct clk div_iva_hs_clk = {
 519         .name           = "div_iva_hs_clk",
 520         .parent         = &dpll_core_m5_ck,
 521         .clksel         = div_iva_hs_clk_div,
 522         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_IVA,
 523         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 524         .ops            = &clkops_null,
 525         .recalc         = &omap2_clksel_recalc,
 526         .round_rate     = &omap2_clksel_round_rate,
 527         .set_rate       = &omap2_clksel_set_rate,
 528 };
 529
 530 static struct clk div_mpu_hs_clk = {
 531         .name           = "div_mpu_hs_clk",
 532         .parent         = &dpll_core_m5_ck,
 533         .clksel         = div_iva_hs_clk_div,
 534         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_MPU,
 535         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 536         .ops            = &clkops_null,
 537         .recalc         = &omap2_clksel_recalc,
 538         .round_rate     = &omap2_clksel_round_rate,
 539         .set_rate       = &omap2_clksel_set_rate,
 540 };
 541
 542 static struct clk dpll_core_m4_ck = {
 543         .name           = "dpll_core_m4_ck",
 544         .parent         = &dpll_core_ck,
 545         .clksel         = dpll_core_m6_div,
 546         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_CORE,
 547         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 548         .ops            = &clkops_null,
 549         .recalc         = &omap2_clksel_recalc,
 550         .round_rate     = &omap2_clksel_round_rate,
 551         .set_rate       = &omap2_clksel_set_rate,
 552 };
 553
 554 static struct clk dll_clk_div_ck = {
 555         .name           = "dll_clk_div_ck",
 556         .parent         = &dpll_core_m4_ck,
 557         .ops            = &clkops_null,
 558         .recalc         = &followparent_recalc,
 559 };
 560
 561 static struct clk dpll_abe_m2_ck = {
 562         .name           = "dpll_abe_m2_ck",
 563         .parent         = &dpll_abe_ck,
 564         .clksel         = dpll_abe_m3_div,
 565         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 566         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 567         .ops            = &clkops_null,
 568         .recalc         = &omap2_clksel_recalc,
 569         .round_rate     = &omap2_clksel_round_rate,
 570         .set_rate       = &omap2_clksel_set_rate,
 571 };
 572
 573 static struct clk dpll_core_m3_ck = {
 574         .name           = "dpll_core_m3_ck",
 575         .parent         = &dpll_core_ck,
 576         .clksel         = dpll_core_m6_div,
 577         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
 578         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 579         .ops            = &clkops_null,
 580         .recalc         = &omap2_clksel_recalc,
 581         .round_rate     = &omap2_clksel_round_rate,
 582         .set_rate       = &omap2_clksel_set_rate,
 583 };
 584
 585 static struct clk dpll_core_m7_ck = {
 586         .name           = "dpll_core_m7_ck",
 587         .parent         = &dpll_core_ck,
 588         .clksel         = dpll_core_m6_div,
 589         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_CORE,
 590         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 591         .ops            = &clkops_null,
 592         .recalc         = &omap2_clksel_recalc,
 593         .round_rate     = &omap2_clksel_round_rate,
 594         .set_rate       = &omap2_clksel_set_rate,
 595 };
 596
 597 static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
 598         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 599         { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
 600         { .parent = NULL },
 601 };
 602
 603 static struct clk iva_hsd_byp_clk_mux_ck = {
 604         .name           = "iva_hsd_byp_clk_mux_ck",
 605         .parent         = &sys_clkin_ck,
 606         .ops            = &clkops_null,
 607         .recalc         = &followparent_recalc,
 608 };
 609
 610 /* DPLL_IVA */
 611 static struct dpll_data dpll_iva_dd = {
 612         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
 613         .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
 614         .clk_ref        = &sys_clkin_ck,
 615         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
 616         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 617         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
 618         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
 619         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 620         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 621         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 622         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 623         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 624         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 625         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 626         .min_divider    = 1,
 627 };
 628
 629
 630 static struct clk dpll_iva_ck = {
 631         .name           = "dpll_iva_ck",
 632         .parent         = &sys_clkin_ck,
 633         .dpll_data      = &dpll_iva_dd,
 634         .init           = &omap2_init_dpll_parent,
 635         .ops            = &clkops_omap3_noncore_dpll_ops,
 636         .recalc         = &omap3_dpll_recalc,
 637         .round_rate     = &omap2_dpll_round_rate,
 638         .set_rate       = &omap3_noncore_dpll_set_rate,
 639 };
 640
 641 static const struct clksel dpll_iva_m4_div[] = {
 642         { .parent = &dpll_iva_ck, .rates = div31_1to31_rates },
 643         { .parent = NULL },
 644 };
 645
 646 static struct clk dpll_iva_m4_ck = {
 647         .name           = "dpll_iva_m4_ck",
 648         .parent         = &dpll_iva_ck,
 649         .clksel         = dpll_iva_m4_div,
 650         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_IVA,
 651         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 652         .ops            = &clkops_null,
 653         .recalc         = &omap2_clksel_recalc,
 654         .round_rate     = &omap2_clksel_round_rate,
 655         .set_rate       = &omap2_clksel_set_rate,
 656 };
 657
 658 static struct clk dpll_iva_m5_ck = {
 659         .name           = "dpll_iva_m5_ck",
 660         .parent         = &dpll_iva_ck,
 661         .clksel         = dpll_iva_m4_div,
 662         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_IVA,
 663         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 664         .ops            = &clkops_null,
 665         .recalc         = &omap2_clksel_recalc,
 666         .round_rate     = &omap2_clksel_round_rate,
 667         .set_rate       = &omap2_clksel_set_rate,
 668 };
 669
 670 /* DPLL_MPU */
 671 static struct dpll_data dpll_mpu_dd = {
 672         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
 673         .clk_bypass     = &div_mpu_hs_clk,
 674         .clk_ref        = &sys_clkin_ck,
 675         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
 676         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 677         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
 678         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
 679         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 680         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 681         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 682         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 683         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 684         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 685         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 686         .min_divider    = 1,
 687 };
 688
 689
 690 static struct clk dpll_mpu_ck = {
 691         .name           = "dpll_mpu_ck",
 692         .parent         = &sys_clkin_ck,
 693         .dpll_data      = &dpll_mpu_dd,
 694         .init           = &omap2_init_dpll_parent,
 695         .ops            = &clkops_omap3_noncore_dpll_ops,
 696         .recalc         = &omap3_dpll_recalc,
 697         .round_rate     = &omap2_dpll_round_rate,
 698         .set_rate       = &omap3_noncore_dpll_set_rate,
 699 };
 700
 701 static const struct clksel dpll_mpu_m2_div[] = {
 702         { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
 703         { .parent = NULL },
 704 };
 705
 706 static struct clk dpll_mpu_m2_ck = {
 707         .name           = "dpll_mpu_m2_ck",
 708         .parent         = &dpll_mpu_ck,
 709         .clksel         = dpll_mpu_m2_div,
 710         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_MPU,
 711         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 712         .ops            = &clkops_null,
 713         .recalc         = &omap2_clksel_recalc,
 714         .round_rate     = &omap2_clksel_round_rate,
 715         .set_rate       = &omap2_clksel_set_rate,
 716 };
 717
 718 static struct clk per_hs_clk_div_ck = {
 719         .name           = "per_hs_clk_div_ck",
 720         .parent         = &dpll_abe_m3_ck,
 721         .ops            = &clkops_null,
 722         .recalc         = &followparent_recalc,
 723 };
 724
 725 static const struct clksel per_hsd_byp_clk_mux_sel[] = {
 726         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 727         { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
 728         { .parent = NULL },
 729 };
 730
 731 static struct clk per_hsd_byp_clk_mux_ck = {
 732         .name           = "per_hsd_byp_clk_mux_ck",
 733         .parent         = &sys_clkin_ck,
 734         .clksel         = per_hsd_byp_clk_mux_sel,
 735         .init           = &omap2_init_clksel_parent,
 736         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_PER,
 737         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 738         .ops            = &clkops_null,
 739         .recalc         = &omap2_clksel_recalc,
 740 };
 741
 742 /* DPLL_PER */
 743 static struct dpll_data dpll_per_dd = {
 744         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
 745         .clk_bypass     = &per_hsd_byp_clk_mux_ck,
 746         .clk_ref        = &sys_clkin_ck,
 747         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
 748         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 749         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
 750         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
 751         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 752         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 753         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 754         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 755         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 756         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 757         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 758         .min_divider    = 1,
 759 };
 760
 761
 762 static struct clk dpll_per_ck = {
 763         .name           = "dpll_per_ck",
 764         .parent         = &sys_clkin_ck,
 765         .dpll_data      = &dpll_per_dd,
 766         .init           = &omap2_init_dpll_parent,
 767         .ops            = &clkops_omap3_noncore_dpll_ops,
 768         .recalc         = &omap3_dpll_recalc,
 769         .round_rate     = &omap2_dpll_round_rate,
 770         .set_rate       = &omap3_noncore_dpll_set_rate,
 771 };
 772
 773 static const struct clksel dpll_per_m2_div[] = {
 774         { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
 775         { .parent = NULL },
 776 };
 777
 778 static struct clk dpll_per_m2_ck = {
 779         .name           = "dpll_per_m2_ck",
 780         .parent         = &dpll_per_ck,
 781         .clksel         = dpll_per_m2_div,
 782         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 783         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 784         .ops            = &clkops_null,
 785         .recalc         = &omap2_clksel_recalc,
 786         .round_rate     = &omap2_clksel_round_rate,
 787         .set_rate       = &omap2_clksel_set_rate,
 788 };
 789
 790 static struct clk dpll_per_m2x2_ck = {
 791         .name           = "dpll_per_m2x2_ck",
 792         .parent         = &dpll_per_ck,
 793         .ops            = &clkops_null,
 794         .recalc         = &followparent_recalc,
 795 };
 796
 797 static struct clk dpll_per_m3_ck = {
 798         .name           = "dpll_per_m3_ck",
 799         .parent         = &dpll_per_ck,
 800         .clksel         = dpll_per_m2_div,
 801         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
 802         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 803         .ops            = &clkops_null,
 804         .recalc         = &omap2_clksel_recalc,
 805         .round_rate     = &omap2_clksel_round_rate,
 806         .set_rate       = &omap2_clksel_set_rate,
 807 };
 808
 809 static struct clk dpll_per_m4_ck = {
 810         .name           = "dpll_per_m4_ck",
 811         .parent         = &dpll_per_ck,
 812         .clksel         = dpll_per_m2_div,
 813         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_PER,
 814         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 815         .ops            = &clkops_null,
 816         .recalc         = &omap2_clksel_recalc,
 817         .round_rate     = &omap2_clksel_round_rate,
 818         .set_rate       = &omap2_clksel_set_rate,
 819 };
 820
 821 static struct clk dpll_per_m5_ck = {
 822         .name           = "dpll_per_m5_ck",
 823         .parent         = &dpll_per_ck,
 824         .clksel         = dpll_per_m2_div,
 825         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_PER,
 826         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 827         .ops            = &clkops_null,
 828         .recalc         = &omap2_clksel_recalc,
 829         .round_rate     = &omap2_clksel_round_rate,
 830         .set_rate       = &omap2_clksel_set_rate,
 831 };
 832
 833 static struct clk dpll_per_m6_ck = {
 834         .name           = "dpll_per_m6_ck",
 835         .parent         = &dpll_per_ck,
 836         .clksel         = dpll_per_m2_div,
 837         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_PER,
 838         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 839         .ops            = &clkops_null,
 840         .recalc         = &omap2_clksel_recalc,
 841         .round_rate     = &omap2_clksel_round_rate,
 842         .set_rate       = &omap2_clksel_set_rate,
 843 };
 844
 845 static struct clk dpll_per_m7_ck = {
 846         .name           = "dpll_per_m7_ck",
 847         .parent         = &dpll_per_ck,
 848         .clksel         = dpll_per_m2_div,
 849         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_PER,
 850         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 851         .ops            = &clkops_null,
 852         .recalc         = &omap2_clksel_recalc,
 853         .round_rate     = &omap2_clksel_round_rate,
 854         .set_rate       = &omap2_clksel_set_rate,
 855 };
 856
 857 /* DPLL_UNIPRO */
 858 static struct dpll_data dpll_unipro_dd = {
 859         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
 860         .clk_bypass     = &sys_clkin_ck,
 861         .clk_ref        = &sys_clkin_ck,
 862         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
 863         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 864         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
 865         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
 866         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 867         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 868         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 869         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 870         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 871         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 872         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 873         .min_divider    = 1,
 874 };
 875
 876
 877 static struct clk dpll_unipro_ck = {
 878         .name           = "dpll_unipro_ck",
 879         .parent         = &sys_clkin_ck,
 880         .dpll_data      = &dpll_unipro_dd,
 881         .init           = &omap2_init_dpll_parent,
 882         .ops            = &clkops_omap3_noncore_dpll_ops,
 883         .recalc         = &omap3_dpll_recalc,
 884         .round_rate     = &omap2_dpll_round_rate,
 885         .set_rate       = &omap3_noncore_dpll_set_rate,
 886 };
 887
 888 static const struct clksel dpll_unipro_m2x2_div[] = {
 889         { .parent = &dpll_unipro_ck, .rates = div31_1to31_rates },
 890         { .parent = NULL },
 891 };
 892
 893 static struct clk dpll_unipro_m2x2_ck = {
 894         .name           = "dpll_unipro_m2x2_ck",
 895         .parent         = &dpll_unipro_ck,
 896         .clksel         = dpll_unipro_m2x2_div,
 897         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
 898         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 899         .ops            = &clkops_null,
 900         .recalc         = &omap2_clksel_recalc,
 901         .round_rate     = &omap2_clksel_round_rate,
 902         .set_rate       = &omap2_clksel_set_rate,
 903 };
 904
 905 static struct clk usb_hs_clk_div_ck = {
 906         .name           = "usb_hs_clk_div_ck",
 907         .parent         = &dpll_abe_m3_ck,
 908         .ops            = &clkops_null,
 909         .recalc         = &followparent_recalc,
 910 };
 911
 912 /* DPLL_USB */
 913 static struct dpll_data dpll_usb_dd = {
 914         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
 915         .clk_bypass     = &usb_hs_clk_div_ck,
 916         .flags          = DPLL_J_TYPE | DPLL_NO_DCO_SEL,
 917         .clk_ref        = &sys_clkin_ck,
 918         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
 919         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 920         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
 921         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
 922         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 923         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 924         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 925         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 926         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 927         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 928         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 929         .min_divider    = 1,
 930 };
 931
 932
 933 static struct clk dpll_usb_ck = {
 934         .name           = "dpll_usb_ck",
 935         .parent         = &sys_clkin_ck,
 936         .dpll_data      = &dpll_usb_dd,
 937         .init           = &omap2_init_dpll_parent,
 938         .ops            = &clkops_omap3_noncore_dpll_ops,
 939         .recalc         = &omap3_dpll_recalc,
 940         .round_rate     = &omap2_dpll_round_rate,
 941         .set_rate       = &omap3_noncore_dpll_set_rate,
 942 };
 943
 944 static struct clk dpll_usb_clkdcoldo_ck = {
 945         .name           = "dpll_usb_clkdcoldo_ck",
 946         .parent         = &dpll_usb_ck,
 947         .ops            = &clkops_null,
 948         .recalc         = &followparent_recalc,
 949 };
 950
 951 static const struct clksel dpll_usb_m2_div[] = {
 952         { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
 953         { .parent = NULL },
 954 };
 955
 956 static struct clk dpll_usb_m2_ck = {
 957         .name           = "dpll_usb_m2_ck",
 958         .parent         = &dpll_usb_ck,
 959         .clksel         = dpll_usb_m2_div,
 960         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_USB,
 961         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
 962         .ops            = &clkops_null,
 963         .recalc         = &omap2_clksel_recalc,
 964         .round_rate     = &omap2_clksel_round_rate,
 965         .set_rate       = &omap2_clksel_set_rate,
 966 };
 967
 968 static const struct clksel ducati_clk_mux_sel[] = {
 969         { .parent = &div_core_ck, .rates = div_1_0_rates },
 970         { .parent = &dpll_per_m6_ck, .rates = div_1_1_rates },
 971         { .parent = NULL },
 972 };
 973
 974 static struct clk ducati_clk_mux_ck = {
 975         .name           = "ducati_clk_mux_ck",
 976         .parent         = &div_core_ck,
 977         .clksel         = ducati_clk_mux_sel,
 978         .init           = &omap2_init_clksel_parent,
 979         .clksel_reg     = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
 980         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
 981         .ops            = &clkops_null,
 982         .recalc         = &omap2_clksel_recalc,
 983 };
 984
 985 static struct clk func_12m_fclk = {
 986         .name           = "func_12m_fclk",
 987         .parent         = &dpll_per_m2x2_ck,
 988         .ops            = &clkops_null,
 989         .recalc         = &followparent_recalc,
 990 };
 991
 992 static struct clk func_24m_clk = {
 993         .name           = "func_24m_clk",
 994         .parent         = &dpll_per_m2_ck,
 995         .ops            = &clkops_null,
 996         .recalc         = &followparent_recalc,
 997 };
 998
 999 static struct clk func_24mc_fclk = {
1000         .name           = "func_24mc_fclk",
1001         .parent         = &dpll_per_m2x2_ck,
1002         .ops            = &clkops_null,
1003         .recalc         = &followparent_recalc,
1004 };
1005
1006 static const struct clksel_rate div2_4to8_rates[] = {
1007         { .div = 4, .val = 0, .flags = RATE_IN_4430 },
1008         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1009         { .div = 0 },
1010 };
1011
1012 static const struct clksel func_48m_fclk_div[] = {
1013         { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
1014         { .parent = NULL },
1015 };
1016
1017 static struct clk func_48m_fclk = {
1018         .name           = "func_48m_fclk",
1019         .parent         = &dpll_per_m2x2_ck,
1020         .clksel         = func_48m_fclk_div,
1021         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1022         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1023         .ops            = &clkops_null,
1024         .recalc         = &omap2_clksel_recalc,
1025         .round_rate     = &omap2_clksel_round_rate,
1026         .set_rate       = &omap2_clksel_set_rate,
1027 };
1028
1029 static struct clk func_48mc_fclk = {
1030         .name           = "func_48mc_fclk",
1031         .parent         = &dpll_per_m2x2_ck,
1032         .ops            = &clkops_null,
1033         .recalc         = &followparent_recalc,
1034 };
1035
1036 static const struct clksel_rate div2_2to4_rates[] = {
1037         { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1038         { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1039         { .div = 0 },
1040 };
1041
1042 static const struct clksel func_64m_fclk_div[] = {
1043         { .parent = &dpll_per_m4_ck, .rates = div2_2to4_rates },
1044         { .parent = NULL },
1045 };
1046
1047 static struct clk func_64m_fclk = {
1048         .name           = "func_64m_fclk",
1049         .parent         = &dpll_per_m4_ck,
1050         .clksel         = func_64m_fclk_div,
1051         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1052         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1053         .ops            = &clkops_null,
1054         .recalc         = &omap2_clksel_recalc,
1055         .round_rate     = &omap2_clksel_round_rate,
1056         .set_rate       = &omap2_clksel_set_rate,
1057 };
1058
1059 static const struct clksel func_96m_fclk_div[] = {
1060         { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1061         { .parent = NULL },
1062 };
1063
1064 static struct clk func_96m_fclk = {
1065         .name           = "func_96m_fclk",
1066         .parent         = &dpll_per_m2x2_ck,
1067         .clksel         = func_96m_fclk_div,
1068         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1069         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1070         .ops            = &clkops_null,
1071         .recalc         = &omap2_clksel_recalc,
1072         .round_rate     = &omap2_clksel_round_rate,
1073         .set_rate       = &omap2_clksel_set_rate,
1074 };
1075
1076 static const struct clksel hsmmc6_fclk_sel[] = {
1077         { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1078         { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1079         { .parent = NULL },
1080 };
1081
1082 static struct clk hsmmc6_fclk = {
1083         .name           = "hsmmc6_fclk",
1084         .parent         = &func_64m_fclk,
1085         .ops            = &clkops_null,
1086         .recalc         = &followparent_recalc,
1087 };
1088
1089 static const struct clksel_rate div2_1to8_rates[] = {
1090         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1091         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1092         { .div = 0 },
1093 };
1094
1095 static const struct clksel init_60m_fclk_div[] = {
1096         { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1097         { .parent = NULL },
1098 };
1099
1100 static struct clk init_60m_fclk = {
1101         .name           = "init_60m_fclk",
1102         .parent         = &dpll_usb_m2_ck,
1103         .clksel         = init_60m_fclk_div,
1104         .clksel_reg     = OMAP4430_CM_CLKSEL_USB_60MHZ,
1105         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1106         .ops            = &clkops_null,
1107         .recalc         = &omap2_clksel_recalc,
1108         .round_rate     = &omap2_clksel_round_rate,
1109         .set_rate       = &omap2_clksel_set_rate,
1110 };
1111
1112 static const struct clksel l3_div_div[] = {
1113         { .parent = &div_core_ck, .rates = div2_1to2_rates },
1114         { .parent = NULL },
1115 };
1116
1117 static struct clk l3_div_ck = {
1118         .name           = "l3_div_ck",
1119         .parent         = &div_core_ck,
1120         .clksel         = l3_div_div,
1121         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1122         .clksel_mask    = OMAP4430_CLKSEL_L3_MASK,
1123         .ops            = &clkops_null,
1124         .recalc         = &omap2_clksel_recalc,
1125         .round_rate     = &omap2_clksel_round_rate,
1126         .set_rate       = &omap2_clksel_set_rate,
1127 };
1128
1129 static const struct clksel l4_div_div[] = {
1130         { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1131         { .parent = NULL },
1132 };
1133
1134 static struct clk l4_div_ck = {
1135         .name           = "l4_div_ck",
1136         .parent         = &l3_div_ck,
1137         .clksel         = l4_div_div,
1138         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1139         .clksel_mask    = OMAP4430_CLKSEL_L4_MASK,
1140         .ops            = &clkops_null,
1141         .recalc         = &omap2_clksel_recalc,
1142         .round_rate     = &omap2_clksel_round_rate,
1143         .set_rate       = &omap2_clksel_set_rate,
1144 };
1145
1146 static struct clk lp_clk_div_ck = {
1147         .name           = "lp_clk_div_ck",
1148         .parent         = &dpll_abe_m2x2_ck,
1149         .ops            = &clkops_null,
1150         .recalc         = &followparent_recalc,
1151 };
1152
1153 static const struct clksel l4_wkup_clk_mux_sel[] = {
1154         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1155         { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1156         { .parent = NULL },
1157 };
1158
1159 static struct clk l4_wkup_clk_mux_ck = {
1160         .name           = "l4_wkup_clk_mux_ck",
1161         .parent         = &sys_clkin_ck,
1162         .clksel         = l4_wkup_clk_mux_sel,
1163         .init           = &omap2_init_clksel_parent,
1164         .clksel_reg     = OMAP4430_CM_L4_WKUP_CLKSEL,
1165         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1166         .ops            = &clkops_null,
1167         .recalc         = &omap2_clksel_recalc,
1168 };
1169
1170 static const struct clksel per_abe_nc_fclk_div[] = {
1171         { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1172         { .parent = NULL },
1173 };
1174
1175 static struct clk per_abe_nc_fclk = {
1176         .name           = "per_abe_nc_fclk",
1177         .parent         = &dpll_abe_m2_ck,
1178         .clksel         = per_abe_nc_fclk_div,
1179         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1180         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1181         .ops            = &clkops_null,
1182         .recalc         = &omap2_clksel_recalc,
1183         .round_rate     = &omap2_clksel_round_rate,
1184         .set_rate       = &omap2_clksel_set_rate,
1185 };
1186
1187 static const struct clksel mcasp2_fclk_sel[] = {
1188         { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1189         { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1190         { .parent = NULL },
1191 };
1192
1193 static struct clk mcasp2_fclk = {
1194         .name           = "mcasp2_fclk",
1195         .parent         = &func_96m_fclk,
1196         .ops            = &clkops_null,
1197         .recalc         = &followparent_recalc,
1198 };
1199
1200 static struct clk mcasp3_fclk = {
1201         .name           = "mcasp3_fclk",
1202         .parent         = &func_96m_fclk,
1203         .ops            = &clkops_null,
1204         .recalc         = &followparent_recalc,
1205 };
1206
1207 static struct clk ocp_abe_iclk = {
1208         .name           = "ocp_abe_iclk",
1209         .parent         = &aess_fclk,
1210         .ops            = &clkops_null,
1211         .recalc         = &followparent_recalc,
1212 };
1213
1214 static struct clk per_abe_24m_fclk = {
1215         .name           = "per_abe_24m_fclk",
1216         .parent         = &dpll_abe_m2_ck,
1217         .ops            = &clkops_null,
1218         .recalc         = &followparent_recalc,
1219 };
1220
1221 static const struct clksel pmd_stm_clock_mux_sel[] = {
1222         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1223         { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
1224         { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
1225         { .parent = NULL },
1226 };
1227
1228 static struct clk pmd_stm_clock_mux_ck = {
1229         .name           = "pmd_stm_clock_mux_ck",
1230         .parent         = &sys_clkin_ck,
1231         .ops            = &clkops_null,
1232         .recalc         = &followparent_recalc,
1233 };
1234
1235 static struct clk pmd_trace_clk_mux_ck = {
1236         .name           = "pmd_trace_clk_mux_ck",
1237         .parent         = &sys_clkin_ck,
1238         .ops            = &clkops_null,
1239         .recalc         = &followparent_recalc,
1240 };
1241
1242 static const struct clksel syc_clk_div_div[] = {
1243         { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
1244         { .parent = NULL },
1245 };
1246
1247 static struct clk syc_clk_div_ck = {
1248         .name           = "syc_clk_div_ck",
1249         .parent         = &sys_clkin_ck,
1250         .clksel         = syc_clk_div_div,
1251         .clksel_reg     = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1252         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1253         .ops            = &clkops_null,
1254         .recalc         = &omap2_clksel_recalc,
1255         .round_rate     = &omap2_clksel_round_rate,
1256         .set_rate       = &omap2_clksel_set_rate,
1257 };
1258
1259 /* Leaf clocks controlled by modules */
1260
1261 static struct clk aes1_fck = {
1262         .name           = "aes1_fck",
1263         .ops            = &clkops_omap2_dflt,
1264         .enable_reg     = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1265         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1266         .clkdm_name     = "l4_secure_clkdm",
1267         .parent         = &l3_div_ck,
1268         .recalc         = &followparent_recalc,
1269 };
1270
1271 static struct clk aes2_fck = {
1272         .name           = "aes2_fck",
1273         .ops            = &clkops_omap2_dflt,
1274         .enable_reg     = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1275         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1276         .clkdm_name     = "l4_secure_clkdm",
1277         .parent         = &l3_div_ck,
1278         .recalc         = &followparent_recalc,
1279 };
1280
1281 static struct clk aess_fck = {
1282         .name           = "aess_fck",
1283         .ops            = &clkops_omap2_dflt,
1284         .enable_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1285         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1286         .clkdm_name     = "abe_clkdm",
1287         .parent         = &aess_fclk,
1288         .recalc         = &followparent_recalc,
1289 };
1290
1291 static struct clk des3des_fck = {
1292         .name           = "des3des_fck",
1293         .ops            = &clkops_omap2_dflt,
1294         .enable_reg     = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1295         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1296         .clkdm_name     = "l4_secure_clkdm",
1297         .parent         = &l4_div_ck,
1298         .recalc         = &followparent_recalc,
1299 };
1300
1301 static const struct clksel dmic_sync_mux_sel[] = {
1302         { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1303         { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1304         { .parent = &func_24m_clk, .rates = div_1_2_rates },
1305         { .parent = NULL },
1306 };
1307
1308 static struct clk dmic_sync_mux_ck = {
1309         .name           = "dmic_sync_mux_ck",
1310         .parent         = &abe_24m_fclk,
1311         .clksel         = dmic_sync_mux_sel,
1312         .init           = &omap2_init_clksel_parent,
1313         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1314         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1315         .ops            = &clkops_null,
1316         .recalc         = &omap2_clksel_recalc,
1317 };
1318
1319 static const struct clksel func_dmic_abe_gfclk_sel[] = {
1320         { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1321         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1322         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1323         { .parent = NULL },
1324 };
1325
1326 /* Merged func_dmic_abe_gfclk into dmic */
1327 static struct clk dmic_fck = {
1328         .name           = "dmic_fck",
1329         .parent         = &dmic_sync_mux_ck,
1330         .clksel         = func_dmic_abe_gfclk_sel,
1331         .init           = &omap2_init_clksel_parent,
1332         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1333         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1334         .ops            = &clkops_omap2_dflt,
1335         .recalc         = &omap2_clksel_recalc,
1336         .enable_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1337         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1338         .clkdm_name     = "abe_clkdm",
1339 };
1340
1341 static struct clk dsp_fck = {
1342         .name           = "dsp_fck",
1343         .ops            = &clkops_omap2_dflt,
1344         .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1345         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1346         .clkdm_name     = "tesla_clkdm",
1347         .parent         = &dpll_iva_m4_ck,
1348         .recalc         = &followparent_recalc,
1349 };
1350
1351 static struct clk dss_fck = {
1352         .name           = "dss_fck",
1353         .ops            = &clkops_omap2_dflt,
1354         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1355         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1356         .clkdm_name     = "l3_dss_clkdm",
1357         .parent         = &l3_div_ck,
1358         .recalc         = &followparent_recalc,
1359 };
1360
1361 static struct clk efuse_ctrl_cust_fck = {
1362         .name           = "efuse_ctrl_cust_fck",
1363         .ops            = &clkops_omap2_dflt,
1364         .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1365         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1366         .clkdm_name     = "l4_cefuse_clkdm",
1367         .parent         = &sys_clkin_ck,
1368         .recalc         = &followparent_recalc,
1369 };
1370
1371 static struct clk emif1_fck = {
1372         .name           = "emif1_fck",
1373         .ops            = &clkops_omap2_dflt,
1374         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1375         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1376         .flags          = ENABLE_ON_INIT,
1377         .clkdm_name     = "l3_emif_clkdm",
1378         .parent         = &ddrphy_ck,
1379         .recalc         = &followparent_recalc,
1380 };
1381
1382 static struct clk emif2_fck = {
1383         .name           = "emif2_fck",
1384         .ops            = &clkops_omap2_dflt,
1385         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1386         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1387         .flags          = ENABLE_ON_INIT,
1388         .clkdm_name     = "l3_emif_clkdm",
1389         .parent         = &ddrphy_ck,
1390         .recalc         = &followparent_recalc,
1391 };
1392
1393 static const struct clksel fdif_fclk_div[] = {
1394         { .parent = &dpll_per_m4_ck, .rates = div3_1to4_rates },
1395         { .parent = NULL },
1396 };
1397
1398 /* Merged fdif_fclk into fdif */
1399 static struct clk fdif_fck = {
1400         .name           = "fdif_fck",
1401         .parent         = &dpll_per_m4_ck,
1402         .clksel         = fdif_fclk_div,
1403         .clksel_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1404         .clksel_mask    = OMAP4430_CLKSEL_FCLK_MASK,
1405         .ops            = &clkops_omap2_dflt,
1406         .recalc         = &omap2_clksel_recalc,
1407         .round_rate     = &omap2_clksel_round_rate,
1408         .set_rate       = &omap2_clksel_set_rate,
1409         .enable_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1410         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1411         .clkdm_name     = "iss_clkdm",
1412 };
1413
1414 static struct clk fpka_fck = {
1415         .name           = "fpka_fck",
1416         .ops            = &clkops_omap2_dflt,
1417         .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
1418         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1419         .clkdm_name     = "l4_secure_clkdm",
1420         .parent         = &l4_div_ck,
1421         .recalc         = &followparent_recalc,
1422 };
1423
1424 static struct clk gpio1_ick = {
1425         .name           = "gpio1_ick",
1426         .ops            = &clkops_omap2_dflt,
1427         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1428         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1429         .clkdm_name     = "l4_wkup_clkdm",
1430         .parent         = &l4_wkup_clk_mux_ck,
1431         .recalc         = &followparent_recalc,
1432 };
1433
1434 static struct clk gpio2_ick = {
1435         .name           = "gpio2_ick",
1436         .ops            = &clkops_omap2_dflt,
1437         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1438         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1439         .clkdm_name     = "l4_per_clkdm",
1440         .parent         = &l4_div_ck,
1441         .recalc         = &followparent_recalc,
1442 };
1443
1444 static struct clk gpio3_ick = {
1445         .name           = "gpio3_ick",
1446         .ops            = &clkops_omap2_dflt,
1447         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1448         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1449         .clkdm_name     = "l4_per_clkdm",
1450         .parent         = &l4_div_ck,
1451         .recalc         = &followparent_recalc,
1452 };
1453
1454 static struct clk gpio4_ick = {
1455         .name           = "gpio4_ick",
1456         .ops            = &clkops_omap2_dflt,
1457         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1458         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1459         .clkdm_name     = "l4_per_clkdm",
1460         .parent         = &l4_div_ck,
1461         .recalc         = &followparent_recalc,
1462 };
1463
1464 static struct clk gpio5_ick = {
1465         .name           = "gpio5_ick",
1466         .ops            = &clkops_omap2_dflt,
1467         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1468         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1469         .clkdm_name     = "l4_per_clkdm",
1470         .parent         = &l4_div_ck,
1471         .recalc         = &followparent_recalc,
1472 };
1473
1474 static struct clk gpio6_ick = {
1475         .name           = "gpio6_ick",
1476         .ops            = &clkops_omap2_dflt,
1477         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1478         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1479         .clkdm_name     = "l4_per_clkdm",
1480         .parent         = &l4_div_ck,
1481         .recalc         = &followparent_recalc,
1482 };
1483
1484 static struct clk gpmc_ick = {
1485         .name           = "gpmc_ick",
1486         .ops            = &clkops_omap2_dflt,
1487         .enable_reg     = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1488         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1489         .clkdm_name     = "l3_2_clkdm",
1490         .parent         = &l3_div_ck,
1491         .recalc         = &followparent_recalc,
1492 };
1493
1494 static const struct clksel sgx_clk_mux_sel[] = {
1495         { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
1496         { .parent = &dpll_per_m7_ck, .rates = div_1_1_rates },
1497         { .parent = NULL },
1498 };
1499
1500 /* Merged sgx_clk_mux into gpu */
1501 static struct clk gpu_fck = {
1502         .name           = "gpu_fck",
1503         .parent         = &dpll_core_m7_ck,
1504         .clksel         = sgx_clk_mux_sel,
1505         .init           = &omap2_init_clksel_parent,
1506         .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1507         .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1508         .ops            = &clkops_omap2_dflt,
1509         .recalc         = &omap2_clksel_recalc,
1510         .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1511         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1512         .clkdm_name     = "l3_gfx_clkdm",
1513 };
1514
1515 static struct clk hdq1w_fck = {
1516         .name           = "hdq1w_fck",
1517         .ops            = &clkops_omap2_dflt,
1518         .enable_reg     = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1519         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1520         .clkdm_name     = "l4_per_clkdm",
1521         .parent         = &func_12m_fclk,
1522         .recalc         = &followparent_recalc,
1523 };
1524
1525 static const struct clksel hsi_fclk_div[] = {
1526         { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1527         { .parent = NULL },
1528 };
1529
1530 /* Merged hsi_fclk into hsi */
1531 static struct clk hsi_fck = {
1532         .name           = "hsi_fck",
1533         .parent         = &dpll_per_m2x2_ck,
1534         .clksel         = hsi_fclk_div,
1535         .clksel_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1536         .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
1537         .ops            = &clkops_omap2_dflt,
1538         .recalc         = &omap2_clksel_recalc,
1539         .round_rate     = &omap2_clksel_round_rate,
1540         .set_rate       = &omap2_clksel_set_rate,
1541         .enable_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1542         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1543         .clkdm_name     = "l3_init_clkdm",
1544 };
1545
1546 static struct clk i2c1_fck = {
1547         .name           = "i2c1_fck",
1548         .ops            = &clkops_omap2_dflt,
1549         .enable_reg     = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1550         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1551         .clkdm_name     = "l4_per_clkdm",
1552         .parent         = &func_96m_fclk,
1553         .recalc         = &followparent_recalc,
1554 };
1555
1556 static struct clk i2c2_fck = {
1557         .name           = "i2c2_fck",
1558         .ops            = &clkops_omap2_dflt,
1559         .enable_reg     = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1560         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1561         .clkdm_name     = "l4_per_clkdm",
1562         .parent         = &func_96m_fclk,
1563         .recalc         = &followparent_recalc,
1564 };
1565
1566 static struct clk i2c3_fck = {
1567         .name           = "i2c3_fck",
1568         .ops            = &clkops_omap2_dflt,
1569         .enable_reg     = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1570         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1571         .clkdm_name     = "l4_per_clkdm",
1572         .parent         = &func_96m_fclk,
1573         .recalc         = &followparent_recalc,
1574 };
1575
1576 static struct clk i2c4_fck = {
1577         .name           = "i2c4_fck",
1578         .ops            = &clkops_omap2_dflt,
1579         .enable_reg     = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1580         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1581         .clkdm_name     = "l4_per_clkdm",
1582         .parent         = &func_96m_fclk,
1583         .recalc         = &followparent_recalc,
1584 };
1585
1586 static struct clk ipu_fck = {
1587         .name           = "ipu_fck",
1588         .ops            = &clkops_omap2_dflt,
1589         .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1590         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1591         .clkdm_name     = "ducati_clkdm",
1592         .parent         = &ducati_clk_mux_ck,
1593         .recalc         = &followparent_recalc,
1594 };
1595
1596 static struct clk iss_fck = {
1597         .name           = "iss_fck",
1598         .ops            = &clkops_omap2_dflt,
1599         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
1600         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1601         .clkdm_name     = "iss_clkdm",
1602         .parent         = &ducati_clk_mux_ck,
1603         .recalc         = &followparent_recalc,
1604 };
1605
1606 static struct clk iva_fck = {
1607         .name           = "iva_fck",
1608         .ops            = &clkops_omap2_dflt,
1609         .enable_reg     = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1610         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1611         .clkdm_name     = "ivahd_clkdm",
1612         .parent         = &dpll_iva_m5_ck,
1613         .recalc         = &followparent_recalc,
1614 };
1615
1616 static struct clk kbd_fck = {
1617         .name           = "kbd_fck",
1618         .ops            = &clkops_omap2_dflt,
1619         .enable_reg     = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1620         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1621         .clkdm_name     = "l4_wkup_clkdm",
1622         .parent         = &sys_32k_ck,
1623         .recalc         = &followparent_recalc,
1624 };
1625
1626 static struct clk l3_instr_ick = {
1627         .name           = "l3_instr_ick",
1628         .ops            = &clkops_omap2_dflt,
1629         .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1630         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1631         .clkdm_name     = "l3_instr_clkdm",
1632         .parent         = &l3_div_ck,
1633         .recalc         = &followparent_recalc,
1634 };
1635
1636 static struct clk l3_main_3_ick = {
1637         .name           = "l3_main_3_ick",
1638         .ops            = &clkops_omap2_dflt,
1639         .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1640         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1641         .clkdm_name     = "l3_instr_clkdm",
1642         .parent         = &l3_div_ck,
1643         .recalc         = &followparent_recalc,
1644 };
1645
1646 static struct clk mcasp_sync_mux_ck = {
1647         .name           = "mcasp_sync_mux_ck",
1648         .parent         = &abe_24m_fclk,
1649         .clksel         = dmic_sync_mux_sel,
1650         .init           = &omap2_init_clksel_parent,
1651         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1652         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1653         .ops            = &clkops_null,
1654         .recalc         = &omap2_clksel_recalc,
1655 };
1656
1657 static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1658         { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1659         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1660         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1661         { .parent = NULL },
1662 };
1663
1664 /* Merged func_mcasp_abe_gfclk into mcasp */
1665 static struct clk mcasp_fck = {
1666         .name           = "mcasp_fck",
1667         .parent         = &mcasp_sync_mux_ck,
1668         .clksel         = func_mcasp_abe_gfclk_sel,
1669         .init           = &omap2_init_clksel_parent,
1670         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1671         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1672         .ops            = &clkops_omap2_dflt,
1673         .recalc         = &omap2_clksel_recalc,
1674         .enable_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1675         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1676         .clkdm_name     = "abe_clkdm",
1677 };
1678
1679 static struct clk mcbsp1_sync_mux_ck = {
1680         .name           = "mcbsp1_sync_mux_ck",
1681         .parent         = &abe_24m_fclk,
1682         .clksel         = dmic_sync_mux_sel,
1683         .init           = &omap2_init_clksel_parent,
1684         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1685         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1686         .ops            = &clkops_null,
1687         .recalc         = &omap2_clksel_recalc,
1688 };
1689
1690 static const struct clksel func_mcbsp1_gfclk_sel[] = {
1691         { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1692         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1693         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1694         { .parent = NULL },
1695 };
1696
1697 /* Merged func_mcbsp1_gfclk into mcbsp1 */
1698 static struct clk mcbsp1_fck = {
1699         .name           = "mcbsp1_fck",
1700         .parent         = &mcbsp1_sync_mux_ck,
1701         .clksel         = func_mcbsp1_gfclk_sel,
1702         .init           = &omap2_init_clksel_parent,
1703         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1704         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1705         .ops            = &clkops_omap2_dflt,
1706         .recalc         = &omap2_clksel_recalc,
1707         .enable_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1708         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1709         .clkdm_name     = "abe_clkdm",
1710 };
1711
1712 static struct clk mcbsp2_sync_mux_ck = {
1713         .name           = "mcbsp2_sync_mux_ck",
1714         .parent         = &abe_24m_fclk,
1715         .clksel         = dmic_sync_mux_sel,
1716         .init           = &omap2_init_clksel_parent,
1717         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1718         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1719         .ops            = &clkops_null,
1720         .recalc         = &omap2_clksel_recalc,
1721 };
1722
1723 static const struct clksel func_mcbsp2_gfclk_sel[] = {
1724         { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1725         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1726         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1727         { .parent = NULL },
1728 };
1729
1730 /* Merged func_mcbsp2_gfclk into mcbsp2 */
1731 static struct clk mcbsp2_fck = {
1732         .name           = "mcbsp2_fck",
1733         .parent         = &mcbsp2_sync_mux_ck,
1734         .clksel         = func_mcbsp2_gfclk_sel,
1735         .init           = &omap2_init_clksel_parent,
1736         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1737         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1738         .ops            = &clkops_omap2_dflt,
1739         .recalc         = &omap2_clksel_recalc,
1740         .enable_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1741         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1742         .clkdm_name     = "abe_clkdm",
1743 };
1744
1745 static struct clk mcbsp3_sync_mux_ck = {
1746         .name           = "mcbsp3_sync_mux_ck",
1747         .parent         = &abe_24m_fclk,
1748         .clksel         = dmic_sync_mux_sel,
1749         .init           = &omap2_init_clksel_parent,
1750         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1751         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1752         .ops            = &clkops_null,
1753         .recalc         = &omap2_clksel_recalc,
1754 };
1755
1756 static const struct clksel func_mcbsp3_gfclk_sel[] = {
1757         { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1758         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1759         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1760         { .parent = NULL },
1761 };
1762
1763 /* Merged func_mcbsp3_gfclk into mcbsp3 */
1764 static struct clk mcbsp3_fck = {
1765         .name           = "mcbsp3_fck",
1766         .parent         = &mcbsp3_sync_mux_ck,
1767         .clksel         = func_mcbsp3_gfclk_sel,
1768         .init           = &omap2_init_clksel_parent,
1769         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1770         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1771         .ops            = &clkops_omap2_dflt,
1772         .recalc         = &omap2_clksel_recalc,
1773         .enable_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1774         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1775         .clkdm_name     = "abe_clkdm",
1776 };
1777
1778 static struct clk mcbsp4_sync_mux_ck = {
1779         .name           = "mcbsp4_sync_mux_ck",
1780         .parent         = &func_96m_fclk,
1781         .clksel         = mcasp2_fclk_sel,
1782         .init           = &omap2_init_clksel_parent,
1783         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1784         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1785         .ops            = &clkops_null,
1786         .recalc         = &omap2_clksel_recalc,
1787 };
1788
1789 static const struct clksel per_mcbsp4_gfclk_sel[] = {
1790         { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
1791         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1792         { .parent = NULL },
1793 };
1794
1795 /* Merged per_mcbsp4_gfclk into mcbsp4 */
1796 static struct clk mcbsp4_fck = {
1797         .name           = "mcbsp4_fck",
1798         .parent         = &mcbsp4_sync_mux_ck,
1799         .clksel         = per_mcbsp4_gfclk_sel,
1800         .init           = &omap2_init_clksel_parent,
1801         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1802         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
1803         .ops            = &clkops_omap2_dflt,
1804         .recalc         = &omap2_clksel_recalc,
1805         .enable_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1806         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1807         .clkdm_name     = "l4_per_clkdm",
1808 };
1809
1810 static struct clk mcpdm_fck = {
1811         .name           = "mcpdm_fck",
1812         .ops            = &clkops_omap2_dflt,
1813         .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
1814         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1815         .clkdm_name     = "abe_clkdm",
1816         .parent         = &pad_clks_ck,
1817         .recalc         = &followparent_recalc,
1818 };
1819
1820 static struct clk mcspi1_fck = {
1821         .name           = "mcspi1_fck",
1822         .ops            = &clkops_omap2_dflt,
1823         .enable_reg     = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
1824         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1825         .clkdm_name     = "l4_per_clkdm",
1826         .parent         = &func_48m_fclk,
1827         .recalc         = &followparent_recalc,
1828 };
1829
1830 static struct clk mcspi2_fck = {
1831         .name           = "mcspi2_fck",
1832         .ops            = &clkops_omap2_dflt,
1833         .enable_reg     = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
1834         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1835         .clkdm_name     = "l4_per_clkdm",
1836         .parent         = &func_48m_fclk,
1837         .recalc         = &followparent_recalc,
1838 };
1839
1840 static struct clk mcspi3_fck = {
1841         .name           = "mcspi3_fck",
1842         .ops            = &clkops_omap2_dflt,
1843         .enable_reg     = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
1844         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1845         .clkdm_name     = "l4_per_clkdm",
1846         .parent         = &func_48m_fclk,
1847         .recalc         = &followparent_recalc,
1848 };
1849
1850 static struct clk mcspi4_fck = {
1851         .name           = "mcspi4_fck",
1852         .ops            = &clkops_omap2_dflt,
1853         .enable_reg     = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
1854         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1855         .clkdm_name     = "l4_per_clkdm",
1856         .parent         = &func_48m_fclk,
1857         .recalc         = &followparent_recalc,
1858 };
1859
1860 /* Merged hsmmc1_fclk into mmc1 */
1861 static struct clk mmc1_fck = {
1862         .name           = "mmc1_fck",
1863         .parent         = &func_64m_fclk,
1864         .clksel         = hsmmc6_fclk_sel,
1865         .init           = &omap2_init_clksel_parent,
1866         .clksel_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
1867         .clksel_mask    = OMAP4430_CLKSEL_MASK,
1868         .ops            = &clkops_omap2_dflt,
1869         .recalc         = &omap2_clksel_recalc,
1870         .enable_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
1871         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1872         .clkdm_name     = "l3_init_clkdm",
1873 };
1874
1875 /* Merged hsmmc2_fclk into mmc2 */
1876 static struct clk mmc2_fck = {
1877         .name           = "mmc2_fck",
1878         .parent         = &func_64m_fclk,
1879         .clksel         = hsmmc6_fclk_sel,
1880         .init           = &omap2_init_clksel_parent,
1881         .clksel_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
1882         .clksel_mask    = OMAP4430_CLKSEL_MASK,
1883         .ops            = &clkops_omap2_dflt,
1884         .recalc         = &omap2_clksel_recalc,
1885         .enable_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
1886         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1887         .clkdm_name     = "l3_init_clkdm",
1888 };
1889
1890 static struct clk mmc3_fck = {
1891         .name           = "mmc3_fck",
1892         .ops            = &clkops_omap2_dflt,
1893         .enable_reg     = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
1894         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1895         .clkdm_name     = "l4_per_clkdm",
1896         .parent         = &func_48m_fclk,
1897         .recalc         = &followparent_recalc,
1898 };
1899
1900 static struct clk mmc4_fck = {
1901         .name           = "mmc4_fck",
1902         .ops            = &clkops_omap2_dflt,
1903         .enable_reg     = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
1904         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1905         .clkdm_name     = "l4_per_clkdm",
1906         .parent         = &func_48m_fclk,
1907         .recalc         = &followparent_recalc,
1908 };
1909
1910 static struct clk mmc5_fck = {
1911         .name           = "mmc5_fck",
1912         .ops            = &clkops_omap2_dflt,
1913         .enable_reg     = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
1914         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1915         .clkdm_name     = "l4_per_clkdm",
1916         .parent         = &func_48m_fclk,
1917         .recalc         = &followparent_recalc,
1918 };
1919
1920 static struct clk ocp_wp_noc_ick = {
1921         .name           = "ocp_wp_noc_ick",
1922         .ops            = &clkops_omap2_dflt,
1923         .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
1924         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1925         .clkdm_name     = "l3_instr_clkdm",
1926         .parent         = &l3_div_ck,
1927         .recalc         = &followparent_recalc,
1928 };
1929
1930 static struct clk rng_ick = {
1931         .name           = "rng_ick",
1932         .ops            = &clkops_omap2_dflt,
1933         .enable_reg     = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
1934         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1935         .clkdm_name     = "l4_secure_clkdm",
1936         .parent         = &l4_div_ck,
1937         .recalc         = &followparent_recalc,
1938 };
1939
1940 static struct clk sha2md5_fck = {
1941         .name           = "sha2md5_fck",
1942         .ops            = &clkops_omap2_dflt,
1943         .enable_reg     = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
1944         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1945         .clkdm_name     = "l4_secure_clkdm",
1946         .parent         = &l3_div_ck,
1947         .recalc         = &followparent_recalc,
1948 };
1949
1950 static struct clk sl2if_ick = {
1951         .name           = "sl2if_ick",
1952         .ops            = &clkops_omap2_dflt,
1953         .enable_reg     = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
1954         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1955         .clkdm_name     = "ivahd_clkdm",
1956         .parent         = &dpll_iva_m5_ck,
1957         .recalc         = &followparent_recalc,
1958 };
1959
1960 static struct clk slimbus1_fck = {
1961         .name           = "slimbus1_fck",
1962         .ops            = &clkops_omap2_dflt,
1963         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1964         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1965         .clkdm_name     = "abe_clkdm",
1966         .parent         = &ocp_abe_iclk,
1967         .recalc         = &followparent_recalc,
1968 };
1969
1970 static struct clk slimbus2_fck = {
1971         .name           = "slimbus2_fck",
1972         .ops            = &clkops_omap2_dflt,
1973         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1974         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1975         .clkdm_name     = "l4_per_clkdm",
1976         .parent         = &l4_div_ck,
1977         .recalc         = &followparent_recalc,
1978 };
1979
1980 static struct clk smartreflex_core_fck = {
1981         .name           = "smartreflex_core_fck",
1982         .ops            = &clkops_omap2_dflt,
1983         .enable_reg     = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
1984         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1985         .clkdm_name     = "l4_ao_clkdm",
1986         .parent         = &l4_wkup_clk_mux_ck,
1987         .recalc         = &followparent_recalc,
1988 };
1989
1990 static struct clk smartreflex_iva_fck = {
1991         .name           = "smartreflex_iva_fck",
1992         .ops            = &clkops_omap2_dflt,
1993         .enable_reg     = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
1994         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1995         .clkdm_name     = "l4_ao_clkdm",
1996         .parent         = &l4_wkup_clk_mux_ck,
1997         .recalc         = &followparent_recalc,
1998 };
1999
2000 static struct clk smartreflex_mpu_fck = {
2001         .name           = "smartreflex_mpu_fck",
2002         .ops            = &clkops_omap2_dflt,
2003         .enable_reg     = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2004         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2005         .clkdm_name     = "l4_ao_clkdm",
2006         .parent         = &l4_wkup_clk_mux_ck,
2007         .recalc         = &followparent_recalc,
2008 };
2009
2010 /* Merged dmt1_clk_mux into timer1 */
2011 static struct clk timer1_fck = {
2012         .name           = "timer1_fck",
2013         .parent         = &sys_clkin_ck,
2014         .clksel         = abe_dpll_bypass_clk_mux_sel,
2015         .init           = &omap2_init_clksel_parent,
2016         .clksel_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2017         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2018         .ops            = &clkops_omap2_dflt,
2019         .recalc         = &omap2_clksel_recalc,
2020         .enable_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2021         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2022         .clkdm_name     = "l4_wkup_clkdm",
2023 };
2024
2025 /* Merged cm2_dm10_mux into timer10 */
2026 static struct clk timer10_fck = {
2027         .name           = "timer10_fck",
2028         .parent         = &sys_clkin_ck,
2029         .clksel         = abe_dpll_bypass_clk_mux_sel,
2030         .init           = &omap2_init_clksel_parent,
2031         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2032         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2033         .ops            = &clkops_omap2_dflt,
2034         .recalc         = &omap2_clksel_recalc,
2035         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2036         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2037         .clkdm_name     = "l4_per_clkdm",
2038 };
2039
2040 /* Merged cm2_dm11_mux into timer11 */
2041 static struct clk timer11_fck = {
2042         .name           = "timer11_fck",
2043         .parent         = &sys_clkin_ck,
2044         .clksel         = abe_dpll_bypass_clk_mux_sel,
2045         .init           = &omap2_init_clksel_parent,
2046         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2047         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2048         .ops            = &clkops_omap2_dflt,
2049         .recalc         = &omap2_clksel_recalc,
2050         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2051         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2052         .clkdm_name     = "l4_per_clkdm",
2053 };
2054
2055 /* Merged cm2_dm2_mux into timer2 */
2056 static struct clk timer2_fck = {
2057         .name           = "timer2_fck",
2058         .parent         = &sys_clkin_ck,
2059         .clksel         = abe_dpll_bypass_clk_mux_sel,
2060         .init           = &omap2_init_clksel_parent,
2061         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2062         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2063         .ops            = &clkops_omap2_dflt,
2064         .recalc         = &omap2_clksel_recalc,
2065         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2066         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2067         .clkdm_name     = "l4_per_clkdm",
2068 };
2069
2070 /* Merged cm2_dm3_mux into timer3 */
2071 static struct clk timer3_fck = {
2072         .name           = "timer3_fck",
2073         .parent         = &sys_clkin_ck,
2074         .clksel         = abe_dpll_bypass_clk_mux_sel,
2075         .init           = &omap2_init_clksel_parent,
2076         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2077         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2078         .ops            = &clkops_omap2_dflt,
2079         .recalc         = &omap2_clksel_recalc,
2080         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2081         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2082         .clkdm_name     = "l4_per_clkdm",
2083 };
2084
2085 /* Merged cm2_dm4_mux into timer4 */
2086 static struct clk timer4_fck = {
2087         .name           = "timer4_fck",
2088         .parent         = &sys_clkin_ck,
2089         .clksel         = abe_dpll_bypass_clk_mux_sel,
2090         .init           = &omap2_init_clksel_parent,
2091         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2092         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2093         .ops            = &clkops_omap2_dflt,
2094         .recalc         = &omap2_clksel_recalc,
2095         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2096         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2097         .clkdm_name     = "l4_per_clkdm",
2098 };
2099
2100 static const struct clksel timer5_sync_mux_sel[] = {
2101         { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
2102         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
2103         { .parent = NULL },
2104 };
2105
2106 /* Merged timer5_sync_mux into timer5 */
2107 static struct clk timer5_fck = {
2108         .name           = "timer5_fck",
2109         .parent         = &syc_clk_div_ck,
2110         .clksel         = timer5_sync_mux_sel,
2111         .init           = &omap2_init_clksel_parent,
2112         .clksel_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2113         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2114         .ops            = &clkops_omap2_dflt,
2115         .recalc         = &omap2_clksel_recalc,
2116         .enable_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2117         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2118         .clkdm_name     = "abe_clkdm",
2119 };
2120
2121 /* Merged timer6_sync_mux into timer6 */
2122 static struct clk timer6_fck = {
2123         .name           = "timer6_fck",
2124         .parent         = &syc_clk_div_ck,
2125         .clksel         = timer5_sync_mux_sel,
2126         .init           = &omap2_init_clksel_parent,
2127         .clksel_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2128         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2129         .ops            = &clkops_omap2_dflt,
2130         .recalc         = &omap2_clksel_recalc,
2131         .enable_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2132         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2133         .clkdm_name     = "abe_clkdm",
2134 };
2135
2136 /* Merged timer7_sync_mux into timer7 */
2137 static struct clk timer7_fck = {
2138         .name           = "timer7_fck",
2139         .parent         = &syc_clk_div_ck,
2140         .clksel         = timer5_sync_mux_sel,
2141         .init           = &omap2_init_clksel_parent,
2142         .clksel_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2143         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2144         .ops            = &clkops_omap2_dflt,
2145         .recalc         = &omap2_clksel_recalc,
2146         .enable_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2147         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2148         .clkdm_name     = "abe_clkdm",
2149 };
2150
2151 /* Merged timer8_sync_mux into timer8 */
2152 static struct clk timer8_fck = {
2153         .name           = "timer8_fck",
2154         .parent         = &syc_clk_div_ck,
2155         .clksel         = timer5_sync_mux_sel,
2156         .init           = &omap2_init_clksel_parent,
2157         .clksel_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2158         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2159         .ops            = &clkops_omap2_dflt,
2160         .recalc         = &omap2_clksel_recalc,
2161         .enable_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2162         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2163         .clkdm_name     = "abe_clkdm",
2164 };
2165
2166 /* Merged cm2_dm9_mux into timer9 */
2167 static struct clk timer9_fck = {
2168         .name           = "timer9_fck",
2169         .parent         = &sys_clkin_ck,
2170         .clksel         = abe_dpll_bypass_clk_mux_sel,
2171         .init           = &omap2_init_clksel_parent,
2172         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2173         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2174         .ops            = &clkops_omap2_dflt,
2175         .recalc         = &omap2_clksel_recalc,
2176         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2177         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2178         .clkdm_name     = "l4_per_clkdm",
2179 };
2180
2181 static struct clk uart1_fck = {
2182         .name           = "uart1_fck",
2183         .ops            = &clkops_omap2_dflt,
2184         .enable_reg     = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2185         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2186         .clkdm_name     = "l4_per_clkdm",
2187         .parent         = &func_48m_fclk,
2188         .recalc         = &followparent_recalc,
2189 };
2190
2191 static struct clk uart2_fck = {
2192         .name           = "uart2_fck",
2193         .ops            = &clkops_omap2_dflt,
2194         .enable_reg     = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2195         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2196         .clkdm_name     = "l4_per_clkdm",
2197         .parent         = &func_48m_fclk,
2198         .recalc         = &followparent_recalc,
2199 };
2200
2201 static struct clk uart3_fck = {
2202         .name           = "uart3_fck",
2203         .ops            = &clkops_omap2_dflt,
2204         .enable_reg     = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2205         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2206         .clkdm_name     = "l4_per_clkdm",
2207         .parent         = &func_48m_fclk,
2208         .recalc         = &followparent_recalc,
2209 };
2210
2211 static struct clk uart4_fck = {
2212         .name           = "uart4_fck",
2213         .ops            = &clkops_omap2_dflt,
2214         .enable_reg     = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2215         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2216         .clkdm_name     = "l4_per_clkdm",
2217         .parent         = &func_48m_fclk,
2218         .recalc         = &followparent_recalc,
2219 };
2220
2221 static struct clk usb_host_fs_fck = {
2222         .name           = "usb_host_fs_fck",
2223         .ops            = &clkops_omap2_dflt,
2224         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2225         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2226         .clkdm_name     = "l3_init_clkdm",
2227         .parent         = &func_48mc_fclk,
2228         .recalc         = &followparent_recalc,
2229 };
2230
2231 static struct clk usb_host_hs_fck = {
2232         .name           = "usb_host_hs_fck",
2233         .ops            = &clkops_omap2_dflt,
2234         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2235         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2236         .clkdm_name     = "l3_init_clkdm",
2237         .parent         = &init_60m_fclk,
2238         .recalc         = &followparent_recalc,
2239 };
2240
2241 static struct clk usb_otg_hs_ick = {
2242         .name           = "usb_otg_hs_ick",
2243         .ops            = &clkops_omap2_dflt,
2244         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2245         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2246         .clkdm_name     = "l3_init_clkdm",
2247         .parent         = &l3_div_ck,
2248         .recalc         = &followparent_recalc,
2249 };
2250
2251 static struct clk usb_tll_hs_ick = {
2252         .name           = "usb_tll_hs_ick",
2253         .ops            = &clkops_omap2_dflt,
2254         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2255         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2256         .clkdm_name     = "l3_init_clkdm",
2257         .parent         = &l4_div_ck,
2258         .recalc         = &followparent_recalc,
2259 };
2260
2261 static struct clk usim_fck = {
2262         .name           = "usim_fck",
2263         .ops            = &clkops_omap2_dflt,
2264         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2265         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2266         .clkdm_name     = "l4_wkup_clkdm",
2267         .parent         = &sys_32k_ck,
2268         .recalc         = &followparent_recalc,
2269 };
2270
2271 static struct clk wd_timer2_fck = {
2272         .name           = "wd_timer2_fck",
2273         .ops            = &clkops_omap2_dflt,
2274         .enable_reg     = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2275         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2276         .clkdm_name     = "l4_wkup_clkdm",
2277         .parent         = &sys_32k_ck,
2278         .recalc         = &followparent_recalc,
2279 };
2280
2281 static struct clk wd_timer3_fck = {
2282         .name           = "wd_timer3_fck",
2283         .ops            = &clkops_omap2_dflt,
2284         .enable_reg     = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2285         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2286         .clkdm_name     = "abe_clkdm",
2287         .parent         = &sys_32k_ck,
2288         .recalc         = &followparent_recalc,
2289 };
2290
2291 /* Remaining optional clocks */
2292 static const struct clksel otg_60m_gfclk_sel[] = {
2293         { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2294         { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2295         { .parent = NULL },
2296 };
2297
2298 static struct clk otg_60m_gfclk_ck = {
2299         .name           = "otg_60m_gfclk_ck",
2300         .parent         = &utmi_phy_clkout_ck,
2301         .clksel         = otg_60m_gfclk_sel,
2302         .init           = &omap2_init_clksel_parent,
2303         .clksel_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2304         .clksel_mask    = OMAP4430_CLKSEL_60M_MASK,
2305         .ops            = &clkops_null,
2306         .recalc         = &omap2_clksel_recalc,
2307 };
2308
2309 static const struct clksel stm_clk_div_div[] = {
2310         { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2311         { .parent = NULL },
2312 };
2313
2314 static struct clk stm_clk_div_ck = {
2315         .name           = "stm_clk_div_ck",
2316         .parent         = &pmd_stm_clock_mux_ck,
2317         .clksel         = stm_clk_div_div,
2318         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2319         .clksel_mask    = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2320         .ops            = &clkops_null,
2321         .recalc         = &omap2_clksel_recalc,
2322         .round_rate     = &omap2_clksel_round_rate,
2323         .set_rate       = &omap2_clksel_set_rate,
2324 };
2325
2326 static const struct clksel trace_clk_div_div[] = {
2327         { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2328         { .parent = NULL },
2329 };
2330
2331 static struct clk trace_clk_div_ck = {
2332         .name           = "trace_clk_div_ck",
2333         .parent         = &pmd_trace_clk_mux_ck,
2334         .clksel         = trace_clk_div_div,
2335         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2336         .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2337         .ops            = &clkops_null,
2338         .recalc         = &omap2_clksel_recalc,
2339         .round_rate     = &omap2_clksel_round_rate,
2340         .set_rate       = &omap2_clksel_set_rate,
2341 };
2342
2343 static const struct clksel_rate div2_14to18_rates[] = {
2344         { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2345         { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2346         { .div = 0 },
2347 };
2348
2349 static const struct clksel usim_fclk_div[] = {
2350         { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates },
2351         { .parent = NULL },
2352 };
2353
2354 static struct clk usim_fclk = {
2355         .name           = "usim_fclk",
2356         .parent         = &dpll_per_m4_ck,
2357         .clksel         = usim_fclk_div,
2358         .clksel_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2359         .clksel_mask    = OMAP4430_CLKSEL_DIV_MASK,
2360         .ops            = &clkops_null,
2361         .recalc         = &omap2_clksel_recalc,
2362         .round_rate     = &omap2_clksel_round_rate,
2363         .set_rate       = &omap2_clksel_set_rate,
2364 };
2365
2366 static const struct clksel utmi_p1_gfclk_sel[] = {
2367         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2368         { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2369         { .parent = NULL },
2370 };
2371
2372 static struct clk utmi_p1_gfclk_ck = {
2373         .name           = "utmi_p1_gfclk_ck",
2374         .parent         = &init_60m_fclk,
2375         .clksel         = utmi_p1_gfclk_sel,
2376         .init           = &omap2_init_clksel_parent,
2377         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2378         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P1_MASK,
2379         .ops            = &clkops_null,
2380         .recalc         = &omap2_clksel_recalc,
2381 };
2382
2383 static const struct clksel utmi_p2_gfclk_sel[] = {
2384         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2385         { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2386         { .parent = NULL },
2387 };
2388
2389 static struct clk utmi_p2_gfclk_ck = {
2390         .name           = "utmi_p2_gfclk_ck",
2391         .parent         = &init_60m_fclk,
2392         .clksel         = utmi_p2_gfclk_sel,
2393         .init           = &omap2_init_clksel_parent,
2394         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2395         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P2_MASK,
2396         .ops            = &clkops_null,
2397         .recalc         = &omap2_clksel_recalc,
2398 };
2399
2400 /*
2401  * clkdev
2402  */
2403
2404 static struct omap_clk omap44xx_clks[] = {
2405         CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
2406         CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
2407         CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
2408         CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
2409         CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
2410         CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
2411         CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
2412         CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
2413         CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
2414         CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
2415         CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
2416         CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
2417         CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
2418         CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
2419         CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
2420         CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
2421         CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
2422         CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
2423         CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
2424         CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
2425         CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
2426         CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
2427         CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
2428         CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
2429         CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
2430         CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
2431         CLK(NULL,       "dpll_abe_m3_ck",               &dpll_abe_m3_ck,        CK_443X),
2432         CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
2433         CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
2434         CLK(NULL,       "dpll_core_m6_ck",              &dpll_core_m6_ck,       CK_443X),
2435         CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
2436         CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
2437         CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
2438         CLK(NULL,       "dpll_core_m5_ck",              &dpll_core_m5_ck,       CK_443X),
2439         CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
2440         CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
2441         CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
2442         CLK(NULL,       "dpll_core_m4_ck",              &dpll_core_m4_ck,       CK_443X),
2443         CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
2444         CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
2445         CLK(NULL,       "dpll_core_m3_ck",              &dpll_core_m3_ck,       CK_443X),
2446         CLK(NULL,       "dpll_core_m7_ck",              &dpll_core_m7_ck,       CK_443X),
2447         CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
2448         CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
2449         CLK(NULL,       "dpll_iva_m4_ck",               &dpll_iva_m4_ck,        CK_443X),
2450         CLK(NULL,       "dpll_iva_m5_ck",               &dpll_iva_m5_ck,        CK_443X),
2451         CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
2452         CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
2453         CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
2454         CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
2455         CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
2456         CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
2457         CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
2458         CLK(NULL,       "dpll_per_m3_ck",               &dpll_per_m3_ck,        CK_443X),
2459         CLK(NULL,       "dpll_per_m4_ck",               &dpll_per_m4_ck,        CK_443X),
2460         CLK(NULL,       "dpll_per_m5_ck",               &dpll_per_m5_ck,        CK_443X),
2461         CLK(NULL,       "dpll_per_m6_ck",               &dpll_per_m6_ck,        CK_443X),
2462         CLK(NULL,       "dpll_per_m7_ck",               &dpll_per_m7_ck,        CK_443X),
2463         CLK(NULL,       "dpll_unipro_ck",               &dpll_unipro_ck,        CK_443X),
2464         CLK(NULL,       "dpll_unipro_m2x2_ck",          &dpll_unipro_m2x2_ck,   CK_443X),
2465         CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
2466         CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
2467         CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
2468         CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck,        CK_443X),
2469         CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck,     CK_443X),
2470         CLK(NULL,       "func_12m_fclk",                &func_12m_fclk, CK_443X),
2471         CLK(NULL,       "func_24m_clk",                 &func_24m_clk,  CK_443X),
2472         CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk,        CK_443X),
2473         CLK(NULL,       "func_48m_fclk",                &func_48m_fclk, CK_443X),
2474         CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
2475         CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
2476         CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
2477         CLK(NULL,       "hsmmc6_fclk",                  &hsmmc6_fclk,   CK_443X),
2478         CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
2479         CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
2480         CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
2481         CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
2482         CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
2483         CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
2484         CLK(NULL,       "mcasp2_fclk",                  &mcasp2_fclk,   CK_443X),
2485         CLK(NULL,       "mcasp3_fclk",                  &mcasp3_fclk,   CK_443X),
2486         CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
2487         CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
2488         CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
2489         CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
2490         CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
2491         CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
2492         CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
2493         CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
2494         CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
2495         CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
2496         CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
2497         CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
2498         CLK(NULL,       "dss_fck",                      &dss_fck,       CK_443X),
2499         CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
2500         CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
2501         CLK(NULL,       "emif2_fck",                    &emif2_fck,     CK_443X),
2502         CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
2503         CLK(NULL,       "fpka_fck",                     &fpka_fck,      CK_443X),
2504         CLK(NULL,       "gpio1_ick",                    &gpio1_ick,     CK_443X),
2505         CLK(NULL,       "gpio2_ick",                    &gpio2_ick,     CK_443X),
2506         CLK(NULL,       "gpio3_ick",                    &gpio3_ick,     CK_443X),
2507         CLK(NULL,       "gpio4_ick",                    &gpio4_ick,     CK_443X),
2508         CLK(NULL,       "gpio5_ick",                    &gpio5_ick,     CK_443X),
2509         CLK(NULL,       "gpio6_ick",                    &gpio6_ick,     CK_443X),
2510         CLK(NULL,       "gpmc_ick",                     &gpmc_ick,      CK_443X),
2511         CLK(NULL,       "gpu_fck",                      &gpu_fck,       CK_443X),
2512         CLK("omap2_hdq.0",      "fck",                          &hdq1w_fck,     CK_443X),
2513         CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
2514         CLK("i2c_omap.1",       "fck",                          &i2c1_fck,      CK_443X),
2515         CLK("i2c_omap.2",       "fck",                          &i2c2_fck,      CK_443X),
2516         CLK("i2c_omap.3",       "fck",                          &i2c3_fck,      CK_443X),
2517         CLK("i2c_omap.4",       "fck",                          &i2c4_fck,      CK_443X),
2518         CLK(NULL,       "ipu_fck",                      &ipu_fck,       CK_443X),
2519         CLK(NULL,       "iss_fck",                      &iss_fck,       CK_443X),
2520         CLK(NULL,       "iva_fck",                      &iva_fck,       CK_443X),
2521         CLK(NULL,       "kbd_fck",                      &kbd_fck,       CK_443X),
2522         CLK(NULL,       "l3_instr_ick",                 &l3_instr_ick,  CK_443X),
2523         CLK(NULL,       "l3_main_3_ick",                &l3_main_3_ick, CK_443X),
2524         CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
2525         CLK(NULL,       "mcasp_fck",                    &mcasp_fck,     CK_443X),
2526         CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
2527         CLK("omap-mcbsp.1",     "fck",                          &mcbsp1_fck,    CK_443X),
2528         CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
2529         CLK("omap-mcbsp.2",     "fck",                          &mcbsp2_fck,    CK_443X),
2530         CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
2531         CLK("omap-mcbsp.3",     "fck",                          &mcbsp3_fck,    CK_443X),
2532         CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
2533         CLK("omap-mcbsp.4",     "fck",                          &mcbsp4_fck,    CK_443X),
2534         CLK(NULL,       "mcpdm_fck",                    &mcpdm_fck,     CK_443X),
2535         CLK("omap2_mcspi.1",    "fck",                          &mcspi1_fck,    CK_443X),
2536         CLK("omap2_mcspi.2",    "fck",                          &mcspi2_fck,    CK_443X),
2537         CLK("omap2_mcspi.3",    "fck",                          &mcspi3_fck,    CK_443X),
2538         CLK("omap2_mcspi.4",    "fck",                          &mcspi4_fck,    CK_443X),
2539         CLK("mmci-omap-hs.0",   "fck",                          &mmc1_fck,      CK_443X),
2540         CLK("mmci-omap-hs.1",   "fck",                          &mmc2_fck,      CK_443X),
2541         CLK("mmci-omap-hs.2",   "fck",                          &mmc3_fck,      CK_443X),
2542         CLK("mmci-omap-hs.3",   "fck",                          &mmc4_fck,      CK_443X),
2543         CLK("mmci-omap-hs.4",   "fck",                          &mmc5_fck,      CK_443X),
2544         CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
2545         CLK("omap_rng", "ick",                          &rng_ick,       CK_443X),
2546         CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
2547         CLK(NULL,       "sl2if_ick",                    &sl2if_ick,     CK_443X),
2548         CLK(NULL,       "slimbus1_fck",                 &slimbus1_fck,  CK_443X),
2549         CLK(NULL,       "slimbus2_fck",                 &slimbus2_fck,  CK_443X),
2550         CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
2551         CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
2552         CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
2553         CLK(NULL,       "gpt1_fck",                     &timer1_fck,    CK_443X),
2554         CLK(NULL,       "gpt10_fck",                    &timer10_fck,   CK_443X),
2555         CLK(NULL,       "gpt11_fck",                    &timer11_fck,   CK_443X),
2556         CLK(NULL,       "gpt2_fck",                     &timer2_fck,    CK_443X),
2557         CLK(NULL,       "gpt3_fck",                     &timer3_fck,    CK_443X),
2558         CLK(NULL,       "gpt4_fck",                     &timer4_fck,    CK_443X),
2559         CLK(NULL,       "gpt5_fck",                     &timer5_fck,    CK_443X),
2560         CLK(NULL,       "gpt6_fck",                     &timer6_fck,    CK_443X),
2561         CLK(NULL,       "gpt7_fck",                     &timer7_fck,    CK_443X),
2562         CLK(NULL,       "gpt8_fck",                     &timer8_fck,    CK_443X),
2563         CLK(NULL,       "gpt9_fck",                     &timer9_fck,    CK_443X),
2564         CLK(NULL,       "uart1_fck",                    &uart1_fck,     CK_443X),
2565         CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
2566         CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
2567         CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
2568         CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
2569         CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
2570         CLK("musb_hdrc",        "ick",                          &usb_otg_hs_ick,        CK_443X),
2571         CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
2572         CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
2573         CLK("omap_wdt", "fck",                          &wd_timer2_fck, CK_443X),
2574         CLK(NULL,       "wd_timer3_fck",                &wd_timer3_fck, CK_443X),
2575         CLK(NULL,       "otg_60m_gfclk_ck",             &otg_60m_gfclk_ck,      CK_443X),
2576         CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
2577         CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
2578         CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
2579         CLK(NULL,       "utmi_p1_gfclk_ck",             &utmi_p1_gfclk_ck,      CK_443X),
2580         CLK(NULL,       "utmi_p2_gfclk_ck",             &utmi_p2_gfclk_ck,      CK_443X),
2581         CLK(NULL,       "gpio1_dbck",                   &dummy_ck,      CK_443X),
2582         CLK(NULL,       "gpio2_dbck",                   &dummy_ck,      CK_443X),
2583         CLK(NULL,       "gpio3_dbck",                   &dummy_ck,      CK_443X),
2584         CLK(NULL,       "gpio4_dbck",                   &dummy_ck,      CK_443X),
2585         CLK(NULL,       "gpio5_dbck",                   &dummy_ck,      CK_443X),
2586         CLK(NULL,       "gpio6_dbck",                   &dummy_ck,      CK_443X),
2587         CLK(NULL,       "gpmc_ck",                      &dummy_ck,      CK_443X),
2588         CLK(NULL,       "gpt1_ick",                     &dummy_ck,      CK_443X),
2589         CLK(NULL,       "gpt2_ick",                     &dummy_ck,      CK_443X),
2590         CLK(NULL,       "gpt3_ick",                     &dummy_ck,      CK_443X),
2591         CLK(NULL,       "gpt4_ick",                     &dummy_ck,      CK_443X),
2592         CLK(NULL,       "gpt5_ick",                     &dummy_ck,      CK_443X),
2593         CLK(NULL,       "gpt6_ick",                     &dummy_ck,      CK_443X),
2594         CLK(NULL,       "gpt7_ick",                     &dummy_ck,      CK_443X),
2595         CLK(NULL,       "gpt8_ick",                     &dummy_ck,      CK_443X),
2596         CLK(NULL,       "gpt9_ick",                     &dummy_ck,      CK_443X),
2597         CLK(NULL,       "gpt10_ick",                    &dummy_ck,      CK_443X),
2598         CLK(NULL,       "gpt11_ick",                    &dummy_ck,      CK_443X),
2599         CLK("i2c_omap.1",       "ick",                          &dummy_ck,      CK_443X),
2600         CLK("i2c_omap.2",       "ick",                          &dummy_ck,      CK_443X),
2601         CLK("i2c_omap.3",       "ick",                          &dummy_ck,      CK_443X),
2602         CLK("i2c_omap.4",       "ick",                          &dummy_ck,      CK_443X),
2603         CLK("mmci-omap-hs.0",   "ick",                          &dummy_ck,      CK_443X),
2604         CLK("mmci-omap-hs.1",   "ick",                          &dummy_ck,      CK_443X),
2605         CLK("mmci-omap-hs.2",   "ick",                          &dummy_ck,      CK_443X),
2606         CLK("mmci-omap-hs.3",   "ick",                          &dummy_ck,      CK_443X),
2607         CLK("mmci-omap-hs.4",   "ick",                          &dummy_ck,      CK_443X),
2608         CLK("omap-mcbsp.1",     "ick",                          &dummy_ck,      CK_443X),
2609         CLK("omap-mcbsp.2",     "ick",                          &dummy_ck,      CK_443X),
2610         CLK("omap-mcbsp.3",     "ick",                          &dummy_ck,      CK_443X),
2611         CLK("omap-mcbsp.4",     "ick",                          &dummy_ck,      CK_443X),
2612         CLK("omap2_mcspi.1",    "ick",                          &dummy_ck,      CK_443X),
2613         CLK("omap2_mcspi.2",    "ick",                          &dummy_ck,      CK_443X),
2614         CLK("omap2_mcspi.3",    "ick",                          &dummy_ck,      CK_443X),
2615         CLK("omap2_mcspi.4",    "ick",                          &dummy_ck,      CK_443X),
2616         CLK(NULL,       "uart1_ick",                    &dummy_ck,      CK_443X),
2617         CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
2618         CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
2619         CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
2620         CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
2621 };
2622
2623 int __init omap4xxx_clk_init(void)
2624 {
2625         struct omap_clk *c;
2626         u32 cpu_clkflg;
2627
2628         if (cpu_is_omap44xx()) {
2629                 cpu_mask = RATE_IN_4430;
2630                 cpu_clkflg = CK_443X;
2631         }
2632
2633         clk_init(&omap2_clk_functions);
2634
2635         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
2636                                                                           c++)
2637                 clk_preinit(c->lk.clk);
2638
2639         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
2640                                                                           c++)
2641                 if (c->cpu & cpu_clkflg) {
2642                         clkdev_add(&c->lk);
2643                         clk_register(c->lk.clk);
2644                         omap2_init_clk_clkdm(c->lk.clk);
2645                 }
2646
2647         recalculate_root_clocks();
2648
2649         /*
2650          * Only enable those clocks we will need, let the drivers
2651          * enable other clocks as necessary
2652          */
2653         clk_enable_init_clocks();
2654
2655         return 0;
2656 }