arch/arm/mach-omap2/gpmc.c

   1 /*
   2  * GPMC support functions
   3  *
   4  * Copyright (C) 2005-2006 Nokia Corporation
   5  *
   6  * Author: Juha Yrjola
   7  *
   8  * Copyright (C) 2009 Texas Instruments
   9  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #undef DEBUG
  16
  17 #include <linux/irq.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/err.h>
  21 #include <linux/clk.h>
  22 #include <linux/ioport.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/io.h>
  25 #include <linux/module.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/of.h>
  29 #include <linux/of_mtd.h>
  30 #include <linux/of_device.h>
  31 #include <linux/mtd/nand.h>
  32
  33 #include <linux/platform_data/mtd-nand-omap2.h>
  34
  35 #include <asm/mach-types.h>
  36
  37 #include "soc.h"
  38 #include "common.h"
  39 #include "omap_device.h"
  40 #include "gpmc.h"
  41 #include "gpmc-nand.h"
  42
  43 #define DEVICE_NAME             "omap-gpmc"
  44
  45 /* GPMC register offsets */
  46 #define GPMC_REVISION           0x00
  47 #define GPMC_SYSCONFIG          0x10
  48 #define GPMC_SYSSTATUS          0x14
  49 #define GPMC_IRQSTATUS          0x18
  50 #define GPMC_IRQENABLE          0x1c
  51 #define GPMC_TIMEOUT_CONTROL    0x40
  52 #define GPMC_ERR_ADDRESS        0x44
  53 #define GPMC_ERR_TYPE           0x48
  54 #define GPMC_CONFIG             0x50
  55 #define GPMC_STATUS             0x54
  56 #define GPMC_PREFETCH_CONFIG1   0x1e0
  57 #define GPMC_PREFETCH_CONFIG2   0x1e4
  58 #define GPMC_PREFETCH_CONTROL   0x1ec
  59 #define GPMC_PREFETCH_STATUS    0x1f0
  60 #define GPMC_ECC_CONFIG         0x1f4
  61 #define GPMC_ECC_CONTROL        0x1f8
  62 #define GPMC_ECC_SIZE_CONFIG    0x1fc
  63 #define GPMC_ECC1_RESULT        0x200
  64 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
  65 #define GPMC_ECC_BCH_RESULT_1   0x244   /* not available on OMAP2 */
  66 #define GPMC_ECC_BCH_RESULT_2   0x248   /* not available on OMAP2 */
  67 #define GPMC_ECC_BCH_RESULT_3   0x24c   /* not available on OMAP2 */
  68
  69 /* GPMC ECC control settings */
  70 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
  71 #define GPMC_ECC_CTRL_ECCDISABLE        0x000
  72 #define GPMC_ECC_CTRL_ECCREG1           0x001
  73 #define GPMC_ECC_CTRL_ECCREG2           0x002
  74 #define GPMC_ECC_CTRL_ECCREG3           0x003
  75 #define GPMC_ECC_CTRL_ECCREG4           0x004
  76 #define GPMC_ECC_CTRL_ECCREG5           0x005
  77 #define GPMC_ECC_CTRL_ECCREG6           0x006
  78 #define GPMC_ECC_CTRL_ECCREG7           0x007
  79 #define GPMC_ECC_CTRL_ECCREG8           0x008
  80 #define GPMC_ECC_CTRL_ECCREG9           0x009
  81
  82 #define GPMC_CONFIG2_CSEXTRADELAY               BIT(7)
  83 #define GPMC_CONFIG3_ADVEXTRADELAY              BIT(7)
  84 #define GPMC_CONFIG4_OEEXTRADELAY               BIT(7)
  85 #define GPMC_CONFIG4_WEEXTRADELAY               BIT(23)
  86 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN        BIT(6)
  87 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN        BIT(7)
  88
  89 #define GPMC_CS0_OFFSET         0x60
  90 #define GPMC_CS_SIZE            0x30
  91 #define GPMC_BCH_SIZE           0x10
  92
  93 #define GPMC_MEM_START          0x00000000
  94 #define GPMC_MEM_END            0x3FFFFFFF
  95 #define BOOT_ROM_SPACE          0x100000        /* 1MB */
  96
  97 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
  98 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
  99
 100 #define CS_NUM_SHIFT            24
 101 #define ENABLE_PREFETCH         (0x1 << 7)
 102 #define DMA_MPU_MODE            2
 103
 104 #define GPMC_REVISION_MAJOR(l)          ((l >> 4) & 0xf)
 105 #define GPMC_REVISION_MINOR(l)          (l & 0xf)
 106
 107 #define GPMC_HAS_WR_ACCESS              0x1
 108 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
 109
 110 /* XXX: Only NAND irq has been considered,currently these are the only ones used
 111  */
 112 #define GPMC_NR_IRQ             2
 113
 114 struct gpmc_client_irq  {
 115         unsigned                irq;
 116         u32                     bitmask;
 117 };
 118
 119 /* Structure to save gpmc cs context */
 120 struct gpmc_cs_config {
 121         u32 config1;
 122         u32 config2;
 123         u32 config3;
 124         u32 config4;
 125         u32 config5;
 126         u32 config6;
 127         u32 config7;
 128         int is_valid;
 129 };
 130
 131 /*
 132  * Structure to save/restore gpmc context
 133  * to support core off on OMAP3
 134  */
 135 struct omap3_gpmc_regs {
 136         u32 sysconfig;
 137         u32 irqenable;
 138         u32 timeout_ctrl;
 139         u32 config;
 140         u32 prefetch_config1;
 141         u32 prefetch_config2;
 142         u32 prefetch_control;
 143         struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 144 };
 145
 146 static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
 147 static struct irq_chip gpmc_irq_chip;
 148 static unsigned gpmc_irq_start;
 149
 150 static struct resource  gpmc_mem_root;
 151 static struct resource  gpmc_cs_mem[GPMC_CS_NUM];
 152 static DEFINE_SPINLOCK(gpmc_mem_lock);
 153 static unsigned int gpmc_cs_map;        /* flag for cs which are initialized */
 154 static struct device *gpmc_dev;
 155 static int gpmc_irq;
 156 static resource_size_t phys_base, mem_size;
 157 static unsigned gpmc_capability;
 158 static void __iomem *gpmc_base;
 159
 160 static struct clk *gpmc_l3_clk;
 161
 162 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 163
 164 static void gpmc_write_reg(int idx, u32 val)
 165 {
 166         __raw_writel(val, gpmc_base + idx);
 167 }
 168
 169 static u32 gpmc_read_reg(int idx)
 170 {
 171         return __raw_readl(gpmc_base + idx);
 172 }
 173
 174 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 175 {
 176         void __iomem *reg_addr;
 177
 178         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 179         __raw_writel(val, reg_addr);
 180 }
 181
 182 u32 gpmc_cs_read_reg(int cs, int idx)
 183 {
 184         void __iomem *reg_addr;
 185
 186         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 187         return __raw_readl(reg_addr);
 188 }
 189
 190 /* TODO: Add support for gpmc_fck to clock framework and use it */
 191 unsigned long gpmc_get_fclk_period(void)
 192 {
 193         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 194
 195         if (rate == 0) {
 196                 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
 197                 return 0;
 198         }
 199
 200         rate /= 1000;
 201         rate = 1000000000 / rate;       /* In picoseconds */
 202
 203         return rate;
 204 }
 205
 206 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 207 {
 208         unsigned long tick_ps;
 209
 210         /* Calculate in picosecs to yield more exact results */
 211         tick_ps = gpmc_get_fclk_period();
 212
 213         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 214 }
 215
 216 unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 217 {
 218         unsigned long tick_ps;
 219
 220         /* Calculate in picosecs to yield more exact results */
 221         tick_ps = gpmc_get_fclk_period();
 222
 223         return (time_ps + tick_ps - 1) / tick_ps;
 224 }
 225
 226 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 227 {
 228         return ticks * gpmc_get_fclk_period() / 1000;
 229 }
 230
 231 unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
 232 {
 233         unsigned long ticks = gpmc_ns_to_ticks(time_ns);
 234
 235         return ticks * gpmc_get_fclk_period() / 1000;
 236 }
 237
 238 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 239 {
 240         return ticks * gpmc_get_fclk_period();
 241 }
 242
 243 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
 244 {
 245         unsigned long ticks = gpmc_ps_to_ticks(time_ps);
 246
 247         return ticks * gpmc_get_fclk_period();
 248 }
 249
 250 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
 251 {
 252         u32 l;
 253
 254         l = gpmc_cs_read_reg(cs, reg);
 255         if (value)
 256                 l |= mask;
 257         else
 258                 l &= ~mask;
 259         gpmc_cs_write_reg(cs, reg, l);
 260 }
 261
 262 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 263 {
 264         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
 265                            GPMC_CONFIG1_TIME_PARA_GRAN,
 266                            p->time_para_granularity);
 267         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
 268                            GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
 269         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
 270                            GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
 271         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 272                            GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
 273         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 274                            GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
 275         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 276                            GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
 277                            p->cycle2cyclesamecsen);
 278         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 279                            GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
 280                            p->cycle2cyclediffcsen);
 281 }
 282
 283 #ifdef DEBUG
 284 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
 285                                int time, const char *name)
 286 #else
 287 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
 288                                int time)
 289 #endif
 290 {
 291         u32 l;
 292         int ticks, mask, nr_bits;
 293
 294         if (time == 0)
 295                 ticks = 0;
 296         else
 297                 ticks = gpmc_ns_to_ticks(time);
 298         nr_bits = end_bit - st_bit + 1;
 299         if (ticks >= 1 << nr_bits) {
 300 #ifdef DEBUG
 301                 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
 302                                 cs, name, time, ticks, 1 << nr_bits);
 303 #endif
 304                 return -1;
 305         }
 306
 307         mask = (1 << nr_bits) - 1;
 308         l = gpmc_cs_read_reg(cs, reg);
 309 #ifdef DEBUG
 310         printk(KERN_INFO
 311                 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 312                cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
 313                         (l >> st_bit) & mask, time);
 314 #endif
 315         l &= ~(mask << st_bit);
 316         l |= ticks << st_bit;
 317         gpmc_cs_write_reg(cs, reg, l);
 318
 319         return 0;
 320 }
 321
 322 #ifdef DEBUG
 323 #define GPMC_SET_ONE(reg, st, end, field) \
 324         if (set_gpmc_timing_reg(cs, (reg), (st), (end),         \
 325                         t->field, #field) < 0)                  \
 326                 return -1
 327 #else
 328 #define GPMC_SET_ONE(reg, st, end, field) \
 329         if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
 330                 return -1
 331 #endif
 332
 333 int gpmc_calc_divider(unsigned int sync_clk)
 334 {
 335         int div;
 336         u32 l;
 337
 338         l = sync_clk + (gpmc_get_fclk_period() - 1);
 339         div = l / gpmc_get_fclk_period();
 340         if (div > 4)
 341                 return -1;
 342         if (div <= 0)
 343                 div = 1;
 344
 345         return div;
 346 }
 347
 348 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 349 {
 350         int div;
 351         u32 l;
 352
 353         div = gpmc_calc_divider(t->sync_clk);
 354         if (div < 0)
 355                 return div;
 356
 357         GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
 358         GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
 359         GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
 360
 361         GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
 362         GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
 363         GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
 364
 365         GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
 366         GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
 367         GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
 368         GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
 369
 370         GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
 371         GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
 372         GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
 373
 374         GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 375
 376         GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
 377         GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
 378
 379         GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring);
 380         GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation);
 381
 382         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
 383                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
 384         if (gpmc_capability & GPMC_HAS_WR_ACCESS)
 385                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
 386
 387         /* caller is expected to have initialized CONFIG1 to cover
 388          * at least sync vs async
 389          */
 390         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 391         if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
 392 #ifdef DEBUG
 393                 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
 394                                 cs, (div * gpmc_get_fclk_period()) / 1000, div);
 395 #endif
 396                 l &= ~0x03;
 397                 l |= (div - 1);
 398                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 399         }
 400
 401         gpmc_cs_bool_timings(cs, &t->bool_timings);
 402
 403         return 0;
 404 }
 405
 406 static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
 407 {
 408         u32 l;
 409         u32 mask;
 410
 411         mask = (1 << GPMC_SECTION_SHIFT) - size;
 412         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 413         l &= ~0x3f;
 414         l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
 415         l &= ~(0x0f << 8);
 416         l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
 417         l |= GPMC_CONFIG7_CSVALID;
 418         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 419 }
 420
 421 static void gpmc_cs_disable_mem(int cs)
 422 {
 423         u32 l;
 424
 425         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 426         l &= ~GPMC_CONFIG7_CSVALID;
 427         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 428 }
 429
 430 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 431 {
 432         u32 l;
 433         u32 mask;
 434
 435         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 436         *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
 437         mask = (l >> 8) & 0x0f;
 438         *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
 439 }
 440
 441 static int gpmc_cs_mem_enabled(int cs)
 442 {
 443         u32 l;
 444
 445         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 446         return l & GPMC_CONFIG7_CSVALID;
 447 }
 448
 449 int gpmc_cs_set_reserved(int cs, int reserved)
 450 {
 451         if (cs > GPMC_CS_NUM)
 452                 return -ENODEV;
 453
 454         gpmc_cs_map &= ~(1 << cs);
 455         gpmc_cs_map |= (reserved ? 1 : 0) << cs;
 456
 457         return 0;
 458 }
 459
 460 int gpmc_cs_reserved(int cs)
 461 {
 462         if (cs > GPMC_CS_NUM)
 463                 return -ENODEV;
 464
 465         return gpmc_cs_map & (1 << cs);
 466 }
 467
 468 static unsigned long gpmc_mem_align(unsigned long size)
 469 {
 470         int order;
 471
 472         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 473         order = GPMC_CHUNK_SHIFT - 1;
 474         do {
 475                 size >>= 1;
 476                 order++;
 477         } while (size);
 478         size = 1 << order;
 479         return size;
 480 }
 481
 482 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 483 {
 484         struct resource *res = &gpmc_cs_mem[cs];
 485         int r;
 486
 487         size = gpmc_mem_align(size);
 488         spin_lock(&gpmc_mem_lock);
 489         res->start = base;
 490         res->end = base + size - 1;
 491         r = request_resource(&gpmc_mem_root, res);
 492         spin_unlock(&gpmc_mem_lock);
 493
 494         return r;
 495 }
 496
 497 static int gpmc_cs_delete_mem(int cs)
 498 {
 499         struct resource *res = &gpmc_cs_mem[cs];
 500         int r;
 501
 502         spin_lock(&gpmc_mem_lock);
 503         r = release_resource(&gpmc_cs_mem[cs]);
 504         res->start = 0;
 505         res->end = 0;
 506         spin_unlock(&gpmc_mem_lock);
 507
 508         return r;
 509 }
 510
 511 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 512 {
 513         struct resource *res = &gpmc_cs_mem[cs];
 514         int r = -1;
 515
 516         if (cs > GPMC_CS_NUM)
 517                 return -ENODEV;
 518
 519         size = gpmc_mem_align(size);
 520         if (size > (1 << GPMC_SECTION_SHIFT))
 521                 return -ENOMEM;
 522
 523         spin_lock(&gpmc_mem_lock);
 524         if (gpmc_cs_reserved(cs)) {
 525                 r = -EBUSY;
 526                 goto out;
 527         }
 528         if (gpmc_cs_mem_enabled(cs))
 529                 r = adjust_resource(res, res->start & ~(size - 1), size);
 530         if (r < 0)
 531                 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
 532                                       size, NULL, NULL);
 533         if (r < 0)
 534                 goto out;
 535
 536         gpmc_cs_enable_mem(cs, res->start, resource_size(res));
 537         *base = res->start;
 538         gpmc_cs_set_reserved(cs, 1);
 539 out:
 540         spin_unlock(&gpmc_mem_lock);
 541         return r;
 542 }
 543 EXPORT_SYMBOL(gpmc_cs_request);
 544
 545 void gpmc_cs_free(int cs)
 546 {
 547         spin_lock(&gpmc_mem_lock);
 548         if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
 549                 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
 550                 BUG();
 551                 spin_unlock(&gpmc_mem_lock);
 552                 return;
 553         }
 554         gpmc_cs_disable_mem(cs);
 555         release_resource(&gpmc_cs_mem[cs]);
 556         gpmc_cs_set_reserved(cs, 0);
 557         spin_unlock(&gpmc_mem_lock);
 558 }
 559 EXPORT_SYMBOL(gpmc_cs_free);
 560
 561 /**
 562  * gpmc_cs_configure - write request to configure gpmc
 563  * @cs: chip select number
 564  * @cmd: command type
 565  * @wval: value to write
 566  * @return status of the operation
 567  */
 568 int gpmc_cs_configure(int cs, int cmd, int wval)
 569 {
 570         int err = 0;
 571         u32 regval = 0;
 572
 573         switch (cmd) {
 574         case GPMC_ENABLE_IRQ:
 575                 gpmc_write_reg(GPMC_IRQENABLE, wval);
 576                 break;
 577
 578         case GPMC_SET_IRQ_STATUS:
 579                 gpmc_write_reg(GPMC_IRQSTATUS, wval);
 580                 break;
 581
 582         case GPMC_CONFIG_WP:
 583                 regval = gpmc_read_reg(GPMC_CONFIG);
 584                 if (wval)
 585                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
 586                 else
 587                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
 588                 gpmc_write_reg(GPMC_CONFIG, regval);
 589                 break;
 590
 591         case GPMC_CONFIG_RDY_BSY:
 592                 regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 593                 if (wval)
 594                         regval |= WR_RD_PIN_MONITORING;
 595                 else
 596                         regval &= ~WR_RD_PIN_MONITORING;
 597                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
 598                 break;
 599
 600         case GPMC_CONFIG_DEV_SIZE:
 601                 regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 602
 603                 /* clear 2 target bits */
 604                 regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
 605
 606                 /* set the proper value */
 607                 regval |= GPMC_CONFIG1_DEVICESIZE(wval);
 608
 609                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
 610                 break;
 611
 612         case GPMC_CONFIG_DEV_TYPE:
 613                 regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 614                 regval |= GPMC_CONFIG1_DEVICETYPE(wval);
 615                 if (wval == GPMC_DEVICETYPE_NOR)
 616                         regval |= GPMC_CONFIG1_MUXADDDATA;
 617                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
 618                 break;
 619
 620         default:
 621                 printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
 622                 err = -EINVAL;
 623         }
 624
 625         return err;
 626 }
 627 EXPORT_SYMBOL(gpmc_cs_configure);
 628
 629 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
 630 {
 631         int i;
 632
 633         reg->gpmc_status = gpmc_base + GPMC_STATUS;
 634         reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
 635                                 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
 636         reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
 637                                 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
 638         reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
 639                                 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
 640         reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
 641         reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
 642         reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
 643         reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
 644         reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
 645         reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
 646         reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
 647         reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
 648
 649         for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
 650                 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
 651                                            GPMC_BCH_SIZE * i;
 652                 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
 653                                            GPMC_BCH_SIZE * i;
 654                 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
 655                                            GPMC_BCH_SIZE * i;
 656                 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
 657                                            GPMC_BCH_SIZE * i;
 658         }
 659 }
 660
 661 int gpmc_get_client_irq(unsigned irq_config)
 662 {
 663         int i;
 664
 665         if (hweight32(irq_config) > 1)
 666                 return 0;
 667
 668         for (i = 0; i < GPMC_NR_IRQ; i++)
 669                 if (gpmc_client_irq[i].bitmask & irq_config)
 670                         return gpmc_client_irq[i].irq;
 671
 672         return 0;
 673 }
 674
 675 static int gpmc_irq_endis(unsigned irq, bool endis)
 676 {
 677         int i;
 678         u32 regval;
 679
 680         for (i = 0; i < GPMC_NR_IRQ; i++)
 681                 if (irq == gpmc_client_irq[i].irq) {
 682                         regval = gpmc_read_reg(GPMC_IRQENABLE);
 683                         if (endis)
 684                                 regval |= gpmc_client_irq[i].bitmask;
 685                         else
 686                                 regval &= ~gpmc_client_irq[i].bitmask;
 687                         gpmc_write_reg(GPMC_IRQENABLE, regval);
 688                         break;
 689                 }
 690
 691         return 0;
 692 }
 693
 694 static void gpmc_irq_disable(struct irq_data *p)
 695 {
 696         gpmc_irq_endis(p->irq, false);
 697 }
 698
 699 static void gpmc_irq_enable(struct irq_data *p)
 700 {
 701         gpmc_irq_endis(p->irq, true);
 702 }
 703
 704 static void gpmc_irq_noop(struct irq_data *data) { }
 705
 706 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
 707
 708 static int gpmc_setup_irq(void)
 709 {
 710         int i;
 711         u32 regval;
 712
 713         if (!gpmc_irq)
 714                 return -EINVAL;
 715
 716         gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
 717         if (IS_ERR_VALUE(gpmc_irq_start)) {
 718                 pr_err("irq_alloc_descs failed\n");
 719                 return gpmc_irq_start;
 720         }
 721
 722         gpmc_irq_chip.name = "gpmc";
 723         gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
 724         gpmc_irq_chip.irq_enable = gpmc_irq_enable;
 725         gpmc_irq_chip.irq_disable = gpmc_irq_disable;
 726         gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
 727         gpmc_irq_chip.irq_ack = gpmc_irq_noop;
 728         gpmc_irq_chip.irq_mask = gpmc_irq_noop;
 729         gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
 730
 731         gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
 732         gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
 733
 734         for (i = 0; i < GPMC_NR_IRQ; i++) {
 735                 gpmc_client_irq[i].irq = gpmc_irq_start + i;
 736                 irq_set_chip_and_handler(gpmc_client_irq[i].irq,
 737                                         &gpmc_irq_chip, handle_simple_irq);
 738                 set_irq_flags(gpmc_client_irq[i].irq,
 739                                 IRQF_VALID | IRQF_NOAUTOEN);
 740         }
 741
 742         /* Disable interrupts */
 743         gpmc_write_reg(GPMC_IRQENABLE, 0);
 744
 745         /* clear interrupts */
 746         regval = gpmc_read_reg(GPMC_IRQSTATUS);
 747         gpmc_write_reg(GPMC_IRQSTATUS, regval);
 748
 749         return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
 750 }
 751
 752 static int gpmc_free_irq(void)
 753 {
 754         int i;
 755
 756         if (gpmc_irq)
 757                 free_irq(gpmc_irq, NULL);
 758
 759         for (i = 0; i < GPMC_NR_IRQ; i++) {
 760                 irq_set_handler(gpmc_client_irq[i].irq, NULL);
 761                 irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
 762                 irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
 763         }
 764
 765         irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
 766
 767         return 0;
 768 }
 769
 770 static void gpmc_mem_exit(void)
 771 {
 772         int cs;
 773
 774         for (cs = 0; cs < GPMC_CS_NUM; cs++) {
 775                 if (!gpmc_cs_mem_enabled(cs))
 776                         continue;
 777                 gpmc_cs_delete_mem(cs);
 778         }
 779
 780 }
 781
 782 static int gpmc_mem_init(void)
 783 {
 784         int cs, rc;
 785         unsigned long boot_rom_space = 0;
 786
 787         /* never allocate the first page, to facilitate bug detection;
 788          * even if we didn't boot from ROM.
 789          */
 790         boot_rom_space = BOOT_ROM_SPACE;
 791         /* In apollon the CS0 is mapped as 0x0000 0000 */
 792         if (machine_is_omap_apollon())
 793                 boot_rom_space = 0;
 794         gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
 795         gpmc_mem_root.end = GPMC_MEM_END;
 796
 797         /* Reserve all regions that has been set up by bootloader */
 798         for (cs = 0; cs < GPMC_CS_NUM; cs++) {
 799                 u32 base, size;
 800
 801                 if (!gpmc_cs_mem_enabled(cs))
 802                         continue;
 803                 gpmc_cs_get_memconf(cs, &base, &size);
 804                 rc = gpmc_cs_insert_mem(cs, base, size);
 805                 if (IS_ERR_VALUE(rc)) {
 806                         while (--cs >= 0)
 807                                 if (gpmc_cs_mem_enabled(cs))
 808                                         gpmc_cs_delete_mem(cs);
 809                         return rc;
 810                 }
 811         }
 812
 813         return 0;
 814 }
 815
 816 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
 817 {
 818         u32 temp;
 819         int div;
 820
 821         div = gpmc_calc_divider(sync_clk);
 822         temp = gpmc_ps_to_ticks(time_ps);
 823         temp = (temp + div - 1) / div;
 824         return gpmc_ticks_to_ps(temp * div);
 825 }
 826
 827 /* XXX: can the cycles be avoided ? */
 828 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
 829                                 struct gpmc_device_timings *dev_t)
 830 {
 831         bool mux = dev_t->mux;
 832         u32 temp;
 833
 834         /* adv_rd_off */
 835         temp = dev_t->t_avdp_r;
 836         /* XXX: mux check required ? */
 837         if (mux) {
 838                 /* XXX: t_avdp not to be required for sync, only added for tusb
 839                  * this indirectly necessitates requirement of t_avdp_r and
 840                  * t_avdp_w instead of having a single t_avdp
 841                  */
 842                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
 843                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
 844         }
 845         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
 846
 847         /* oe_on */
 848         temp = dev_t->t_oeasu; /* XXX: remove this ? */
 849         if (mux) {
 850                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
 851                 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
 852                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
 853         }
 854         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
 855
 856         /* access */
 857         /* XXX: any scope for improvement ?, by combining oe_on
 858          * and clk_activation, need to check whether
 859          * access = clk_activation + round to sync clk ?
 860          */
 861         temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
 862         temp += gpmc_t->clk_activation;
 863         if (dev_t->cyc_oe)
 864                 temp = max_t(u32, temp, gpmc_t->oe_on +
 865                                 gpmc_ticks_to_ps(dev_t->cyc_oe));
 866         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
 867
 868         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
 869         gpmc_t->cs_rd_off = gpmc_t->oe_off;
 870
 871         /* rd_cycle */
 872         temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
 873         temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
 874                                                         gpmc_t->access;
 875         /* XXX: barter t_ce_rdyz with t_cez_r ? */
 876         if (dev_t->t_ce_rdyz)
 877                 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
 878         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
 879
 880         return 0;
 881 }
 882
 883 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
 884                                 struct gpmc_device_timings *dev_t)
 885 {
 886         bool mux = dev_t->mux;
 887         u32 temp;
 888
 889         /* adv_wr_off */
 890         temp = dev_t->t_avdp_w;
 891         if (mux) {
 892                 temp = max_t(u32, temp,
 893                         gpmc_t->clk_activation + dev_t->t_avdh);
 894                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
 895         }
 896         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
 897
 898         /* wr_data_mux_bus */
 899         temp = max_t(u32, dev_t->t_weasu,
 900                         gpmc_t->clk_activation + dev_t->t_rdyo);
 901         /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
 902          * and in that case remember to handle we_on properly
 903          */
 904         if (mux) {
 905                 temp = max_t(u32, temp,
 906                         gpmc_t->adv_wr_off + dev_t->t_aavdh);
 907                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
 908                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
 909         }
 910         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
 911
 912         /* we_on */
 913         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
 914                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
 915         else
 916                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
 917
 918         /* wr_access */
 919         /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
 920         gpmc_t->wr_access = gpmc_t->access;
 921
 922         /* we_off */
 923         temp = gpmc_t->we_on + dev_t->t_wpl;
 924         temp = max_t(u32, temp,
 925                         gpmc_t->wr_access + gpmc_ticks_to_ps(1));
 926         temp = max_t(u32, temp,
 927                 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
 928         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
 929
 930         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
 931                                                         dev_t->t_wph);
 932
 933         /* wr_cycle */
 934         temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
 935         temp += gpmc_t->wr_access;
 936         /* XXX: barter t_ce_rdyz with t_cez_w ? */
 937         if (dev_t->t_ce_rdyz)
 938                 temp = max_t(u32, temp,
 939                                  gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
 940         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
 941
 942         return 0;
 943 }
 944
 945 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
 946                                 struct gpmc_device_timings *dev_t)
 947 {
 948         bool mux = dev_t->mux;
 949         u32 temp;
 950
 951         /* adv_rd_off */
 952         temp = dev_t->t_avdp_r;
 953         if (mux)
 954                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
 955         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
 956
 957         /* oe_on */
 958         temp = dev_t->t_oeasu;
 959         if (mux)
 960                 temp = max_t(u32, temp,
 961                         gpmc_t->adv_rd_off + dev_t->t_aavdh);
 962         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
 963
 964         /* access */
 965         temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
 966                                 gpmc_t->oe_on + dev_t->t_oe);
 967         temp = max_t(u32, temp,
 968                                 gpmc_t->cs_on + dev_t->t_ce);
 969         temp = max_t(u32, temp,
 970                                 gpmc_t->adv_on + dev_t->t_aa);
 971         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
 972
 973         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
 974         gpmc_t->cs_rd_off = gpmc_t->oe_off;
 975
 976         /* rd_cycle */
 977         temp = max_t(u32, dev_t->t_rd_cycle,
 978                         gpmc_t->cs_rd_off + dev_t->t_cez_r);
 979         temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
 980         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
 981
 982         return 0;
 983 }
 984
 985 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
 986                                 struct gpmc_device_timings *dev_t)
 987 {
 988         bool mux = dev_t->mux;
 989         u32 temp;
 990
 991         /* adv_wr_off */
 992         temp = dev_t->t_avdp_w;
 993         if (mux)
 994                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
 995         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
 996
 997         /* wr_data_mux_bus */
 998         temp = dev_t->t_weasu;
 999         if (mux) {
1000                 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1001                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1002                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1003         }
1004         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1005
1006         /* we_on */
1007         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1008                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1009         else
1010                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1011
1012         /* we_off */
1013         temp = gpmc_t->we_on + dev_t->t_wpl;
1014         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1015
1016         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1017                                                         dev_t->t_wph);
1018
1019         /* wr_cycle */
1020         temp = max_t(u32, dev_t->t_wr_cycle,
1021                                 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1022         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1023
1024         return 0;
1025 }
1026
1027 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1028                         struct gpmc_device_timings *dev_t)
1029 {
1030         u32 temp;
1031
1032         gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1033                                                 gpmc_get_fclk_period();
1034
1035         gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1036                                         dev_t->t_bacc,
1037                                         gpmc_t->sync_clk);
1038
1039         temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1040         gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1041
1042         if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1043                 return 0;
1044
1045         if (dev_t->ce_xdelay)
1046                 gpmc_t->bool_timings.cs_extra_delay = true;
1047         if (dev_t->avd_xdelay)
1048                 gpmc_t->bool_timings.adv_extra_delay = true;
1049         if (dev_t->oe_xdelay)
1050                 gpmc_t->bool_timings.oe_extra_delay = true;
1051         if (dev_t->we_xdelay)
1052                 gpmc_t->bool_timings.we_extra_delay = true;
1053
1054         return 0;
1055 }
1056
1057 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1058                         struct gpmc_device_timings *dev_t)
1059 {
1060         u32 temp;
1061
1062         /* cs_on */
1063         gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1064
1065         /* adv_on */
1066         temp = dev_t->t_avdasu;
1067         if (dev_t->t_ce_avd)
1068                 temp = max_t(u32, temp,
1069                                 gpmc_t->cs_on + dev_t->t_ce_avd);
1070         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1071
1072         if (dev_t->sync_write || dev_t->sync_read)
1073                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1074
1075         return 0;
1076 }
1077
1078 /* TODO: remove this function once all peripherals are confirmed to
1079  * work with generic timing. Simultaneously gpmc_cs_set_timings()
1080  * has to be modified to handle timings in ps instead of ns
1081 */
1082 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1083 {
1084         t->cs_on /= 1000;
1085         t->cs_rd_off /= 1000;
1086         t->cs_wr_off /= 1000;
1087         t->adv_on /= 1000;
1088         t->adv_rd_off /= 1000;
1089         t->adv_wr_off /= 1000;
1090         t->we_on /= 1000;
1091         t->we_off /= 1000;
1092         t->oe_on /= 1000;
1093         t->oe_off /= 1000;
1094         t->page_burst_access /= 1000;
1095         t->access /= 1000;
1096         t->rd_cycle /= 1000;
1097         t->wr_cycle /= 1000;
1098         t->bus_turnaround /= 1000;
1099         t->cycle2cycle_delay /= 1000;
1100         t->wait_monitoring /= 1000;
1101         t->clk_activation /= 1000;
1102         t->wr_access /= 1000;
1103         t->wr_data_mux_bus /= 1000;
1104 }
1105
1106 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1107                         struct gpmc_device_timings *dev_t)
1108 {
1109         memset(gpmc_t, 0, sizeof(*gpmc_t));
1110
1111         gpmc_calc_common_timings(gpmc_t, dev_t);
1112
1113         if (dev_t->sync_read)
1114                 gpmc_calc_sync_read_timings(gpmc_t, dev_t);
1115         else
1116                 gpmc_calc_async_read_timings(gpmc_t, dev_t);
1117
1118         if (dev_t->sync_write)
1119                 gpmc_calc_sync_write_timings(gpmc_t, dev_t);
1120         else
1121                 gpmc_calc_async_write_timings(gpmc_t, dev_t);
1122
1123         /* TODO: remove, see function definition */
1124         gpmc_convert_ps_to_ns(gpmc_t);
1125
1126         return 0;
1127 }
1128
1129 #ifdef CONFIG_OF
1130 static struct of_device_id gpmc_dt_ids[] = {
1131         { .compatible = "ti,omap2420-gpmc" },
1132         { .compatible = "ti,omap2430-gpmc" },
1133         { .compatible = "ti,omap3430-gpmc" },   /* omap3430 & omap3630 */
1134         { .compatible = "ti,omap4430-gpmc" },   /* omap4430 & omap4460 & omap543x */
1135         { .compatible = "ti,am3352-gpmc" },     /* am335x devices */
1136         { }
1137 };
1138 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1139
1140 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1141                                                 struct gpmc_timings *gpmc_t)
1142 {
1143         u32 val;
1144
1145         memset(gpmc_t, 0, sizeof(*gpmc_t));
1146
1147         /* minimum clock period for syncronous mode */
1148         if (!of_property_read_u32(np, "gpmc,sync-clk", &val))
1149                 gpmc_t->sync_clk = val;
1150
1151         /* chip select timtings */
1152         if (!of_property_read_u32(np, "gpmc,cs-on", &val))
1153                 gpmc_t->cs_on = val;
1154
1155         if (!of_property_read_u32(np, "gpmc,cs-rd-off", &val))
1156                 gpmc_t->cs_rd_off = val;
1157
1158         if (!of_property_read_u32(np, "gpmc,cs-wr-off", &val))
1159                 gpmc_t->cs_wr_off = val;
1160
1161         /* ADV signal timings */
1162         if (!of_property_read_u32(np, "gpmc,adv-on", &val))
1163                 gpmc_t->adv_on = val;
1164
1165         if (!of_property_read_u32(np, "gpmc,adv-rd-off", &val))
1166                 gpmc_t->adv_rd_off = val;
1167
1168         if (!of_property_read_u32(np, "gpmc,adv-wr-off", &val))
1169                 gpmc_t->adv_wr_off = val;
1170
1171         /* WE signal timings */
1172         if (!of_property_read_u32(np, "gpmc,we-on", &val))
1173                 gpmc_t->we_on = val;
1174
1175         if (!of_property_read_u32(np, "gpmc,we-off", &val))
1176                 gpmc_t->we_off = val;
1177
1178         /* OE signal timings */
1179         if (!of_property_read_u32(np, "gpmc,oe-on", &val))
1180                 gpmc_t->oe_on = val;
1181
1182         if (!of_property_read_u32(np, "gpmc,oe-off", &val))
1183                 gpmc_t->oe_off = val;
1184
1185         /* access and cycle timings */
1186         if (!of_property_read_u32(np, "gpmc,page-burst-access", &val))
1187                 gpmc_t->page_burst_access = val;
1188
1189         if (!of_property_read_u32(np, "gpmc,access", &val))
1190                 gpmc_t->access = val;
1191
1192         if (!of_property_read_u32(np, "gpmc,rd-cycle", &val))
1193                 gpmc_t->rd_cycle = val;
1194
1195         if (!of_property_read_u32(np, "gpmc,wr-cycle", &val))
1196                 gpmc_t->wr_cycle = val;
1197
1198         /* only for OMAP3430 */
1199         if (!of_property_read_u32(np, "gpmc,wr-access", &val))
1200                 gpmc_t->wr_access = val;
1201
1202         if (!of_property_read_u32(np, "gpmc,wr-data-mux-bus", &val))
1203                 gpmc_t->wr_data_mux_bus = val;
1204 }
1205
1206 #ifdef CONFIG_MTD_NAND
1207
1208 static const char * const nand_ecc_opts[] = {
1209         [OMAP_ECC_HAMMING_CODE_DEFAULT]         = "sw",
1210         [OMAP_ECC_HAMMING_CODE_HW]              = "hw",
1211         [OMAP_ECC_HAMMING_CODE_HW_ROMCODE]      = "hw-romcode",
1212         [OMAP_ECC_BCH4_CODE_HW]                 = "bch4",
1213         [OMAP_ECC_BCH8_CODE_HW]                 = "bch8",
1214 };
1215
1216 static int gpmc_probe_nand_child(struct platform_device *pdev,
1217                                  struct device_node *child)
1218 {
1219         u32 val;
1220         const char *s;
1221         struct gpmc_timings gpmc_t;
1222         struct omap_nand_platform_data *gpmc_nand_data;
1223
1224         if (of_property_read_u32(child, "reg", &val) < 0) {
1225                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1226                         child->full_name);
1227                 return -ENODEV;
1228         }
1229
1230         gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
1231                                       GFP_KERNEL);
1232         if (!gpmc_nand_data)
1233                 return -ENOMEM;
1234
1235         gpmc_nand_data->cs = val;
1236         gpmc_nand_data->of_node = child;
1237
1238         if (!of_property_read_string(child, "ti,nand-ecc-opt", &s))
1239                 for (val = 0; val < ARRAY_SIZE(nand_ecc_opts); val++)
1240                         if (!strcasecmp(s, nand_ecc_opts[val])) {
1241                                 gpmc_nand_data->ecc_opt = val;
1242                                 break;
1243                         }
1244
1245         val = of_get_nand_bus_width(child);
1246         if (val == 16)
1247                 gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
1248
1249         gpmc_read_timings_dt(child, &gpmc_t);
1250         gpmc_nand_init(gpmc_nand_data, &gpmc_t);
1251
1252         return 0;
1253 }
1254 #else
1255 static int gpmc_probe_nand_child(struct platform_device *pdev,
1256                                  struct device_node *child)
1257 {
1258         return 0;
1259 }
1260 #endif
1261
1262 static int gpmc_probe_dt(struct platform_device *pdev)
1263 {
1264         int ret;
1265         struct device_node *child;
1266         const struct of_device_id *of_id =
1267                 of_match_device(gpmc_dt_ids, &pdev->dev);
1268
1269         if (!of_id)
1270                 return 0;
1271
1272         for_each_node_by_name(child, "nand") {
1273                 ret = gpmc_probe_nand_child(pdev, child);
1274                 of_node_put(child);
1275                 if (ret < 0)
1276                         return ret;
1277         }
1278
1279         return 0;
1280 }
1281 #else
1282 static int gpmc_probe_dt(struct platform_device *pdev)
1283 {
1284         return 0;
1285 }
1286 #endif
1287
1288 static int gpmc_probe(struct platform_device *pdev)
1289 {
1290         int rc;
1291         u32 l;
1292         struct resource *res;
1293
1294         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1295         if (res == NULL)
1296                 return -ENOENT;
1297
1298         phys_base = res->start;
1299         mem_size = resource_size(res);
1300
1301         gpmc_base = devm_request_and_ioremap(&pdev->dev, res);
1302         if (!gpmc_base) {
1303                 dev_err(&pdev->dev, "error: request memory / ioremap\n");
1304                 return -EADDRNOTAVAIL;
1305         }
1306
1307         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1308         if (res == NULL)
1309                 dev_warn(&pdev->dev, "Failed to get resource: irq\n");
1310         else
1311                 gpmc_irq = res->start;
1312
1313         gpmc_l3_clk = clk_get(&pdev->dev, "fck");
1314         if (IS_ERR(gpmc_l3_clk)) {
1315                 dev_err(&pdev->dev, "error: clk_get\n");
1316                 gpmc_irq = 0;
1317                 return PTR_ERR(gpmc_l3_clk);
1318         }
1319
1320         clk_prepare_enable(gpmc_l3_clk);
1321
1322         gpmc_dev = &pdev->dev;
1323
1324         l = gpmc_read_reg(GPMC_REVISION);
1325         if (GPMC_REVISION_MAJOR(l) > 0x4)
1326                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
1327         dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
1328                  GPMC_REVISION_MINOR(l));
1329
1330         rc = gpmc_mem_init();
1331         if (IS_ERR_VALUE(rc)) {
1332                 clk_disable_unprepare(gpmc_l3_clk);
1333                 clk_put(gpmc_l3_clk);
1334                 dev_err(gpmc_dev, "failed to reserve memory\n");
1335                 return rc;
1336         }
1337
1338         if (IS_ERR_VALUE(gpmc_setup_irq()))
1339                 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
1340
1341         rc = gpmc_probe_dt(pdev);
1342         if (rc < 0) {
1343                 clk_disable_unprepare(gpmc_l3_clk);
1344                 clk_put(gpmc_l3_clk);
1345                 dev_err(gpmc_dev, "failed to probe DT parameters\n");
1346                 return rc;
1347         }
1348
1349         return 0;
1350 }
1351
1352 static int gpmc_remove(struct platform_device *pdev)
1353 {
1354         gpmc_free_irq();
1355         gpmc_mem_exit();
1356         gpmc_dev = NULL;
1357         return 0;
1358 }
1359
1360 static struct platform_driver gpmc_driver = {
1361         .probe          = gpmc_probe,
1362         .remove         = gpmc_remove,
1363         .driver         = {
1364                 .name   = DEVICE_NAME,
1365                 .owner  = THIS_MODULE,
1366                 .of_match_table = of_match_ptr(gpmc_dt_ids),
1367         },
1368 };
1369
1370 static __init int gpmc_init(void)
1371 {
1372         return platform_driver_register(&gpmc_driver);
1373 }
1374
1375 static __exit void gpmc_exit(void)
1376 {
1377         platform_driver_unregister(&gpmc_driver);
1378
1379 }
1380
1381 postcore_initcall(gpmc_init);
1382 module_exit(gpmc_exit);
1383
1384 static int __init omap_gpmc_init(void)
1385 {
1386         struct omap_hwmod *oh;
1387         struct platform_device *pdev;
1388         char *oh_name = "gpmc";
1389
1390         /*
1391          * if the board boots up with a populated DT, do not
1392          * manually add the device from this initcall
1393          */
1394         if (of_have_populated_dt())
1395                 return -ENODEV;
1396
1397         oh = omap_hwmod_lookup(oh_name);
1398         if (!oh) {
1399                 pr_err("Could not look up %s\n", oh_name);
1400                 return -ENODEV;
1401         }
1402
1403         pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0);
1404         WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
1405
1406         return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
1407 }
1408 postcore_initcall(omap_gpmc_init);
1409
1410 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
1411 {
1412         int i;
1413         u32 regval;
1414
1415         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1416
1417         if (!regval)
1418                 return IRQ_NONE;
1419
1420         for (i = 0; i < GPMC_NR_IRQ; i++)
1421                 if (regval & gpmc_client_irq[i].bitmask)
1422                         generic_handle_irq(gpmc_client_irq[i].irq);
1423
1424         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1425
1426         return IRQ_HANDLED;
1427 }
1428
1429 #ifdef CONFIG_ARCH_OMAP3
1430 static struct omap3_gpmc_regs gpmc_context;
1431
1432 void omap3_gpmc_save_context(void)
1433 {
1434         int i;
1435
1436         gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
1437         gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
1438         gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
1439         gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
1440         gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
1441         gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
1442         gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
1443         for (i = 0; i < GPMC_CS_NUM; i++) {
1444                 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
1445                 if (gpmc_context.cs_context[i].is_valid) {
1446                         gpmc_context.cs_context[i].config1 =
1447                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
1448                         gpmc_context.cs_context[i].config2 =
1449                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
1450                         gpmc_context.cs_context[i].config3 =
1451                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
1452                         gpmc_context.cs_context[i].config4 =
1453                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
1454                         gpmc_context.cs_context[i].config5 =
1455                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
1456                         gpmc_context.cs_context[i].config6 =
1457                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
1458                         gpmc_context.cs_context[i].config7 =
1459                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
1460                 }
1461         }
1462 }
1463
1464 void omap3_gpmc_restore_context(void)
1465 {
1466         int i;
1467
1468         gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
1469         gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
1470         gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
1471         gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
1472         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
1473         gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
1474         gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
1475         for (i = 0; i < GPMC_CS_NUM; i++) {
1476                 if (gpmc_context.cs_context[i].is_valid) {
1477                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
1478                                 gpmc_context.cs_context[i].config1);
1479                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
1480                                 gpmc_context.cs_context[i].config2);
1481                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
1482                                 gpmc_context.cs_context[i].config3);
1483                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
1484                                 gpmc_context.cs_context[i].config4);
1485                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
1486                                 gpmc_context.cs_context[i].config5);
1487                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
1488                                 gpmc_context.cs_context[i].config6);
1489                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
1490                                 gpmc_context.cs_context[i].config7);
1491                 }
1492         }
1493 }
1494 #endif /* CONFIG_ARCH_OMAP3 */