arch/arm/mach-omap2/hsmmc.c

   1 /*
   2  * linux/arch/arm/mach-omap2/hsmmc.c
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Author: Texas Instruments
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/kernel.h>
  13 #include <linux/slab.h>
  14 #include <linux/string.h>
  15 #include <linux/delay.h>
  16 #include <linux/gpio.h>
  17 #include <linux/mmc/host.h>
  18 #include <linux/platform_data/gpio-omap.h>
  19 #include <linux/platform_data/hsmmc-omap.h>
  20
  21 #include "soc.h"
  22 #include "omap_device.h"
  23 #include "omap-pm.h"
  24
  25 #include "mux.h"
  26 #include "hsmmc.h"
  27 #include "control.h"
  28
  29 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
  30
  31 static u16 control_pbias_offset;
  32 static u16 control_devconf1_offset;
  33
  34 #define HSMMC_NAME_LEN  9
  35
  36 static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
  37                                   int power_on, int vdd)
  38 {
  39         u32 reg, prog_io;
  40         struct omap_hsmmc_platform_data *mmc = dev->platform_data;
  41
  42         if (mmc->slots[0].remux)
  43                 mmc->slots[0].remux(dev, slot, power_on);
  44
  45         /*
  46          * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
  47          * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
  48          * 1.8V and 3.0V modes, controlled by the PBIAS register.
  49          *
  50          * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
  51          * is most naturally TWL VSIM; those pins also use PBIAS.
  52          *
  53          * FIXME handle VMMC1A as needed ...
  54          */
  55         if (power_on) {
  56                 if (cpu_is_omap2430()) {
  57                         reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
  58                         if ((1 << vdd) >= MMC_VDD_30_31)
  59                                 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
  60                         else
  61                                 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
  62                         omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
  63                 }
  64
  65                 if (mmc->slots[0].internal_clock) {
  66                         reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
  67                         reg |= OMAP2_MMCSDIO1ADPCLKISEL;
  68                         omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
  69                 }
  70
  71                 reg = omap_ctrl_readl(control_pbias_offset);
  72                 if (cpu_is_omap3630()) {
  73                         /* Set MMC I/O to 52Mhz */
  74                         prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
  75                         prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
  76                         omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
  77                 } else {
  78                         reg |= OMAP2_PBIASSPEEDCTRL0;
  79                 }
  80                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
  81                 omap_ctrl_writel(reg, control_pbias_offset);
  82         } else {
  83                 reg = omap_ctrl_readl(control_pbias_offset);
  84                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
  85                 omap_ctrl_writel(reg, control_pbias_offset);
  86         }
  87 }
  88
  89 static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
  90                                  int power_on, int vdd)
  91 {
  92         u32 reg;
  93
  94         /* 100ms delay required for PBIAS configuration */
  95         msleep(100);
  96
  97         if (power_on) {
  98                 reg = omap_ctrl_readl(control_pbias_offset);
  99                 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
 100                 if ((1 << vdd) <= MMC_VDD_165_195)
 101                         reg &= ~OMAP2_PBIASLITEVMODE0;
 102                 else
 103                         reg |= OMAP2_PBIASLITEVMODE0;
 104                 omap_ctrl_writel(reg, control_pbias_offset);
 105         } else {
 106                 reg = omap_ctrl_readl(control_pbias_offset);
 107                 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
 108                         OMAP2_PBIASLITEVMODE0);
 109                 omap_ctrl_writel(reg, control_pbias_offset);
 110         }
 111 }
 112
 113 static void hsmmc2_select_input_clk_src(struct omap_hsmmc_platform_data *mmc)
 114 {
 115         u32 reg;
 116
 117         reg = omap_ctrl_readl(control_devconf1_offset);
 118         if (mmc->slots[0].internal_clock)
 119                 reg |= OMAP2_MMCSDIO2ADPCLKISEL;
 120         else
 121                 reg &= ~OMAP2_MMCSDIO2ADPCLKISEL;
 122         omap_ctrl_writel(reg, control_devconf1_offset);
 123 }
 124
 125 static void hsmmc2_before_set_reg(struct device *dev, int slot,
 126                                    int power_on, int vdd)
 127 {
 128         struct omap_hsmmc_platform_data *mmc = dev->platform_data;
 129
 130         if (mmc->slots[0].remux)
 131                 mmc->slots[0].remux(dev, slot, power_on);
 132
 133         if (power_on)
 134                 hsmmc2_select_input_clk_src(mmc);
 135 }
 136
 137 static int am35x_hsmmc2_set_power(struct device *dev, int slot,
 138                                   int power_on, int vdd)
 139 {
 140         struct omap_hsmmc_platform_data *mmc = dev->platform_data;
 141
 142         if (power_on)
 143                 hsmmc2_select_input_clk_src(mmc);
 144
 145         return 0;
 146 }
 147
 148 static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
 149                                                         int vdd)
 150 {
 151         return 0;
 152 }
 153
 154 static inline void omap_hsmmc_mux(struct omap_hsmmc_platform_data
 155                                   *mmc_controller, int controller_nr)
 156 {
 157         if (gpio_is_valid(mmc_controller->slots[0].switch_pin) &&
 158                 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
 159                 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
 160                                         OMAP_PIN_INPUT_PULLUP);
 161         if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) &&
 162                 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
 163                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
 164                                         OMAP_PIN_INPUT_PULLUP);
 165         if (cpu_is_omap34xx()) {
 166                 if (controller_nr == 0) {
 167                         omap_mux_init_signal("sdmmc1_clk",
 168                                 OMAP_PIN_INPUT_PULLUP);
 169                         omap_mux_init_signal("sdmmc1_cmd",
 170                                 OMAP_PIN_INPUT_PULLUP);
 171                         omap_mux_init_signal("sdmmc1_dat0",
 172                                 OMAP_PIN_INPUT_PULLUP);
 173                         if (mmc_controller->slots[0].caps &
 174                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
 175                                 omap_mux_init_signal("sdmmc1_dat1",
 176                                         OMAP_PIN_INPUT_PULLUP);
 177                                 omap_mux_init_signal("sdmmc1_dat2",
 178                                         OMAP_PIN_INPUT_PULLUP);
 179                                 omap_mux_init_signal("sdmmc1_dat3",
 180                                         OMAP_PIN_INPUT_PULLUP);
 181                         }
 182                         if (mmc_controller->slots[0].caps &
 183                                                 MMC_CAP_8_BIT_DATA) {
 184                                 omap_mux_init_signal("sdmmc1_dat4",
 185                                         OMAP_PIN_INPUT_PULLUP);
 186                                 omap_mux_init_signal("sdmmc1_dat5",
 187                                         OMAP_PIN_INPUT_PULLUP);
 188                                 omap_mux_init_signal("sdmmc1_dat6",
 189                                         OMAP_PIN_INPUT_PULLUP);
 190                                 omap_mux_init_signal("sdmmc1_dat7",
 191                                         OMAP_PIN_INPUT_PULLUP);
 192                         }
 193                 }
 194                 if (controller_nr == 1) {
 195                         /* MMC2 */
 196                         omap_mux_init_signal("sdmmc2_clk",
 197                                 OMAP_PIN_INPUT_PULLUP);
 198                         omap_mux_init_signal("sdmmc2_cmd",
 199                                 OMAP_PIN_INPUT_PULLUP);
 200                         omap_mux_init_signal("sdmmc2_dat0",
 201                                 OMAP_PIN_INPUT_PULLUP);
 202
 203                         /*
 204                          * For 8 wire configurations, Lines DAT4, 5, 6 and 7
 205                          * need to be muxed in the board-*.c files
 206                          */
 207                         if (mmc_controller->slots[0].caps &
 208                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
 209                                 omap_mux_init_signal("sdmmc2_dat1",
 210                                         OMAP_PIN_INPUT_PULLUP);
 211                                 omap_mux_init_signal("sdmmc2_dat2",
 212                                         OMAP_PIN_INPUT_PULLUP);
 213                                 omap_mux_init_signal("sdmmc2_dat3",
 214                                         OMAP_PIN_INPUT_PULLUP);
 215                         }
 216                         if (mmc_controller->slots[0].caps &
 217                                                         MMC_CAP_8_BIT_DATA) {
 218                                 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
 219                                         OMAP_PIN_INPUT_PULLUP);
 220                                 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
 221                                         OMAP_PIN_INPUT_PULLUP);
 222                                 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
 223                                         OMAP_PIN_INPUT_PULLUP);
 224                                 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
 225                                         OMAP_PIN_INPUT_PULLUP);
 226                         }
 227                 }
 228
 229                 /*
 230                  * For MMC3 the pins need to be muxed in the board-*.c files
 231                  */
 232         }
 233 }
 234
 235 static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
 236                                         struct omap_hsmmc_platform_data *mmc)
 237 {
 238         char *hc_name;
 239
 240         hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
 241         if (!hc_name) {
 242                 pr_err("Cannot allocate memory for controller slot name\n");
 243                 kfree(hc_name);
 244                 return -ENOMEM;
 245         }
 246
 247         if (c->name)
 248                 strncpy(hc_name, c->name, HSMMC_NAME_LEN);
 249         else
 250                 snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
 251                                                                 c->mmc, 1);
 252         mmc->slots[0].name = hc_name;
 253         mmc->nr_slots = 1;
 254         mmc->slots[0].caps = c->caps;
 255         mmc->slots[0].internal_clock = !c->ext_clock;
 256         mmc->reg_offset = 0;
 257
 258         mmc->slots[0].switch_pin = c->gpio_cd;
 259         mmc->slots[0].gpio_wp = c->gpio_wp;
 260
 261         mmc->slots[0].remux = c->remux;
 262         mmc->slots[0].init_card = c->init_card;
 263
 264         if (c->cover_only)
 265                 mmc->slots[0].cover = 1;
 266
 267         if (c->nonremovable)
 268                 mmc->slots[0].nonremovable = 1;
 269
 270         /*
 271          * NOTE:  MMC slots should have a Vcc regulator set up.
 272          * This may be from a TWL4030-family chip, another
 273          * controllable regulator, or a fixed supply.
 274          *
 275          * temporary HACK: ocr_mask instead of fixed supply
 276          */
 277         if (soc_is_am35xx())
 278                 mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
 279                                          MMC_VDD_26_27 |
 280                                          MMC_VDD_27_28 |
 281                                          MMC_VDD_29_30 |
 282                                          MMC_VDD_30_31 |
 283                                          MMC_VDD_31_32;
 284         else
 285                 mmc->slots[0].ocr_mask = c->ocr_mask;
 286
 287         if (!soc_is_am35xx())
 288                 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
 289
 290         switch (c->mmc) {
 291         case 1:
 292                 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
 293                         /* on-chip level shifting via PBIAS0/PBIAS1 */
 294                         mmc->slots[0].before_set_reg =
 295                                         omap_hsmmc1_before_set_reg;
 296                         mmc->slots[0].after_set_reg =
 297                                         omap_hsmmc1_after_set_reg;
 298                 }
 299
 300                 if (soc_is_am35xx())
 301                         mmc->slots[0].set_power = nop_mmc_set_power;
 302
 303                 /* OMAP3630 HSMMC1 supports only 4-bit */
 304                 if (cpu_is_omap3630() &&
 305                                 (c->caps & MMC_CAP_8_BIT_DATA)) {
 306                         c->caps &= ~MMC_CAP_8_BIT_DATA;
 307                         c->caps |= MMC_CAP_4_BIT_DATA;
 308                         mmc->slots[0].caps = c->caps;
 309                 }
 310                 break;
 311         case 2:
 312                 if (soc_is_am35xx())
 313                         mmc->slots[0].set_power = am35x_hsmmc2_set_power;
 314
 315                 if (c->ext_clock)
 316                         c->transceiver = 1;
 317                 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
 318                         c->caps &= ~MMC_CAP_8_BIT_DATA;
 319                         c->caps |= MMC_CAP_4_BIT_DATA;
 320                 }
 321                 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
 322                         /* off-chip level shifting, or none */
 323                         mmc->slots[0].before_set_reg = hsmmc2_before_set_reg;
 324                         mmc->slots[0].after_set_reg = NULL;
 325                 }
 326                 break;
 327         case 3:
 328         case 4:
 329         case 5:
 330                 mmc->slots[0].before_set_reg = NULL;
 331                 mmc->slots[0].after_set_reg = NULL;
 332                 break;
 333         default:
 334                 pr_err("MMC%d configuration not supported!\n", c->mmc);
 335                 kfree(hc_name);
 336                 return -ENODEV;
 337         }
 338         return 0;
 339 }
 340
 341 static int omap_hsmmc_done;
 342
 343 void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
 344 {
 345         struct platform_device *pdev;
 346         struct omap_hsmmc_platform_data *mmc_pdata;
 347         int res;
 348
 349         if (omap_hsmmc_done != 1)
 350                 return;
 351
 352         omap_hsmmc_done++;
 353
 354         for (; c->mmc; c++) {
 355                 if (!c->deferred)
 356                         continue;
 357
 358                 pdev = c->pdev;
 359                 if (!pdev)
 360                         continue;
 361
 362                 mmc_pdata = pdev->dev.platform_data;
 363                 if (!mmc_pdata)
 364                         continue;
 365
 366                 mmc_pdata->slots[0].switch_pin = c->gpio_cd;
 367                 mmc_pdata->slots[0].gpio_wp = c->gpio_wp;
 368
 369                 res = omap_device_register(pdev);
 370                 if (res)
 371                         pr_err("Could not late init MMC %s\n",
 372                                c->name);
 373         }
 374 }
 375
 376 #define MAX_OMAP_MMC_HWMOD_NAME_LEN             16
 377
 378 static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
 379                                         int ctrl_nr)
 380 {
 381         struct omap_hwmod *oh;
 382         struct omap_hwmod *ohs[1];
 383         struct omap_device *od;
 384         struct platform_device *pdev;
 385         char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
 386         struct omap_hsmmc_platform_data *mmc_data;
 387         struct omap_hsmmc_dev_attr *mmc_dev_attr;
 388         char *name;
 389         int res;
 390
 391         mmc_data = kzalloc(sizeof(*mmc_data), GFP_KERNEL);
 392         if (!mmc_data) {
 393                 pr_err("Cannot allocate memory for mmc device!\n");
 394                 return;
 395         }
 396
 397         res = omap_hsmmc_pdata_init(hsmmcinfo, mmc_data);
 398         if (res < 0)
 399                 goto free_mmc;
 400
 401         omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
 402
 403         name = "omap_hsmmc";
 404         res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
 405                      "mmc%d", ctrl_nr);
 406         WARN(res >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
 407              "String buffer overflow in MMC%d device setup\n", ctrl_nr);
 408
 409         oh = omap_hwmod_lookup(oh_name);
 410         if (!oh) {
 411                 pr_err("Could not look up %s\n", oh_name);
 412                 goto free_name;
 413         }
 414         ohs[0] = oh;
 415         if (oh->dev_attr != NULL) {
 416                 mmc_dev_attr = oh->dev_attr;
 417                 mmc_data->controller_flags = mmc_dev_attr->flags;
 418                 /*
 419                  * erratum 2.1.1.128 doesn't apply if board has
 420                  * a transceiver is attached
 421                  */
 422                 if (hsmmcinfo->transceiver)
 423                         mmc_data->controller_flags &=
 424                                 ~OMAP_HSMMC_BROKEN_MULTIBLOCK_READ;
 425         }
 426
 427         pdev = platform_device_alloc(name, ctrl_nr - 1);
 428         if (!pdev) {
 429                 pr_err("Could not allocate pdev for %s\n", name);
 430                 goto free_name;
 431         }
 432         dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
 433
 434         od = omap_device_alloc(pdev, ohs, 1);
 435         if (IS_ERR(od)) {
 436                 pr_err("Could not allocate od for %s\n", name);
 437                 goto put_pdev;
 438         }
 439
 440         res = platform_device_add_data(pdev, mmc_data,
 441                               sizeof(struct omap_hsmmc_platform_data));
 442         if (res) {
 443                 pr_err("Could not add pdata for %s\n", name);
 444                 goto put_pdev;
 445         }
 446
 447         hsmmcinfo->pdev = pdev;
 448
 449         if (hsmmcinfo->deferred)
 450                 goto free_mmc;
 451
 452         res = omap_device_register(pdev);
 453         if (res) {
 454                 pr_err("Could not register od for %s\n", name);
 455                 goto free_od;
 456         }
 457
 458         goto free_mmc;
 459
 460 free_od:
 461         omap_device_delete(od);
 462
 463 put_pdev:
 464         platform_device_put(pdev);
 465
 466 free_name:
 467         kfree(mmc_data->slots[0].name);
 468
 469 free_mmc:
 470         kfree(mmc_data);
 471 }
 472
 473 void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
 474 {
 475         if (omap_hsmmc_done)
 476                 return;
 477
 478         omap_hsmmc_done = 1;
 479
 480         if (cpu_is_omap2430()) {
 481                 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
 482                 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
 483         } else {
 484                 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
 485                 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
 486         }
 487
 488         for (; controllers->mmc; controllers++)
 489                 omap_hsmmc_init_one(controllers, controllers->mmc);
 490
 491 }
 492
 493 #endif