arch/arm/mach-omap2/omap-mpuss-lowpower.c

   1 /*
   2  * OMAP MPUSS low power code
   3  *
   4  * Copyright (C) 2011 Texas Instruments, Inc.
   5  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   6  *
   7  * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
   8  * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
   9  * CPU0 and CPU1 LPRM modules.
  10  * CPU0, CPU1 and MPUSS each have there own power domain and
  11  * hence multiple low power combinations of MPUSS are possible.
  12  *
  13  * The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
  14  * because the mode is not supported by hw constraints of dormant
  15  * mode. While waking up from the dormant mode, a reset  signal
  16  * to the Cortex-A9 processor must be asserted by the external
  17  * power controller.
  18  *
  19  * With architectural inputs and hardware recommendations, only
  20  * below modes are supported from power gain vs latency point of view.
  21  *
  22  *      CPU0            CPU1            MPUSS
  23  *      ----------------------------------------------
  24  *      ON              ON              ON
  25  *      ON(Inactive)    OFF             ON(Inactive)
  26  *      OFF             OFF             CSWR
  27  *      OFF             OFF             OSWR
  28  *      OFF             OFF             OFF(Device OFF *TBD)
  29  *      ----------------------------------------------
  30  *
  31  * Note: CPU0 is the master core and it is the last CPU to go down
  32  * and first to wake-up when MPUSS low power states are excercised
  33  *
  34  *
  35  * This program is free software; you can redistribute it and/or modify
  36  * it under the terms of the GNU General Public License version 2 as
  37  * published by the Free Software Foundation.
  38  */
  39
  40 #include <linux/kernel.h>
  41 #include <linux/io.h>
  42 #include <linux/errno.h>
  43 #include <linux/linkage.h>
  44 #include <linux/smp.h>
  45
  46 #include <asm/cacheflush.h>
  47 #include <asm/tlbflush.h>
  48 #include <asm/smp_scu.h>
  49 #include <asm/pgalloc.h>
  50 #include <asm/suspend.h>
  51 #include <asm/hardware/cache-l2x0.h>
  52
  53 #include "soc.h"
  54 #include "common.h"
  55 #include "omap44xx.h"
  56 #include "omap4-sar-layout.h"
  57 #include "pm.h"
  58 #include "prcm_mpu44xx.h"
  59 #include "prminst44xx.h"
  60 #include "prcm44xx.h"
  61 #include "prm44xx.h"
  62 #include "prm-regbits-44xx.h"
  63
  64 #ifdef CONFIG_SMP
  65
  66 struct omap4_cpu_pm_info {
  67         struct powerdomain *pwrdm;
  68         void __iomem *scu_sar_addr;
  69         void __iomem *wkup_sar_addr;
  70         void __iomem *l2x0_sar_addr;
  71         void (*secondary_startup)(void);
  72 };
  73
  74 /**
  75  * struct cpu_pm_ops - CPU pm operations
  76  * @finish_suspend:     CPU suspend finisher function pointer
  77  * @resume:             CPU resume function pointer
  78  * @scu_prepare:        CPU Snoop Control program function pointer
  79  *
  80  * Structure holds functions pointer for CPU low power operations like
  81  * suspend, resume and scu programming.
  82  */
  83 struct cpu_pm_ops {
  84         int (*finish_suspend)(unsigned long cpu_state);
  85         void (*resume)(void);
  86         void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state);
  87 };
  88
  89 static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
  90 static struct powerdomain *mpuss_pd;
  91 static void __iomem *sar_base;
  92
  93 static int default_finish_suspend(unsigned long cpu_state)
  94 {
  95         omap_do_wfi();
  96         return 0;
  97 }
  98
  99 static void dummy_cpu_resume(void)
 100 {}
 101
 102 static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state)
 103 {}
 104
 105 struct cpu_pm_ops omap_pm_ops = {
 106         .finish_suspend         = default_finish_suspend,
 107         .resume                 = dummy_cpu_resume,
 108         .scu_prepare            = dummy_scu_prepare,
 109 };
 110
 111 /*
 112  * Program the wakeup routine address for the CPU0 and CPU1
 113  * used for OFF or DORMANT wakeup.
 114  */
 115 static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
 116 {
 117         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
 118
 119         __raw_writel(addr, pm_info->wkup_sar_addr);
 120 }
 121
 122 /*
 123  * Store the SCU power status value to scratchpad memory
 124  */
 125 static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
 126 {
 127         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
 128         u32 scu_pwr_st;
 129
 130         switch (cpu_state) {
 131         case PWRDM_POWER_RET:
 132                 scu_pwr_st = SCU_PM_DORMANT;
 133                 break;
 134         case PWRDM_POWER_OFF:
 135                 scu_pwr_st = SCU_PM_POWEROFF;
 136                 break;
 137         case PWRDM_POWER_ON:
 138         case PWRDM_POWER_INACTIVE:
 139         default:
 140                 scu_pwr_st = SCU_PM_NORMAL;
 141                 break;
 142         }
 143
 144         __raw_writel(scu_pwr_st, pm_info->scu_sar_addr);
 145 }
 146
 147 /* Helper functions for MPUSS OSWR */
 148 static inline void mpuss_clear_prev_logic_pwrst(void)
 149 {
 150         u32 reg;
 151
 152         reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 153                 OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
 154         omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION,
 155                 OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
 156 }
 157
 158 static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
 159 {
 160         u32 reg;
 161
 162         if (cpu_id) {
 163                 reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
 164                                         OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
 165                 omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
 166                                         OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
 167         } else {
 168                 reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
 169                                         OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
 170                 omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
 171                                         OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
 172         }
 173 }
 174
 175 /**
 176  * omap4_mpuss_read_prev_context_state:
 177  * Function returns the MPUSS previous context state
 178  */
 179 u32 omap4_mpuss_read_prev_context_state(void)
 180 {
 181         u32 reg;
 182
 183         reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 184                 OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
 185         reg &= OMAP4430_LOSTCONTEXT_DFF_MASK;
 186         return reg;
 187 }
 188
 189 /*
 190  * Store the CPU cluster state for L2X0 low power operations.
 191  */
 192 static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
 193 {
 194         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
 195
 196         __raw_writel(save_state, pm_info->l2x0_sar_addr);
 197 }
 198
 199 /*
 200  * Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
 201  * in every restore MPUSS OFF path.
 202  */
 203 #ifdef CONFIG_CACHE_L2X0
 204 static void save_l2x0_context(void)
 205 {
 206         u32 val;
 207         void __iomem *l2x0_base = omap4_get_l2cache_base();
 208         if (l2x0_base) {
 209                 val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
 210                 __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
 211                 val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
 212                 __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
 213         }
 214 }
 215 #else
 216 static void save_l2x0_context(void)
 217 {}
 218 #endif
 219
 220 /**
 221  * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
 222  * The purpose of this function is to manage low power programming
 223  * of OMAP4 MPUSS subsystem
 224  * @cpu : CPU ID
 225  * @power_state: Low power state.
 226  *
 227  * MPUSS states for the context save:
 228  * save_state =
 229  *      0 - Nothing lost and no need to save: MPUSS INACTIVE
 230  *      1 - CPUx L1 and logic lost: MPUSS CSWR
 231  *      2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
 232  *      3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
 233  */
 234 int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 235 {
 236         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
 237         unsigned int save_state = 0;
 238         unsigned int wakeup_cpu;
 239
 240         if (omap_rev() == OMAP4430_REV_ES1_0)
 241                 return -ENXIO;
 242
 243         switch (power_state) {
 244         case PWRDM_POWER_ON:
 245         case PWRDM_POWER_INACTIVE:
 246                 save_state = 0;
 247                 break;
 248         case PWRDM_POWER_OFF:
 249                 save_state = 1;
 250                 break;
 251         case PWRDM_POWER_RET:
 252         default:
 253                 /*
 254                  * CPUx CSWR is invalid hardware state. Also CPUx OSWR
 255                  * doesn't make much scense, since logic is lost and $L1
 256                  * needs to be cleaned because of coherency. This makes
 257                  * CPUx OSWR equivalent to CPUX OFF and hence not supported
 258                  */
 259                 WARN_ON(1);
 260                 return -ENXIO;
 261         }
 262
 263         pwrdm_pre_transition(NULL);
 264
 265         /*
 266          * Check MPUSS next state and save interrupt controller if needed.
 267          * In MPUSS OSWR or device OFF, interrupt controller  contest is lost.
 268          */
 269         mpuss_clear_prev_logic_pwrst();
 270         if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
 271                 (pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
 272                 save_state = 2;
 273
 274         cpu_clear_prev_logic_pwrst(cpu);
 275         pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
 276         set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume));
 277         omap_pm_ops.scu_prepare(cpu, power_state);
 278         l2x0_pwrst_prepare(cpu, save_state);
 279
 280         /*
 281          * Call low level function  with targeted low power state.
 282          */
 283         if (save_state)
 284                 cpu_suspend(save_state, omap_pm_ops.finish_suspend);
 285         else
 286                 omap_pm_ops.finish_suspend(save_state);
 287
 288         /*
 289          * Restore the CPUx power state to ON otherwise CPUx
 290          * power domain can transitions to programmed low power
 291          * state while doing WFI outside the low powe code. On
 292          * secure devices, CPUx does WFI which can result in
 293          * domain transition
 294          */
 295         wakeup_cpu = smp_processor_id();
 296         pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
 297
 298         pwrdm_post_transition(NULL);
 299
 300         return 0;
 301 }
 302
 303 /**
 304  * omap4_hotplug_cpu: OMAP4 CPU hotplug entry
 305  * @cpu : CPU ID
 306  * @power_state: CPU low power state.
 307  */
 308 int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
 309 {
 310         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
 311         unsigned int cpu_state = 0;
 312
 313         if (omap_rev() == OMAP4430_REV_ES1_0)
 314                 return -ENXIO;
 315
 316         if (power_state == PWRDM_POWER_OFF)
 317                 cpu_state = 1;
 318
 319         pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
 320         pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
 321         set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup));
 322         omap_pm_ops.scu_prepare(cpu, power_state);
 323
 324         /*
 325          * CPU never retuns back if targeted power state is OFF mode.
 326          * CPU ONLINE follows normal CPU ONLINE ptah via
 327          * omap_secondary_startup().
 328          */
 329         omap_pm_ops.finish_suspend(cpu_state);
 330
 331         pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
 332         return 0;
 333 }
 334
 335
 336 /*
 337  * Initialise OMAP4 MPUSS
 338  */
 339 int __init omap4_mpuss_init(void)
 340 {
 341         struct omap4_cpu_pm_info *pm_info;
 342
 343         if (omap_rev() == OMAP4430_REV_ES1_0) {
 344                 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
 345                 return -ENODEV;
 346         }
 347
 348         sar_base = omap4_get_sar_ram_base();
 349
 350         /* Initilaise per CPU PM information */
 351         pm_info = &per_cpu(omap4_pm_info, 0x0);
 352         pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
 353         pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
 354         pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
 355         pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
 356         if (!pm_info->pwrdm) {
 357                 pr_err("Lookup failed for CPU0 pwrdm\n");
 358                 return -ENODEV;
 359         }
 360
 361         /* Clear CPU previous power domain state */
 362         pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
 363         cpu_clear_prev_logic_pwrst(0);
 364
 365         /* Initialise CPU0 power domain state to ON */
 366         pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
 367
 368         pm_info = &per_cpu(omap4_pm_info, 0x1);
 369         pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
 370         pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
 371         pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
 372         if (cpu_is_omap446x())
 373                 pm_info->secondary_startup = omap_secondary_startup_4460;
 374         else
 375                 pm_info->secondary_startup = omap_secondary_startup;
 376
 377         pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
 378         if (!pm_info->pwrdm) {
 379                 pr_err("Lookup failed for CPU1 pwrdm\n");
 380                 return -ENODEV;
 381         }
 382
 383         /* Clear CPU previous power domain state */
 384         pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
 385         cpu_clear_prev_logic_pwrst(1);
 386
 387         /* Initialise CPU1 power domain state to ON */
 388         pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
 389
 390         mpuss_pd = pwrdm_lookup("mpu_pwrdm");
 391         if (!mpuss_pd) {
 392                 pr_err("Failed to lookup MPUSS power domain\n");
 393                 return -ENODEV;
 394         }
 395         pwrdm_clear_all_prev_pwrst(mpuss_pd);
 396         mpuss_clear_prev_logic_pwrst();
 397
 398         /* Save device type on scratchpad for low level code to use */
 399         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
 400                 __raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
 401         else
 402                 __raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
 403
 404         save_l2x0_context();
 405
 406         if (cpu_is_omap44xx()) {
 407                 omap_pm_ops.finish_suspend = omap4_finish_suspend;
 408                 omap_pm_ops.resume = omap4_cpu_resume;
 409                 omap_pm_ops.scu_prepare = scu_pwrst_prepare;
 410         }
 411
 412         return 0;
 413 }
 414
 415 #endif