arch/arm/mach-omap2/omap-mpuss-lowpower.c

   1 /*
   2  * OMAP MPUSS low power code
   3  *
   4  * Copyright (C) 2011 Texas Instruments, Inc.
   5  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   6  *
   7  * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
   8  * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
   9  * CPU0 and CPU1 LPRM modules.
  10  * CPU0, CPU1 and MPUSS each have there own power domain and
  11  * hence multiple low power combinations of MPUSS are possible.
  12  *
  13  * The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
  14  * because the mode is not supported by hw constraints of dormant
  15  * mode. While waking up from the dormant mode, a reset  signal
  16  * to the Cortex-A9 processor must be asserted by the external
  17  * power controller.
  18  *
  19  * With architectural inputs and hardware recommendations, only
  20  * below modes are supported from power gain vs latency point of view.
  21  *
  22  *      CPU0            CPU1            MPUSS
  23  *      ----------------------------------------------
  24  *      ON              ON              ON
  25  *      ON(Inactive)    OFF             ON(Inactive)
  26  *      OFF             OFF             CSWR
  27  *      OFF             OFF             OSWR
  28  *      OFF             OFF             OFF(Device OFF *TBD)
  29  *      ----------------------------------------------
  30  *
  31  * Note: CPU0 is the master core and it is the last CPU to go down
  32  * and first to wake-up when MPUSS low power states are excercised
  33  *
  34  *
  35  * This program is free software; you can redistribute it and/or modify
  36  * it under the terms of the GNU General Public License version 2 as
  37  * published by the Free Software Foundation.
  38  */
  39
  40 #include <linux/kernel.h>
  41 #include <linux/io.h>
  42 #include <linux/errno.h>
  43 #include <linux/linkage.h>
  44 #include <linux/smp.h>
  45
  46 #include <asm/cacheflush.h>
  47 #include <asm/tlbflush.h>
  48 #include <asm/smp_scu.h>
  49 #include <asm/pgalloc.h>
  50 #include <asm/suspend.h>
  51 #include <asm/hardware/cache-l2x0.h>
  52
  53 #include "soc.h"
  54 #include "common.h"
  55 #include "omap44xx.h"
  56 #include "omap4-sar-layout.h"
  57 #include "pm.h"
  58 #include "prcm_mpu44xx.h"
  59 #include "prcm_mpu54xx.h"
  60 #include "prminst44xx.h"
  61 #include "prcm44xx.h"
  62 #include "prm44xx.h"
  63 #include "prm-regbits-44xx.h"
  64
  65 #ifdef CONFIG_SMP
  66
  67 struct omap4_cpu_pm_info {
  68         struct powerdomain *pwrdm;
  69         void __iomem *scu_sar_addr;
  70         void __iomem *wkup_sar_addr;
  71         void __iomem *l2x0_sar_addr;
  72         void (*secondary_startup)(void);
  73 };
  74
  75 /**
  76  * struct cpu_pm_ops - CPU pm operations
  77  * @finish_suspend:     CPU suspend finisher function pointer
  78  * @resume:             CPU resume function pointer
  79  * @scu_prepare:        CPU Snoop Control program function pointer
  80  *
  81  * Structure holds functions pointer for CPU low power operations like
  82  * suspend, resume and scu programming.
  83  */
  84 struct cpu_pm_ops {
  85         int (*finish_suspend)(unsigned long cpu_state);
  86         void (*resume)(void);
  87         void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state);
  88 };
  89
  90 static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
  91 static struct powerdomain *mpuss_pd;
  92 static void __iomem *sar_base;
  93 static u32 cpu_context_offset;
  94
  95 static int default_finish_suspend(unsigned long cpu_state)
  96 {
  97         omap_do_wfi();
  98         return 0;
  99 }
 100
 101 static void dummy_cpu_resume(void)
 102 {}
 103
 104 static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state)
 105 {}
 106
 107 struct cpu_pm_ops omap_pm_ops = {
 108         .finish_suspend         = default_finish_suspend,
 109         .resume                 = dummy_cpu_resume,
 110         .scu_prepare            = dummy_scu_prepare,
 111 };
 112
 113 /*
 114  * Program the wakeup routine address for the CPU0 and CPU1
 115  * used for OFF or DORMANT wakeup.
 116  */
 117 static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
 118 {
 119         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
 120
 121         writel_relaxed(addr, pm_info->wkup_sar_addr);
 122 }
 123
 124 /*
 125  * Store the SCU power status value to scratchpad memory
 126  */
 127 static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
 128 {
 129         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
 130         u32 scu_pwr_st;
 131
 132         switch (cpu_state) {
 133         case PWRDM_POWER_RET:
 134                 scu_pwr_st = SCU_PM_DORMANT;
 135                 break;
 136         case PWRDM_POWER_OFF:
 137                 scu_pwr_st = SCU_PM_POWEROFF;
 138                 break;
 139         case PWRDM_POWER_ON:
 140         case PWRDM_POWER_INACTIVE:
 141         default:
 142                 scu_pwr_st = SCU_PM_NORMAL;
 143                 break;
 144         }
 145
 146         writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr);
 147 }
 148
 149 /* Helper functions for MPUSS OSWR */
 150 static inline void mpuss_clear_prev_logic_pwrst(void)
 151 {
 152         u32 reg;
 153
 154         reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 155                 OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
 156         omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION,
 157                 OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
 158 }
 159
 160 static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
 161 {
 162         u32 reg;
 163
 164         if (cpu_id) {
 165                 reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
 166                                         cpu_context_offset);
 167                 omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
 168                                         cpu_context_offset);
 169         } else {
 170                 reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
 171                                         cpu_context_offset);
 172                 omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
 173                                         cpu_context_offset);
 174         }
 175 }
 176
 177 /*
 178  * Store the CPU cluster state for L2X0 low power operations.
 179  */
 180 static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
 181 {
 182         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
 183
 184         writel_relaxed(save_state, pm_info->l2x0_sar_addr);
 185 }
 186
 187 /*
 188  * Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
 189  * in every restore MPUSS OFF path.
 190  */
 191 #ifdef CONFIG_CACHE_L2X0
 192 static void __init save_l2x0_context(void)
 193 {
 194         writel_relaxed(l2x0_saved_regs.aux_ctrl,
 195                      sar_base + L2X0_AUXCTRL_OFFSET);
 196         writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
 197                      sar_base + L2X0_PREFETCH_CTRL_OFFSET);
 198 }
 199 #else
 200 static void __init save_l2x0_context(void)
 201 {}
 202 #endif
 203
 204 /**
 205  * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
 206  * The purpose of this function is to manage low power programming
 207  * of OMAP4 MPUSS subsystem
 208  * @cpu : CPU ID
 209  * @power_state: Low power state.
 210  *
 211  * MPUSS states for the context save:
 212  * save_state =
 213  *      0 - Nothing lost and no need to save: MPUSS INACTIVE
 214  *      1 - CPUx L1 and logic lost: MPUSS CSWR
 215  *      2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
 216  *      3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
 217  */
 218 int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 219 {
 220         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
 221         unsigned int save_state = 0;
 222         unsigned int wakeup_cpu;
 223
 224         if (omap_rev() == OMAP4430_REV_ES1_0)
 225                 return -ENXIO;
 226
 227         switch (power_state) {
 228         case PWRDM_POWER_ON:
 229         case PWRDM_POWER_INACTIVE:
 230                 save_state = 0;
 231                 break;
 232         case PWRDM_POWER_OFF:
 233                 save_state = 1;
 234                 break;
 235         case PWRDM_POWER_RET:
 236         default:
 237                 /*
 238                  * CPUx CSWR is invalid hardware state. Also CPUx OSWR
 239                  * doesn't make much scense, since logic is lost and $L1
 240                  * needs to be cleaned because of coherency. This makes
 241                  * CPUx OSWR equivalent to CPUX OFF and hence not supported
 242                  */
 243                 WARN_ON(1);
 244                 return -ENXIO;
 245         }
 246
 247         pwrdm_pre_transition(NULL);
 248
 249         /*
 250          * Check MPUSS next state and save interrupt controller if needed.
 251          * In MPUSS OSWR or device OFF, interrupt controller  contest is lost.
 252          */
 253         mpuss_clear_prev_logic_pwrst();
 254         if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
 255                 (pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
 256                 save_state = 2;
 257
 258         cpu_clear_prev_logic_pwrst(cpu);
 259         pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
 260         set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume));
 261         omap_pm_ops.scu_prepare(cpu, power_state);
 262         l2x0_pwrst_prepare(cpu, save_state);
 263
 264         /*
 265          * Call low level function  with targeted low power state.
 266          */
 267         if (save_state)
 268                 cpu_suspend(save_state, omap_pm_ops.finish_suspend);
 269         else
 270                 omap_pm_ops.finish_suspend(save_state);
 271
 272         if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) && cpu)
 273                 gic_dist_enable();
 274
 275         /*
 276          * Restore the CPUx power state to ON otherwise CPUx
 277          * power domain can transitions to programmed low power
 278          * state while doing WFI outside the low powe code. On
 279          * secure devices, CPUx does WFI which can result in
 280          * domain transition
 281          */
 282         wakeup_cpu = smp_processor_id();
 283         pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
 284
 285         pwrdm_post_transition(NULL);
 286
 287         return 0;
 288 }
 289
 290 /**
 291  * omap4_hotplug_cpu: OMAP4 CPU hotplug entry
 292  * @cpu : CPU ID
 293  * @power_state: CPU low power state.
 294  */
 295 int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
 296 {
 297         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
 298         unsigned int cpu_state = 0;
 299
 300         if (omap_rev() == OMAP4430_REV_ES1_0)
 301                 return -ENXIO;
 302
 303         if (power_state == PWRDM_POWER_OFF)
 304                 cpu_state = 1;
 305
 306         pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
 307         pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
 308         set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup));
 309         omap_pm_ops.scu_prepare(cpu, power_state);
 310
 311         /*
 312          * CPU never retuns back if targeted power state is OFF mode.
 313          * CPU ONLINE follows normal CPU ONLINE ptah via
 314          * omap4_secondary_startup().
 315          */
 316         omap_pm_ops.finish_suspend(cpu_state);
 317
 318         pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
 319         return 0;
 320 }
 321
 322
 323 /*
 324  * Enable Mercury Fast HG retention mode by default.
 325  */
 326 static void enable_mercury_retention_mode(void)
 327 {
 328         u32 reg;
 329
 330         reg = omap4_prcm_mpu_read_inst_reg(OMAP54XX_PRCM_MPU_DEVICE_INST,
 331                                   OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
 332         /* Enable HG_EN, HG_RAMPUP = fast mode */
 333         reg |= BIT(24) | BIT(25);
 334         omap4_prcm_mpu_write_inst_reg(reg, OMAP54XX_PRCM_MPU_DEVICE_INST,
 335                                       OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
 336 }
 337
 338 /*
 339  * Initialise OMAP4 MPUSS
 340  */
 341 int __init omap4_mpuss_init(void)
 342 {
 343         struct omap4_cpu_pm_info *pm_info;
 344
 345         if (omap_rev() == OMAP4430_REV_ES1_0) {
 346                 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
 347                 return -ENODEV;
 348         }
 349
 350         sar_base = omap4_get_sar_ram_base();
 351
 352         /* Initilaise per CPU PM information */
 353         pm_info = &per_cpu(omap4_pm_info, 0x0);
 354         pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
 355         pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
 356         pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
 357         pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
 358         if (!pm_info->pwrdm) {
 359                 pr_err("Lookup failed for CPU0 pwrdm\n");
 360                 return -ENODEV;
 361         }
 362
 363         /* Clear CPU previous power domain state */
 364         pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
 365         cpu_clear_prev_logic_pwrst(0);
 366
 367         /* Initialise CPU0 power domain state to ON */
 368         pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
 369
 370         pm_info = &per_cpu(omap4_pm_info, 0x1);
 371         pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
 372         pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
 373         pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
 374         if (cpu_is_omap446x())
 375                 pm_info->secondary_startup = omap4460_secondary_startup;
 376         else
 377                 pm_info->secondary_startup = omap4_secondary_startup;
 378
 379         pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
 380         if (!pm_info->pwrdm) {
 381                 pr_err("Lookup failed for CPU1 pwrdm\n");
 382                 return -ENODEV;
 383         }
 384
 385         /* Clear CPU previous power domain state */
 386         pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
 387         cpu_clear_prev_logic_pwrst(1);
 388
 389         /* Initialise CPU1 power domain state to ON */
 390         pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
 391
 392         mpuss_pd = pwrdm_lookup("mpu_pwrdm");
 393         if (!mpuss_pd) {
 394                 pr_err("Failed to lookup MPUSS power domain\n");
 395                 return -ENODEV;
 396         }
 397         pwrdm_clear_all_prev_pwrst(mpuss_pd);
 398         mpuss_clear_prev_logic_pwrst();
 399
 400         /* Save device type on scratchpad for low level code to use */
 401         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
 402                 writel_relaxed(1, sar_base + OMAP_TYPE_OFFSET);
 403         else
 404                 writel_relaxed(0, sar_base + OMAP_TYPE_OFFSET);
 405
 406         save_l2x0_context();
 407
 408         if (cpu_is_omap44xx()) {
 409                 omap_pm_ops.finish_suspend = omap4_finish_suspend;
 410                 omap_pm_ops.resume = omap4_cpu_resume;
 411                 omap_pm_ops.scu_prepare = scu_pwrst_prepare;
 412                 cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET;
 413         } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
 414                 cpu_context_offset = OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET;
 415                 enable_mercury_retention_mode();
 416         }
 417
 418         return 0;
 419 }
 420
 421 #endif