2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * XXX handle crossbar/shared link difference for L3?
13 * XXX these should be marked initdata for multi-OMAP kernels
16 #include <linux/i2c-omap.h>
17 #include <linux/platform_data/spi-omap2-mcspi.h>
18 #include <linux/omap-dma.h>
19 #include <plat/dmtimer.h>
21 #include "omap_hwmod.h"
25 #include "omap_hwmod_common_data.h"
27 #include "cm-regbits-24xx.h"
28 #include "prm-regbits-24xx.h"
35 * OMAP2420 hardware module integration data
37 * All of the data in this section should be autogeneratable from the
38 * TI hardware database or other technical documentation. Data that
39 * is driver-specific or driver-kernel integration-specific belongs
48 static struct omap_hwmod_class iva1_hwmod_class = {
52 static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
53 { .name = "iva", .rst_shift = 8 },
56 static struct omap_hwmod omap2420_iva_hwmod = {
58 .class = &iva1_hwmod_class,
59 .clkdm_name = "iva1_clkdm",
60 .rst_lines = omap2420_iva_resets,
61 .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
62 .main_clk = "iva1_ifck",
66 static struct omap_hwmod_class dsp_hwmod_class = {
70 static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
71 { .name = "logic", .rst_shift = 0 },
72 { .name = "mmu", .rst_shift = 1 },
75 static struct omap_hwmod omap2420_dsp_hwmod = {
77 .class = &dsp_hwmod_class,
78 .clkdm_name = "dsp_clkdm",
79 .rst_lines = omap2420_dsp_resets,
80 .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
81 .main_clk = "dsp_fck",
85 static struct omap_hwmod_class_sysconfig i2c_sysc = {
89 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
90 .sysc_fields = &omap_hwmod_sysc_type1,
93 static struct omap_hwmod_class i2c_class = {
96 .rev = OMAP_I2C_IP_VERSION_1,
97 .reset = &omap_i2c_reset,
100 static struct omap_i2c_dev_attr i2c_dev_attr = {
101 .flags = OMAP_I2C_FLAG_NO_FIFO |
102 OMAP_I2C_FLAG_SIMPLE_CLOCK |
103 OMAP_I2C_FLAG_16BIT_DATA_REG |
104 OMAP_I2C_FLAG_BUS_SHIFT_2,
108 static struct omap_hwmod omap2420_i2c1_hwmod = {
110 .mpu_irqs = omap2_i2c1_mpu_irqs,
111 .sdma_reqs = omap2_i2c1_sdma_reqs,
112 .main_clk = "i2c1_fck",
115 .module_offs = CORE_MOD,
117 .module_bit = OMAP2420_EN_I2C1_SHIFT,
119 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
123 .dev_attr = &i2c_dev_attr,
125 * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
126 * while a transfer is active seems to cause the I2C block to
127 * timeout. Why? Good question."
129 .flags = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
133 static struct omap_hwmod omap2420_i2c2_hwmod = {
135 .mpu_irqs = omap2_i2c2_mpu_irqs,
136 .sdma_reqs = omap2_i2c2_sdma_reqs,
137 .main_clk = "i2c2_fck",
140 .module_offs = CORE_MOD,
142 .module_bit = OMAP2420_EN_I2C2_SHIFT,
144 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
148 .dev_attr = &i2c_dev_attr,
149 .flags = HWMOD_16BIT_REG,
153 static struct omap_dma_dev_attr dma_dev_attr = {
154 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
155 IS_CSSA_32 | IS_CDSA_32,
159 static struct omap_hwmod omap2420_dma_system_hwmod = {
161 .class = &omap2xxx_dma_hwmod_class,
162 .mpu_irqs = omap2_dma_system_irqs,
163 .main_clk = "core_l3_ck",
164 .dev_attr = &dma_dev_attr,
165 .flags = HWMOD_NO_IDLEST,
169 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
170 { .name = "dsp", .irq = 26 + OMAP_INTC_START, },
171 { .name = "iva", .irq = 34 + OMAP_INTC_START, },
175 static struct omap_hwmod omap2420_mailbox_hwmod = {
177 .class = &omap2xxx_mailbox_hwmod_class,
178 .mpu_irqs = omap2420_mailbox_irqs,
179 .main_clk = "mailboxes_ick",
183 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
184 .module_offs = CORE_MOD,
186 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
193 * multi channel buffered serial port controller
196 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
200 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
201 { .role = "pad_fck", .clk = "mcbsp_clks" },
202 { .role = "prcm_fck", .clk = "func_96m_ck" },
206 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
207 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
208 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
212 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
214 .class = &omap2420_mcbsp_hwmod_class,
215 .mpu_irqs = omap2420_mcbsp1_irqs,
216 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
217 .main_clk = "mcbsp1_fck",
221 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
222 .module_offs = CORE_MOD,
224 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
227 .opt_clks = mcbsp_opt_clks,
228 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
232 static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
233 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
234 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
238 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
240 .class = &omap2420_mcbsp_hwmod_class,
241 .mpu_irqs = omap2420_mcbsp2_irqs,
242 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
243 .main_clk = "mcbsp2_fck",
247 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
248 .module_offs = CORE_MOD,
250 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
253 .opt_clks = mcbsp_opt_clks,
254 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
257 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
261 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
262 .sysc_fields = &omap_hwmod_sysc_type1,
265 static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
267 .sysc = &omap2420_msdi_sysc,
268 .reset = &omap_msdi_reset,
272 static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
273 { .irq = 83 + OMAP_INTC_START, },
277 static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
278 { .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
279 { .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
283 static struct omap_hwmod omap2420_msdi1_hwmod = {
285 .class = &omap2420_msdi_hwmod_class,
286 .mpu_irqs = omap2420_msdi1_irqs,
287 .sdma_reqs = omap2420_msdi1_sdma_reqs,
288 .main_clk = "mmc_fck",
292 .module_bit = OMAP2420_EN_MMC_SHIFT,
293 .module_offs = CORE_MOD,
295 .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
298 .flags = HWMOD_16BIT_REG,
302 static struct omap_hwmod omap2420_hdq1w_hwmod = {
304 .mpu_irqs = omap2_hdq1w_mpu_irqs,
305 .main_clk = "hdq_fck",
308 .module_offs = CORE_MOD,
310 .module_bit = OMAP24XX_EN_HDQ_SHIFT,
312 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
315 .class = &omap2_hdq1w_class,
322 /* L4 CORE -> I2C1 interface */
323 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
324 .master = &omap2xxx_l4_core_hwmod,
325 .slave = &omap2420_i2c1_hwmod,
327 .addr = omap2_i2c1_addr_space,
328 .user = OCP_USER_MPU | OCP_USER_SDMA,
331 /* L4 CORE -> I2C2 interface */
332 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
333 .master = &omap2xxx_l4_core_hwmod,
334 .slave = &omap2420_i2c2_hwmod,
336 .addr = omap2_i2c2_addr_space,
337 .user = OCP_USER_MPU | OCP_USER_SDMA,
340 /* IVA <- L3 interface */
341 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
342 .master = &omap2xxx_l3_main_hwmod,
343 .slave = &omap2420_iva_hwmod,
345 .user = OCP_USER_MPU | OCP_USER_SDMA,
348 /* DSP <- L3 interface */
349 static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
350 .master = &omap2xxx_l3_main_hwmod,
351 .slave = &omap2420_dsp_hwmod,
353 .user = OCP_USER_MPU | OCP_USER_SDMA,
356 static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
358 .pa_start = 0x48028000,
359 .pa_end = 0x48028000 + SZ_1K - 1,
360 .flags = ADDR_TYPE_RT
365 /* l4_wkup -> timer1 */
366 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
367 .master = &omap2xxx_l4_wkup_hwmod,
368 .slave = &omap2xxx_timer1_hwmod,
370 .addr = omap2420_timer1_addrs,
371 .user = OCP_USER_MPU | OCP_USER_SDMA,
374 /* l4_wkup -> wd_timer2 */
375 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
377 .pa_start = 0x48022000,
378 .pa_end = 0x4802207f,
379 .flags = ADDR_TYPE_RT
384 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
385 .master = &omap2xxx_l4_wkup_hwmod,
386 .slave = &omap2xxx_wd_timer2_hwmod,
387 .clk = "mpu_wdt_ick",
388 .addr = omap2420_wd_timer2_addrs,
389 .user = OCP_USER_MPU | OCP_USER_SDMA,
392 /* l4_wkup -> gpio1 */
393 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
395 .pa_start = 0x48018000,
396 .pa_end = 0x480181ff,
397 .flags = ADDR_TYPE_RT
402 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
403 .master = &omap2xxx_l4_wkup_hwmod,
404 .slave = &omap2xxx_gpio1_hwmod,
406 .addr = omap2420_gpio1_addr_space,
407 .user = OCP_USER_MPU | OCP_USER_SDMA,
410 /* l4_wkup -> gpio2 */
411 static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
413 .pa_start = 0x4801a000,
414 .pa_end = 0x4801a1ff,
415 .flags = ADDR_TYPE_RT
420 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
421 .master = &omap2xxx_l4_wkup_hwmod,
422 .slave = &omap2xxx_gpio2_hwmod,
424 .addr = omap2420_gpio2_addr_space,
425 .user = OCP_USER_MPU | OCP_USER_SDMA,
428 /* l4_wkup -> gpio3 */
429 static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
431 .pa_start = 0x4801c000,
432 .pa_end = 0x4801c1ff,
433 .flags = ADDR_TYPE_RT
438 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
439 .master = &omap2xxx_l4_wkup_hwmod,
440 .slave = &omap2xxx_gpio3_hwmod,
442 .addr = omap2420_gpio3_addr_space,
443 .user = OCP_USER_MPU | OCP_USER_SDMA,
446 /* l4_wkup -> gpio4 */
447 static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
449 .pa_start = 0x4801e000,
450 .pa_end = 0x4801e1ff,
451 .flags = ADDR_TYPE_RT
456 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
457 .master = &omap2xxx_l4_wkup_hwmod,
458 .slave = &omap2xxx_gpio4_hwmod,
460 .addr = omap2420_gpio4_addr_space,
461 .user = OCP_USER_MPU | OCP_USER_SDMA,
464 /* dma_system -> L3 */
465 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
466 .master = &omap2420_dma_system_hwmod,
467 .slave = &omap2xxx_l3_main_hwmod,
469 .user = OCP_USER_MPU | OCP_USER_SDMA,
472 /* l4_core -> dma_system */
473 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
474 .master = &omap2xxx_l4_core_hwmod,
475 .slave = &omap2420_dma_system_hwmod,
477 .addr = omap2_dma_system_addrs,
478 .user = OCP_USER_MPU | OCP_USER_SDMA,
481 /* l4_core -> mailbox */
482 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
483 .master = &omap2xxx_l4_core_hwmod,
484 .slave = &omap2420_mailbox_hwmod,
485 .addr = omap2_mailbox_addrs,
486 .user = OCP_USER_MPU | OCP_USER_SDMA,
489 /* l4_core -> mcbsp1 */
490 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
491 .master = &omap2xxx_l4_core_hwmod,
492 .slave = &omap2420_mcbsp1_hwmod,
494 .addr = omap2_mcbsp1_addrs,
495 .user = OCP_USER_MPU | OCP_USER_SDMA,
498 /* l4_core -> mcbsp2 */
499 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
500 .master = &omap2xxx_l4_core_hwmod,
501 .slave = &omap2420_mcbsp2_hwmod,
503 .addr = omap2xxx_mcbsp2_addrs,
504 .user = OCP_USER_MPU | OCP_USER_SDMA,
507 static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
509 .pa_start = 0x4809c000,
510 .pa_end = 0x4809c000 + SZ_128 - 1,
511 .flags = ADDR_TYPE_RT,
516 /* l4_core -> msdi1 */
517 static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
518 .master = &omap2xxx_l4_core_hwmod,
519 .slave = &omap2420_msdi1_hwmod,
521 .addr = omap2420_msdi1_addrs,
522 .user = OCP_USER_MPU | OCP_USER_SDMA,
525 /* l4_core -> hdq1w interface */
526 static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
527 .master = &omap2xxx_l4_core_hwmod,
528 .slave = &omap2420_hdq1w_hwmod,
530 .addr = omap2_hdq1w_addr_space,
531 .user = OCP_USER_MPU | OCP_USER_SDMA,
532 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
536 /* l4_wkup -> 32ksync_counter */
537 static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
539 .pa_start = 0x48004000,
540 .pa_end = 0x4800401f,
541 .flags = ADDR_TYPE_RT
546 static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = {
548 .pa_start = 0x6800a000,
549 .pa_end = 0x6800afff,
550 .flags = ADDR_TYPE_RT
555 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
556 .master = &omap2xxx_l4_wkup_hwmod,
557 .slave = &omap2xxx_counter_32k_hwmod,
558 .clk = "sync_32k_ick",
559 .addr = omap2420_counter_32k_addrs,
560 .user = OCP_USER_MPU | OCP_USER_SDMA,
563 static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
564 .master = &omap2xxx_l3_main_hwmod,
565 .slave = &omap2xxx_gpmc_hwmod,
567 .addr = omap2420_gpmc_addrs,
568 .user = OCP_USER_MPU | OCP_USER_SDMA,
571 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
572 &omap2xxx_l3_main__l4_core,
573 &omap2xxx_mpu__l3_main,
575 &omap2xxx_l4_core__mcspi1,
576 &omap2xxx_l4_core__mcspi2,
577 &omap2xxx_l4_core__l4_wkup,
578 &omap2_l4_core__uart1,
579 &omap2_l4_core__uart2,
580 &omap2_l4_core__uart3,
581 &omap2420_l4_core__i2c1,
582 &omap2420_l4_core__i2c2,
585 &omap2420_l4_wkup__timer1,
586 &omap2xxx_l4_core__timer2,
587 &omap2xxx_l4_core__timer3,
588 &omap2xxx_l4_core__timer4,
589 &omap2xxx_l4_core__timer5,
590 &omap2xxx_l4_core__timer6,
591 &omap2xxx_l4_core__timer7,
592 &omap2xxx_l4_core__timer8,
593 &omap2xxx_l4_core__timer9,
594 &omap2xxx_l4_core__timer10,
595 &omap2xxx_l4_core__timer11,
596 &omap2xxx_l4_core__timer12,
597 &omap2420_l4_wkup__wd_timer2,
598 &omap2xxx_l4_core__dss,
599 &omap2xxx_l4_core__dss_dispc,
600 &omap2xxx_l4_core__dss_rfbi,
601 &omap2xxx_l4_core__dss_venc,
602 &omap2420_l4_wkup__gpio1,
603 &omap2420_l4_wkup__gpio2,
604 &omap2420_l4_wkup__gpio3,
605 &omap2420_l4_wkup__gpio4,
606 &omap2420_dma_system__l3,
607 &omap2420_l4_core__dma_system,
608 &omap2420_l4_core__mailbox,
609 &omap2420_l4_core__mcbsp1,
610 &omap2420_l4_core__mcbsp2,
611 &omap2420_l4_core__msdi1,
612 &omap2xxx_l4_core__rng,
613 &omap2xxx_l4_core__sham,
614 &omap2xxx_l4_core__aes,
615 &omap2420_l4_core__hdq1w,
616 &omap2420_l4_wkup__counter_32k,
621 int __init omap2420_hwmod_init(void)
624 return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);