2 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * XXX handle crossbar/shared link difference for L3?
13 * XXX these should be marked initdata for multi-OMAP kernels
16 #include <linux/i2c-omap.h>
17 #include <linux/platform_data/asoc-ti-mcbsp.h>
18 #include <linux/platform_data/spi-omap2-mcspi.h>
19 #include <linux/omap-dma.h>
20 #include <linux/platform_data/mailbox-omap.h>
21 #include <plat/dmtimer.h>
23 #include "omap_hwmod.h"
28 #include "omap_hwmod_common_data.h"
29 #include "prm-regbits-24xx.h"
30 #include "cm-regbits-24xx.h"
35 * OMAP2430 hardware module integration data
37 * All of the data in this section should be autogeneratable from the
38 * TI hardware database or other technical documentation. Data that
39 * is driver-specific or driver-kernel integration-specific belongs
48 static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
49 { .name = "logic", .rst_shift = 0 },
50 { .name = "mmu", .rst_shift = 1 },
53 static struct omap_hwmod omap2430_iva_hwmod = {
55 .class = &iva_hwmod_class,
56 .clkdm_name = "dsp_clkdm",
57 .rst_lines = omap2430_iva_resets,
58 .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets),
59 .main_clk = "dsp_fck",
63 static struct omap_hwmod_class_sysconfig i2c_sysc = {
67 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
68 SYSS_HAS_RESET_STATUS),
69 .sysc_fields = &omap_hwmod_sysc_type1,
72 static struct omap_hwmod_class i2c_class = {
75 .rev = OMAP_I2C_IP_VERSION_1,
76 .reset = &omap_i2c_reset,
79 static struct omap_i2c_dev_attr i2c_dev_attr = {
80 .fifo_depth = 8, /* bytes */
81 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
82 OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
86 static struct omap_hwmod omap2430_i2c1_hwmod = {
88 .flags = HWMOD_16BIT_REG,
89 .main_clk = "i2chs1_fck",
93 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
94 * I2CHS IP's do not follow the usual pattern.
95 * prcm_reg_id alone cannot be used to program
96 * the iclk and fclk. Needs to be handled using
97 * additional flags when clk handling is moved
100 .module_offs = CORE_MOD,
102 .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
104 .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
108 .dev_attr = &i2c_dev_attr,
112 static struct omap_hwmod omap2430_i2c2_hwmod = {
114 .flags = HWMOD_16BIT_REG,
115 .main_clk = "i2chs2_fck",
118 .module_offs = CORE_MOD,
120 .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
122 .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
126 .dev_attr = &i2c_dev_attr,
130 static struct omap_hwmod omap2430_gpio5_hwmod = {
132 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
133 .main_clk = "gpio5_fck",
137 .module_bit = OMAP2430_EN_GPIO5_SHIFT,
138 .module_offs = CORE_MOD,
140 .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
143 .class = &omap2xxx_gpio_hwmod_class,
144 .dev_attr = &omap2xxx_gpio_dev_attr,
148 static struct omap_dma_dev_attr dma_dev_attr = {
149 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
150 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
154 static struct omap_hwmod omap2430_dma_system_hwmod = {
156 .class = &omap2xxx_dma_hwmod_class,
157 .mpu_irqs = omap2_dma_system_irqs,
158 .main_clk = "core_l3_ck",
159 .dev_attr = &dma_dev_attr,
160 .flags = HWMOD_NO_IDLEST,
164 static struct omap_mbox_dev_info omap2430_mailbox_info[] = {
165 { .name = "dsp", .tx_id = 0, .rx_id = 1 },
168 static struct omap_mbox_pdata omap2430_mailbox_attrs = {
171 .info_cnt = ARRAY_SIZE(omap2430_mailbox_info),
172 .info = omap2430_mailbox_info,
175 static struct omap_hwmod omap2430_mailbox_hwmod = {
177 .class = &omap2xxx_mailbox_hwmod_class,
178 .main_clk = "mailboxes_ick",
182 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
183 .module_offs = CORE_MOD,
185 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
188 .dev_attr = &omap2430_mailbox_attrs,
192 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
196 static struct omap_hwmod omap2430_mcspi3_hwmod = {
198 .main_clk = "mcspi3_fck",
201 .module_offs = CORE_MOD,
203 .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
205 .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
208 .class = &omap2xxx_mcspi_class,
209 .dev_attr = &omap_mcspi3_dev_attr,
213 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
217 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
218 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
220 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
221 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
222 .sysc_fields = &omap_hwmod_sysc_type1,
225 static struct omap_hwmod_class usbotg_class = {
227 .sysc = &omap2430_usbhsotg_sysc,
231 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
232 .name = "usb_otg_hs",
233 .main_clk = "usbhs_ick",
237 .module_bit = OMAP2430_EN_USBHS_MASK,
238 .module_offs = CORE_MOD,
240 .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
243 .class = &usbotg_class,
245 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
246 * broken when autoidle is enabled
247 * workaround is to disable the autoidle bit at module level.
249 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
250 | HWMOD_SWSUP_MSTANDBY,
255 * multi channel buffered serial port controller
258 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
261 .sysc_flags = (SYSC_HAS_SOFTRESET),
262 .sysc_fields = &omap_hwmod_sysc_type1,
265 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
267 .sysc = &omap2430_mcbsp_sysc,
268 .rev = MCBSP_CONFIG_TYPE2,
271 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
272 { .role = "pad_fck", .clk = "mcbsp_clks" },
273 { .role = "prcm_fck", .clk = "func_96m_ck" },
277 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
279 .class = &omap2430_mcbsp_hwmod_class,
280 .main_clk = "mcbsp1_fck",
284 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
285 .module_offs = CORE_MOD,
287 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
290 .opt_clks = mcbsp_opt_clks,
291 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
295 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
297 .class = &omap2430_mcbsp_hwmod_class,
298 .main_clk = "mcbsp2_fck",
302 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
303 .module_offs = CORE_MOD,
305 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
308 .opt_clks = mcbsp_opt_clks,
309 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
313 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
315 .class = &omap2430_mcbsp_hwmod_class,
316 .main_clk = "mcbsp3_fck",
320 .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
321 .module_offs = CORE_MOD,
323 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
326 .opt_clks = mcbsp_opt_clks,
327 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
331 static struct omap_hwmod omap2430_mcbsp4_hwmod = {
333 .class = &omap2430_mcbsp_hwmod_class,
334 .main_clk = "mcbsp4_fck",
338 .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
339 .module_offs = CORE_MOD,
341 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
344 .opt_clks = mcbsp_opt_clks,
345 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
349 static struct omap_hwmod omap2430_mcbsp5_hwmod = {
351 .class = &omap2430_mcbsp_hwmod_class,
352 .main_clk = "mcbsp5_fck",
356 .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
357 .module_offs = CORE_MOD,
359 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
362 .opt_clks = mcbsp_opt_clks,
363 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
366 /* MMC/SD/SDIO common */
367 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
371 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
372 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
373 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
374 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
375 .sysc_fields = &omap_hwmod_sysc_type1,
378 static struct omap_hwmod_class omap2430_mmc_class = {
380 .sysc = &omap2430_mmc_sysc,
384 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
385 { .role = "dbck", .clk = "mmchsdb1_fck" },
388 static struct omap_mmc_dev_attr mmc1_dev_attr = {
389 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
392 static struct omap_hwmod omap2430_mmc1_hwmod = {
394 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
395 .opt_clks = omap2430_mmc1_opt_clks,
396 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
397 .main_clk = "mmchs1_fck",
400 .module_offs = CORE_MOD,
402 .module_bit = OMAP2430_EN_MMCHS1_SHIFT,
404 .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
407 .dev_attr = &mmc1_dev_attr,
408 .class = &omap2430_mmc_class,
412 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
413 { .role = "dbck", .clk = "mmchsdb2_fck" },
416 static struct omap_hwmod omap2430_mmc2_hwmod = {
418 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
419 .opt_clks = omap2430_mmc2_opt_clks,
420 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
421 .main_clk = "mmchs2_fck",
424 .module_offs = CORE_MOD,
426 .module_bit = OMAP2430_EN_MMCHS2_SHIFT,
428 .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
431 .class = &omap2430_mmc_class,
435 static struct omap_hwmod omap2430_hdq1w_hwmod = {
437 .main_clk = "hdq_fck",
440 .module_offs = CORE_MOD,
442 .module_bit = OMAP24XX_EN_HDQ_SHIFT,
444 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
447 .class = &omap2_hdq1w_class,
454 /* L3 -> L4_CORE interface */
455 /* l3_core -> usbhsotg interface */
456 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
457 .master = &omap2430_usbhsotg_hwmod,
458 .slave = &omap2xxx_l3_main_hwmod,
460 .user = OCP_USER_MPU,
463 /* L4 CORE -> I2C1 interface */
464 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
465 .master = &omap2xxx_l4_core_hwmod,
466 .slave = &omap2430_i2c1_hwmod,
468 .user = OCP_USER_MPU | OCP_USER_SDMA,
471 /* L4 CORE -> I2C2 interface */
472 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
473 .master = &omap2xxx_l4_core_hwmod,
474 .slave = &omap2430_i2c2_hwmod,
476 .user = OCP_USER_MPU | OCP_USER_SDMA,
479 /* l4_core ->usbhsotg interface */
480 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
481 .master = &omap2xxx_l4_core_hwmod,
482 .slave = &omap2430_usbhsotg_hwmod,
484 .user = OCP_USER_MPU,
487 /* L4 CORE -> MMC1 interface */
488 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
489 .master = &omap2xxx_l4_core_hwmod,
490 .slave = &omap2430_mmc1_hwmod,
492 .user = OCP_USER_MPU | OCP_USER_SDMA,
495 /* L4 CORE -> MMC2 interface */
496 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
497 .master = &omap2xxx_l4_core_hwmod,
498 .slave = &omap2430_mmc2_hwmod,
500 .user = OCP_USER_MPU | OCP_USER_SDMA,
503 /* l4 core -> mcspi3 interface */
504 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
505 .master = &omap2xxx_l4_core_hwmod,
506 .slave = &omap2430_mcspi3_hwmod,
508 .user = OCP_USER_MPU | OCP_USER_SDMA,
511 /* IVA2 <- L3 interface */
512 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
513 .master = &omap2xxx_l3_main_hwmod,
514 .slave = &omap2430_iva_hwmod,
516 .user = OCP_USER_MPU | OCP_USER_SDMA,
519 /* l4_wkup -> timer1 */
520 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
521 .master = &omap2xxx_l4_wkup_hwmod,
522 .slave = &omap2xxx_timer1_hwmod,
524 .user = OCP_USER_MPU | OCP_USER_SDMA,
527 /* l4_wkup -> wd_timer2 */
528 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
529 .master = &omap2xxx_l4_wkup_hwmod,
530 .slave = &omap2xxx_wd_timer2_hwmod,
531 .clk = "mpu_wdt_ick",
532 .user = OCP_USER_MPU | OCP_USER_SDMA,
535 /* l4_wkup -> gpio1 */
536 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
537 .master = &omap2xxx_l4_wkup_hwmod,
538 .slave = &omap2xxx_gpio1_hwmod,
540 .user = OCP_USER_MPU | OCP_USER_SDMA,
543 /* l4_wkup -> gpio2 */
544 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
545 .master = &omap2xxx_l4_wkup_hwmod,
546 .slave = &omap2xxx_gpio2_hwmod,
548 .user = OCP_USER_MPU | OCP_USER_SDMA,
551 /* l4_wkup -> gpio3 */
552 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
553 .master = &omap2xxx_l4_wkup_hwmod,
554 .slave = &omap2xxx_gpio3_hwmod,
556 .user = OCP_USER_MPU | OCP_USER_SDMA,
559 /* l4_wkup -> gpio4 */
560 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
561 .master = &omap2xxx_l4_wkup_hwmod,
562 .slave = &omap2xxx_gpio4_hwmod,
564 .user = OCP_USER_MPU | OCP_USER_SDMA,
567 /* l4_core -> gpio5 */
568 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
569 .master = &omap2xxx_l4_core_hwmod,
570 .slave = &omap2430_gpio5_hwmod,
572 .user = OCP_USER_MPU | OCP_USER_SDMA,
575 /* dma_system -> L3 */
576 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
577 .master = &omap2430_dma_system_hwmod,
578 .slave = &omap2xxx_l3_main_hwmod,
580 .user = OCP_USER_MPU | OCP_USER_SDMA,
583 /* l4_core -> dma_system */
584 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
585 .master = &omap2xxx_l4_core_hwmod,
586 .slave = &omap2430_dma_system_hwmod,
588 .addr = omap2_dma_system_addrs,
589 .user = OCP_USER_MPU | OCP_USER_SDMA,
592 /* l4_core -> mailbox */
593 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
594 .master = &omap2xxx_l4_core_hwmod,
595 .slave = &omap2430_mailbox_hwmod,
596 .user = OCP_USER_MPU | OCP_USER_SDMA,
599 /* l4_core -> mcbsp1 */
600 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
601 .master = &omap2xxx_l4_core_hwmod,
602 .slave = &omap2430_mcbsp1_hwmod,
604 .user = OCP_USER_MPU | OCP_USER_SDMA,
607 /* l4_core -> mcbsp2 */
608 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
609 .master = &omap2xxx_l4_core_hwmod,
610 .slave = &omap2430_mcbsp2_hwmod,
612 .user = OCP_USER_MPU | OCP_USER_SDMA,
615 /* l4_core -> mcbsp3 */
616 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
617 .master = &omap2xxx_l4_core_hwmod,
618 .slave = &omap2430_mcbsp3_hwmod,
620 .user = OCP_USER_MPU | OCP_USER_SDMA,
623 /* l4_core -> mcbsp4 */
624 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
625 .master = &omap2xxx_l4_core_hwmod,
626 .slave = &omap2430_mcbsp4_hwmod,
628 .user = OCP_USER_MPU | OCP_USER_SDMA,
631 /* l4_core -> mcbsp5 */
632 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
633 .master = &omap2xxx_l4_core_hwmod,
634 .slave = &omap2430_mcbsp5_hwmod,
636 .user = OCP_USER_MPU | OCP_USER_SDMA,
639 /* l4_core -> hdq1w */
640 static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
641 .master = &omap2xxx_l4_core_hwmod,
642 .slave = &omap2430_hdq1w_hwmod,
644 .user = OCP_USER_MPU | OCP_USER_SDMA,
645 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
648 /* l4_wkup -> 32ksync_counter */
649 static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
650 .master = &omap2xxx_l4_wkup_hwmod,
651 .slave = &omap2xxx_counter_32k_hwmod,
652 .clk = "sync_32k_ick",
653 .user = OCP_USER_MPU | OCP_USER_SDMA,
656 static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
657 .master = &omap2xxx_l3_main_hwmod,
658 .slave = &omap2xxx_gpmc_hwmod,
660 .user = OCP_USER_MPU | OCP_USER_SDMA,
663 static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
664 &omap2xxx_l3_main__l4_core,
665 &omap2xxx_mpu__l3_main,
667 &omap2430_usbhsotg__l3,
668 &omap2430_l4_core__i2c1,
669 &omap2430_l4_core__i2c2,
670 &omap2xxx_l4_core__l4_wkup,
671 &omap2_l4_core__uart1,
672 &omap2_l4_core__uart2,
673 &omap2_l4_core__uart3,
674 &omap2430_l4_core__usbhsotg,
675 &omap2430_l4_core__mmc1,
676 &omap2430_l4_core__mmc2,
677 &omap2xxx_l4_core__mcspi1,
678 &omap2xxx_l4_core__mcspi2,
679 &omap2430_l4_core__mcspi3,
681 &omap2430_l4_wkup__timer1,
682 &omap2xxx_l4_core__timer2,
683 &omap2xxx_l4_core__timer3,
684 &omap2xxx_l4_core__timer4,
685 &omap2xxx_l4_core__timer5,
686 &omap2xxx_l4_core__timer6,
687 &omap2xxx_l4_core__timer7,
688 &omap2xxx_l4_core__timer8,
689 &omap2xxx_l4_core__timer9,
690 &omap2xxx_l4_core__timer10,
691 &omap2xxx_l4_core__timer11,
692 &omap2xxx_l4_core__timer12,
693 &omap2430_l4_wkup__wd_timer2,
694 &omap2xxx_l4_core__dss,
695 &omap2xxx_l4_core__dss_dispc,
696 &omap2xxx_l4_core__dss_rfbi,
697 &omap2xxx_l4_core__dss_venc,
698 &omap2430_l4_wkup__gpio1,
699 &omap2430_l4_wkup__gpio2,
700 &omap2430_l4_wkup__gpio3,
701 &omap2430_l4_wkup__gpio4,
702 &omap2430_l4_core__gpio5,
703 &omap2430_dma_system__l3,
704 &omap2430_l4_core__dma_system,
705 &omap2430_l4_core__mailbox,
706 &omap2430_l4_core__mcbsp1,
707 &omap2430_l4_core__mcbsp2,
708 &omap2430_l4_core__mcbsp3,
709 &omap2430_l4_core__mcbsp4,
710 &omap2430_l4_core__mcbsp5,
711 &omap2430_l4_core__hdq1w,
712 &omap2xxx_l4_core__rng,
713 &omap2xxx_l4_core__sham,
714 &omap2xxx_l4_core__aes,
715 &omap2430_l4_wkup__counter_32k,
720 int __init omap2430_hwmod_init(void)
723 return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);