2 * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
4 * Copyright (C) 2011 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <plat/omap_hwmod.h>
12 #include <plat/serial.h>
14 #include <plat/common.h>
16 #include <mach/irqs.h>
18 #include "omap_hwmod_common_data.h"
22 static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
26 .sysc_flags = (SYSC_HAS_SIDLEMODE |
27 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
28 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
29 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
30 .sysc_fields = &omap_hwmod_sysc_type1,
33 struct omap_hwmod_class omap2_uart_class = {
35 .sysc = &omap2_uart_sysc,
43 static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
47 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
48 SYSS_HAS_RESET_STATUS),
49 .sysc_fields = &omap_hwmod_sysc_type1,
52 struct omap_hwmod_class omap2_dss_hwmod_class = {
54 .sysc = &omap2_dss_sysc,
55 .reset = omap_dss_reset,
63 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
67 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
68 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
69 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
70 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
71 .sysc_fields = &omap_hwmod_sysc_type1,
74 struct omap_hwmod_class omap2_dispc_hwmod_class = {
76 .sysc = &omap2_dispc_sysc,
81 * remote frame buffer interface
84 static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
88 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
90 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
91 .sysc_fields = &omap_hwmod_sysc_type1,
94 struct omap_hwmod_class omap2_rfbi_hwmod_class = {
96 .sysc = &omap2_rfbi_sysc,
104 struct omap_hwmod_class omap2_venc_hwmod_class = {
109 /* Common DMA request line data */
110 struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
111 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
112 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
116 struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
117 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
118 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
122 struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
123 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
124 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
128 struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
129 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
130 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
134 struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
135 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
136 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
140 struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
141 { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
142 { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
143 { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
144 { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
145 { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
146 { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
147 { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
148 { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
152 struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
153 { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
154 { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
155 { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
156 { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
160 struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
161 { .name = "rx", .dma_req = 32 },
162 { .name = "tx", .dma_req = 31 },
166 struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
167 { .name = "rx", .dma_req = 34 },
168 { .name = "tx", .dma_req = 33 },
172 struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
173 { .name = "rx", .dma_req = 18 },
174 { .name = "tx", .dma_req = 17 },
178 /* Other IP block data */
182 * omap_hwmod class data
185 struct omap_hwmod_class l3_hwmod_class = {
189 struct omap_hwmod_class l4_hwmod_class = {
193 struct omap_hwmod_class mpu_hwmod_class = {
197 struct omap_hwmod_class iva_hwmod_class = {
201 /* Common MPU IRQ line data */
203 struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
208 struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
213 struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
218 struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
223 struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
228 struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
233 struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
238 struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
243 struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
248 struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
253 struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
258 struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
259 { .irq = INT_24XX_UART1_IRQ, },
263 struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
264 { .irq = INT_24XX_UART2_IRQ, },
268 struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
269 { .irq = INT_24XX_UART3_IRQ, },
273 struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
278 struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
279 { .irq = INT_24XX_I2C1_IRQ, },
283 struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
284 { .irq = INT_24XX_I2C2_IRQ, },
288 struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
289 { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
293 struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
294 { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
298 struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
299 { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
303 struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
304 { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
308 struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
309 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
310 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
311 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
312 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
316 struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
321 struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {