3 * Copyright (C) 2013 Texas Instruments Incorporated
5 * Hwmod common for AM335x and AM43x
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/platform_data/gpio-omap.h>
18 #include <linux/platform_data/hsmmc-omap.h>
19 #include <linux/platform_data/spi-omap2-mcspi.h>
20 #include "omap_hwmod.h"
25 #include "omap_hwmod_33xx_43xx_common_data.h"
29 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
30 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
31 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
32 #define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag))
36 * instance(s): l3_main, l3_s, l3_instr
38 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
42 struct omap_hwmod am33xx_l3_main_hwmod = {
44 .class = &am33xx_l3_hwmod_class,
45 .clkdm_name = "l3_clkdm",
46 .flags = HWMOD_INIT_NO_IDLE,
47 .main_clk = "l3_gclk",
50 .modulemode = MODULEMODE_SWCTRL,
56 struct omap_hwmod am33xx_l3_s_hwmod = {
58 .class = &am33xx_l3_hwmod_class,
59 .clkdm_name = "l3s_clkdm",
63 struct omap_hwmod am33xx_l3_instr_hwmod = {
65 .class = &am33xx_l3_hwmod_class,
66 .clkdm_name = "l3_clkdm",
67 .flags = HWMOD_INIT_NO_IDLE,
68 .main_clk = "l3_gclk",
71 .modulemode = MODULEMODE_SWCTRL,
78 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
80 struct omap_hwmod_class am33xx_l4_hwmod_class = {
85 struct omap_hwmod am33xx_l4_ls_hwmod = {
87 .class = &am33xx_l4_hwmod_class,
88 .clkdm_name = "l4ls_clkdm",
89 .flags = HWMOD_INIT_NO_IDLE,
90 .main_clk = "l4ls_gclk",
93 .modulemode = MODULEMODE_SWCTRL,
99 struct omap_hwmod am33xx_l4_wkup_hwmod = {
101 .class = &am33xx_l4_hwmod_class,
102 .clkdm_name = "l4_wkup_clkdm",
103 .flags = HWMOD_INIT_NO_IDLE,
106 .modulemode = MODULEMODE_SWCTRL,
114 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
118 struct omap_hwmod am33xx_mpu_hwmod = {
120 .class = &am33xx_mpu_hwmod_class,
121 .clkdm_name = "mpu_clkdm",
122 .flags = HWMOD_INIT_NO_IDLE,
123 .main_clk = "dpll_mpu_m2_ck",
126 .modulemode = MODULEMODE_SWCTRL,
133 * Wakeup controller sub-system under wakeup domain
135 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
141 * Programmable Real-Time Unit and Industrial Communication Subsystem
143 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
147 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
148 { .name = "pruss", .rst_shift = 1 },
152 /* Pseudo hwmod for reset control purpose only */
153 struct omap_hwmod am33xx_pruss_hwmod = {
155 .class = &am33xx_pruss_hwmod_class,
156 .clkdm_name = "pruss_ocp_clkdm",
157 .main_clk = "pruss_ocp_gclk",
160 .modulemode = MODULEMODE_SWCTRL,
163 .rst_lines = am33xx_pruss_resets,
164 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
168 /* Pseudo hwmod for reset control purpose only */
169 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
173 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
174 { .name = "gfx", .rst_shift = 0, .st_shift = 0},
177 struct omap_hwmod am33xx_gfx_hwmod = {
179 .class = &am33xx_gfx_hwmod_class,
180 .clkdm_name = "gfx_l3_clkdm",
181 .main_clk = "gfx_fck_div_ck",
184 .modulemode = MODULEMODE_SWCTRL,
187 .rst_lines = am33xx_gfx_resets,
188 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
193 * power and reset manager (whole prcm infrastructure)
195 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
200 struct omap_hwmod am33xx_prcm_hwmod = {
202 .class = &am33xx_prcm_hwmod_class,
203 .clkdm_name = "l4_wkup_clkdm",
210 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
214 struct omap_hwmod_class am33xx_emif_hwmod_class = {
216 .sysc = &am33xx_emif_sysc,
222 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
226 .sysc_flags = SYSS_HAS_RESET_STATUS,
229 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
231 .sysc = &am33xx_aes0_sysc,
234 struct omap_hwmod am33xx_aes0_hwmod = {
236 .class = &am33xx_aes0_hwmod_class,
237 .clkdm_name = "l3_clkdm",
238 .main_clk = "aes0_fck",
241 .modulemode = MODULEMODE_SWCTRL,
246 /* sha0 HIB2 (the 'P' (public) device) */
247 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
251 .sysc_flags = SYSS_HAS_RESET_STATUS,
254 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
256 .sysc = &am33xx_sha0_sysc,
259 struct omap_hwmod am33xx_sha0_hwmod = {
261 .class = &am33xx_sha0_hwmod_class,
262 .clkdm_name = "l3_clkdm",
263 .main_clk = "l3_gclk",
266 .modulemode = MODULEMODE_SWCTRL,
272 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
276 struct omap_hwmod am33xx_ocmcram_hwmod = {
278 .class = &am33xx_ocmcram_hwmod_class,
279 .clkdm_name = "l3_clkdm",
280 .flags = HWMOD_INIT_NO_IDLE,
281 .main_clk = "l3_gclk",
284 .modulemode = MODULEMODE_SWCTRL,
289 /* 'smartreflex' class */
290 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
291 .name = "smartreflex",
295 struct omap_hwmod am33xx_smartreflex0_hwmod = {
296 .name = "smartreflex0",
297 .class = &am33xx_smartreflex_hwmod_class,
298 .clkdm_name = "l4_wkup_clkdm",
299 .main_clk = "smartreflex0_fck",
302 .modulemode = MODULEMODE_SWCTRL,
308 struct omap_hwmod am33xx_smartreflex1_hwmod = {
309 .name = "smartreflex1",
310 .class = &am33xx_smartreflex_hwmod_class,
311 .clkdm_name = "l4_wkup_clkdm",
312 .main_clk = "smartreflex1_fck",
315 .modulemode = MODULEMODE_SWCTRL,
321 * 'control' module class
323 struct omap_hwmod_class am33xx_control_hwmod_class = {
329 * cpsw/cpgmac sub system
331 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
335 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
336 SYSS_HAS_RESET_STATUS),
337 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
339 .sysc_fields = &omap_hwmod_sysc_type3,
342 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
344 .sysc = &am33xx_cpgmac_sysc,
347 struct omap_hwmod am33xx_cpgmac0_hwmod = {
349 .class = &am33xx_cpgmac0_hwmod_class,
350 .clkdm_name = "cpsw_125mhz_clkdm",
351 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
352 .main_clk = "cpsw_125mhz_gclk",
356 .modulemode = MODULEMODE_SWCTRL,
364 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
365 .name = "davinci_mdio",
368 struct omap_hwmod am33xx_mdio_hwmod = {
369 .name = "davinci_mdio",
370 .class = &am33xx_mdio_hwmod_class,
371 .clkdm_name = "cpsw_125mhz_clkdm",
372 .main_clk = "cpsw_125mhz_gclk",
378 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
383 struct omap_hwmod am33xx_dcan0_hwmod = {
385 .class = &am33xx_dcan_hwmod_class,
386 .clkdm_name = "l4ls_clkdm",
387 .main_clk = "dcan0_fck",
390 .modulemode = MODULEMODE_SWCTRL,
396 struct omap_hwmod am33xx_dcan1_hwmod = {
398 .class = &am33xx_dcan_hwmod_class,
399 .clkdm_name = "l4ls_clkdm",
400 .main_clk = "dcan1_fck",
403 .modulemode = MODULEMODE_SWCTRL,
409 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
413 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
414 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
415 SYSS_HAS_RESET_STATUS),
416 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
417 .sysc_fields = &omap_hwmod_sysc_type1,
420 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
422 .sysc = &am33xx_elm_sysc,
425 struct omap_hwmod am33xx_elm_hwmod = {
427 .class = &am33xx_elm_hwmod_class,
428 .clkdm_name = "l4ls_clkdm",
429 .main_clk = "l4ls_gclk",
432 .modulemode = MODULEMODE_SWCTRL,
438 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
441 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
442 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
443 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
444 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
445 .sysc_fields = &omap_hwmod_sysc_type2,
448 struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
450 .sysc = &am33xx_epwmss_sysc,
454 struct omap_hwmod am33xx_epwmss0_hwmod = {
456 .class = &am33xx_epwmss_hwmod_class,
457 .clkdm_name = "l4ls_clkdm",
458 .main_clk = "l4ls_gclk",
461 .modulemode = MODULEMODE_SWCTRL,
467 struct omap_hwmod am33xx_epwmss1_hwmod = {
469 .class = &am33xx_epwmss_hwmod_class,
470 .clkdm_name = "l4ls_clkdm",
471 .main_clk = "l4ls_gclk",
474 .modulemode = MODULEMODE_SWCTRL,
480 struct omap_hwmod am33xx_epwmss2_hwmod = {
482 .class = &am33xx_epwmss_hwmod_class,
483 .clkdm_name = "l4ls_clkdm",
484 .main_clk = "l4ls_gclk",
487 .modulemode = MODULEMODE_SWCTRL,
493 * 'gpio' class: for gpio 0,1,2,3
495 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
499 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
500 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
501 SYSS_HAS_RESET_STATUS),
502 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
504 .sysc_fields = &omap_hwmod_sysc_type1,
507 struct omap_hwmod_class am33xx_gpio_hwmod_class = {
509 .sysc = &am33xx_gpio_sysc,
513 struct omap_gpio_dev_attr gpio_dev_attr = {
519 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
520 { .role = "dbclk", .clk = "gpio1_dbclk" },
523 struct omap_hwmod am33xx_gpio1_hwmod = {
525 .class = &am33xx_gpio_hwmod_class,
526 .clkdm_name = "l4ls_clkdm",
527 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
528 .main_clk = "l4ls_gclk",
531 .modulemode = MODULEMODE_SWCTRL,
534 .opt_clks = gpio1_opt_clks,
535 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
536 .dev_attr = &gpio_dev_attr,
540 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
541 { .role = "dbclk", .clk = "gpio2_dbclk" },
544 struct omap_hwmod am33xx_gpio2_hwmod = {
546 .class = &am33xx_gpio_hwmod_class,
547 .clkdm_name = "l4ls_clkdm",
548 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
549 .main_clk = "l4ls_gclk",
552 .modulemode = MODULEMODE_SWCTRL,
555 .opt_clks = gpio2_opt_clks,
556 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
557 .dev_attr = &gpio_dev_attr,
561 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
562 { .role = "dbclk", .clk = "gpio3_dbclk" },
565 struct omap_hwmod am33xx_gpio3_hwmod = {
567 .class = &am33xx_gpio_hwmod_class,
568 .clkdm_name = "l4ls_clkdm",
569 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
570 .main_clk = "l4ls_gclk",
573 .modulemode = MODULEMODE_SWCTRL,
576 .opt_clks = gpio3_opt_clks,
577 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
578 .dev_attr = &gpio_dev_attr,
582 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
586 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
587 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
588 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
589 .sysc_fields = &omap_hwmod_sysc_type1,
592 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
597 struct omap_hwmod am33xx_gpmc_hwmod = {
599 .class = &am33xx_gpmc_hwmod_class,
600 .clkdm_name = "l3s_clkdm",
601 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
602 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
603 .main_clk = "l3s_gclk",
606 .modulemode = MODULEMODE_SWCTRL,
612 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
615 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
616 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
617 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
618 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
620 .sysc_fields = &omap_hwmod_sysc_type1,
623 static struct omap_hwmod_class i2c_class = {
625 .sysc = &am33xx_i2c_sysc,
626 .rev = OMAP_I2C_IP_VERSION_2,
627 .reset = &omap_i2c_reset,
630 static struct omap_i2c_dev_attr i2c_dev_attr = {
631 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
635 struct omap_hwmod am33xx_i2c1_hwmod = {
638 .clkdm_name = "l4_wkup_clkdm",
639 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
640 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
643 .modulemode = MODULEMODE_SWCTRL,
646 .dev_attr = &i2c_dev_attr,
650 struct omap_hwmod am33xx_i2c2_hwmod = {
653 .clkdm_name = "l4ls_clkdm",
654 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
655 .main_clk = "dpll_per_m2_div4_ck",
658 .modulemode = MODULEMODE_SWCTRL,
661 .dev_attr = &i2c_dev_attr,
665 struct omap_hwmod am33xx_i2c3_hwmod = {
668 .clkdm_name = "l4ls_clkdm",
669 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
670 .main_clk = "dpll_per_m2_div4_ck",
673 .modulemode = MODULEMODE_SWCTRL,
676 .dev_attr = &i2c_dev_attr,
681 * mailbox module allowing communication between the on-chip processors using a
682 * queued mailbox-interrupt mechanism.
684 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
687 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
689 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
690 .sysc_fields = &omap_hwmod_sysc_type2,
693 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
695 .sysc = &am33xx_mailbox_sysc,
698 struct omap_hwmod am33xx_mailbox_hwmod = {
700 .class = &am33xx_mailbox_hwmod_class,
701 .clkdm_name = "l4ls_clkdm",
702 .main_clk = "l4ls_gclk",
705 .modulemode = MODULEMODE_SWCTRL,
713 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
716 .sysc_flags = SYSC_HAS_SIDLEMODE,
717 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
718 .sysc_fields = &omap_hwmod_sysc_type3,
721 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
723 .sysc = &am33xx_mcasp_sysc,
727 struct omap_hwmod am33xx_mcasp0_hwmod = {
729 .class = &am33xx_mcasp_hwmod_class,
730 .clkdm_name = "l3s_clkdm",
731 .main_clk = "mcasp0_fck",
734 .modulemode = MODULEMODE_SWCTRL,
740 struct omap_hwmod am33xx_mcasp1_hwmod = {
742 .class = &am33xx_mcasp_hwmod_class,
743 .clkdm_name = "l3s_clkdm",
744 .main_clk = "mcasp1_fck",
747 .modulemode = MODULEMODE_SWCTRL,
753 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
757 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
758 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
759 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
760 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
761 .sysc_fields = &omap_hwmod_sysc_type1,
764 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
766 .sysc = &am33xx_mmc_sysc,
770 static struct omap_hsmmc_dev_attr am33xx_mmc0_dev_attr = {
771 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
774 struct omap_hwmod am33xx_mmc0_hwmod = {
776 .class = &am33xx_mmc_hwmod_class,
777 .clkdm_name = "l4ls_clkdm",
778 .main_clk = "mmc_clk",
781 .modulemode = MODULEMODE_SWCTRL,
784 .dev_attr = &am33xx_mmc0_dev_attr,
788 static struct omap_hsmmc_dev_attr am33xx_mmc1_dev_attr = {
789 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
792 struct omap_hwmod am33xx_mmc1_hwmod = {
794 .class = &am33xx_mmc_hwmod_class,
795 .clkdm_name = "l4ls_clkdm",
796 .main_clk = "mmc_clk",
799 .modulemode = MODULEMODE_SWCTRL,
802 .dev_attr = &am33xx_mmc1_dev_attr,
806 static struct omap_hsmmc_dev_attr am33xx_mmc2_dev_attr = {
807 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
809 struct omap_hwmod am33xx_mmc2_hwmod = {
811 .class = &am33xx_mmc_hwmod_class,
812 .clkdm_name = "l3s_clkdm",
813 .main_clk = "mmc_clk",
816 .modulemode = MODULEMODE_SWCTRL,
819 .dev_attr = &am33xx_mmc2_dev_attr,
826 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
829 .sysc_flags = SYSC_HAS_SIDLEMODE,
830 .idlemodes = (SIDLE_FORCE | SIDLE_NO |
831 SIDLE_SMART | SIDLE_SMART_WKUP),
832 .sysc_fields = &omap_hwmod_sysc_type3,
835 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
837 .sysc = &am33xx_rtc_sysc,
838 .unlock = &omap_hwmod_rtc_unlock,
839 .lock = &omap_hwmod_rtc_lock,
842 struct omap_hwmod am33xx_rtc_hwmod = {
844 .class = &am33xx_rtc_hwmod_class,
845 .clkdm_name = "l4_rtc_clkdm",
846 .main_clk = "clk_32768_ck",
849 .modulemode = MODULEMODE_SWCTRL,
855 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
859 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
860 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
861 SYSS_HAS_RESET_STATUS),
862 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
863 .sysc_fields = &omap_hwmod_sysc_type1,
866 struct omap_hwmod_class am33xx_spi_hwmod_class = {
868 .sysc = &am33xx_mcspi_sysc,
869 .rev = OMAP4_MCSPI_REV,
873 struct omap2_mcspi_dev_attr mcspi_attrib = {
876 struct omap_hwmod am33xx_spi0_hwmod = {
878 .class = &am33xx_spi_hwmod_class,
879 .clkdm_name = "l4ls_clkdm",
880 .main_clk = "dpll_per_m2_div4_ck",
883 .modulemode = MODULEMODE_SWCTRL,
886 .dev_attr = &mcspi_attrib,
890 struct omap_hwmod am33xx_spi1_hwmod = {
892 .class = &am33xx_spi_hwmod_class,
893 .clkdm_name = "l4ls_clkdm",
894 .main_clk = "dpll_per_m2_div4_ck",
897 .modulemode = MODULEMODE_SWCTRL,
900 .dev_attr = &mcspi_attrib,
905 * spinlock provides hardware assistance for synchronizing the
906 * processes running on multiple processors
909 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
913 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
914 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
915 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
916 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
917 .sysc_fields = &omap_hwmod_sysc_type1,
920 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
922 .sysc = &am33xx_spinlock_sysc,
925 struct omap_hwmod am33xx_spinlock_hwmod = {
927 .class = &am33xx_spinlock_hwmod_class,
928 .clkdm_name = "l4ls_clkdm",
929 .main_clk = "l4ls_gclk",
932 .modulemode = MODULEMODE_SWCTRL,
937 /* 'timer 2-7' class */
938 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
942 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
943 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
945 .sysc_fields = &omap_hwmod_sysc_type2,
948 struct omap_hwmod_class am33xx_timer_hwmod_class = {
950 .sysc = &am33xx_timer_sysc,
954 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
958 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
959 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
960 SYSS_HAS_RESET_STATUS),
961 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
962 .sysc_fields = &omap_hwmod_sysc_type1,
965 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
967 .sysc = &am33xx_timer1ms_sysc,
970 struct omap_hwmod am33xx_timer1_hwmod = {
972 .class = &am33xx_timer1ms_hwmod_class,
973 .clkdm_name = "l4_wkup_clkdm",
974 .main_clk = "timer1_fck",
977 .modulemode = MODULEMODE_SWCTRL,
982 struct omap_hwmod am33xx_timer2_hwmod = {
984 .class = &am33xx_timer_hwmod_class,
985 .clkdm_name = "l4ls_clkdm",
986 .main_clk = "timer2_fck",
989 .modulemode = MODULEMODE_SWCTRL,
994 struct omap_hwmod am33xx_timer3_hwmod = {
996 .class = &am33xx_timer_hwmod_class,
997 .clkdm_name = "l4ls_clkdm",
998 .main_clk = "timer3_fck",
1001 .modulemode = MODULEMODE_SWCTRL,
1006 struct omap_hwmod am33xx_timer4_hwmod = {
1008 .class = &am33xx_timer_hwmod_class,
1009 .clkdm_name = "l4ls_clkdm",
1010 .main_clk = "timer4_fck",
1013 .modulemode = MODULEMODE_SWCTRL,
1018 struct omap_hwmod am33xx_timer5_hwmod = {
1020 .class = &am33xx_timer_hwmod_class,
1021 .clkdm_name = "l4ls_clkdm",
1022 .main_clk = "timer5_fck",
1025 .modulemode = MODULEMODE_SWCTRL,
1030 struct omap_hwmod am33xx_timer6_hwmod = {
1032 .class = &am33xx_timer_hwmod_class,
1033 .clkdm_name = "l4ls_clkdm",
1034 .main_clk = "timer6_fck",
1037 .modulemode = MODULEMODE_SWCTRL,
1042 struct omap_hwmod am33xx_timer7_hwmod = {
1044 .class = &am33xx_timer_hwmod_class,
1045 .clkdm_name = "l4ls_clkdm",
1046 .main_clk = "timer7_fck",
1049 .modulemode = MODULEMODE_SWCTRL,
1055 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1059 struct omap_hwmod am33xx_tpcc_hwmod = {
1061 .class = &am33xx_tpcc_hwmod_class,
1062 .clkdm_name = "l3_clkdm",
1063 .main_clk = "l3_gclk",
1066 .modulemode = MODULEMODE_SWCTRL,
1071 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1074 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1075 SYSC_HAS_MIDLEMODE),
1076 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1077 .sysc_fields = &omap_hwmod_sysc_type2,
1081 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1083 .sysc = &am33xx_tptc_sysc,
1087 struct omap_hwmod am33xx_tptc0_hwmod = {
1089 .class = &am33xx_tptc_hwmod_class,
1090 .clkdm_name = "l3_clkdm",
1091 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1092 .main_clk = "l3_gclk",
1095 .modulemode = MODULEMODE_SWCTRL,
1101 struct omap_hwmod am33xx_tptc1_hwmod = {
1103 .class = &am33xx_tptc_hwmod_class,
1104 .clkdm_name = "l3_clkdm",
1105 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1106 .main_clk = "l3_gclk",
1109 .modulemode = MODULEMODE_SWCTRL,
1115 struct omap_hwmod am33xx_tptc2_hwmod = {
1117 .class = &am33xx_tptc_hwmod_class,
1118 .clkdm_name = "l3_clkdm",
1119 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1120 .main_clk = "l3_gclk",
1123 .modulemode = MODULEMODE_SWCTRL,
1129 static struct omap_hwmod_class_sysconfig uart_sysc = {
1133 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1134 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1135 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1137 .sysc_fields = &omap_hwmod_sysc_type1,
1140 static struct omap_hwmod_class uart_class = {
1145 struct omap_hwmod am33xx_uart1_hwmod = {
1147 .class = &uart_class,
1148 .clkdm_name = "l4_wkup_clkdm",
1149 .flags = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1150 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1153 .modulemode = MODULEMODE_SWCTRL,
1158 struct omap_hwmod am33xx_uart2_hwmod = {
1160 .class = &uart_class,
1161 .clkdm_name = "l4ls_clkdm",
1162 .flags = HWMOD_SWSUP_SIDLE_ACT,
1163 .main_clk = "dpll_per_m2_div4_ck",
1166 .modulemode = MODULEMODE_SWCTRL,
1172 struct omap_hwmod am33xx_uart3_hwmod = {
1174 .class = &uart_class,
1175 .clkdm_name = "l4ls_clkdm",
1176 .flags = HWMOD_SWSUP_SIDLE_ACT,
1177 .main_clk = "dpll_per_m2_div4_ck",
1180 .modulemode = MODULEMODE_SWCTRL,
1185 struct omap_hwmod am33xx_uart4_hwmod = {
1187 .class = &uart_class,
1188 .clkdm_name = "l4ls_clkdm",
1189 .flags = HWMOD_SWSUP_SIDLE_ACT,
1190 .main_clk = "dpll_per_m2_div4_ck",
1193 .modulemode = MODULEMODE_SWCTRL,
1198 struct omap_hwmod am33xx_uart5_hwmod = {
1200 .class = &uart_class,
1201 .clkdm_name = "l4ls_clkdm",
1202 .flags = HWMOD_SWSUP_SIDLE_ACT,
1203 .main_clk = "dpll_per_m2_div4_ck",
1206 .modulemode = MODULEMODE_SWCTRL,
1211 struct omap_hwmod am33xx_uart6_hwmod = {
1213 .class = &uart_class,
1214 .clkdm_name = "l4ls_clkdm",
1215 .flags = HWMOD_SWSUP_SIDLE_ACT,
1216 .main_clk = "dpll_per_m2_div4_ck",
1219 .modulemode = MODULEMODE_SWCTRL,
1224 /* 'wd_timer' class */
1225 static struct omap_hwmod_class_sysconfig wdt_sysc = {
1229 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1230 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1231 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1233 .sysc_fields = &omap_hwmod_sysc_type1,
1236 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
1239 .pre_shutdown = &omap2_wd_timer_disable,
1243 * XXX: device.c file uses hardcoded name for watchdog timer
1244 * driver "wd_timer2, so we are also using same name as of now...
1246 struct omap_hwmod am33xx_wd_timer1_hwmod = {
1247 .name = "wd_timer2",
1248 .class = &am33xx_wd_timer_hwmod_class,
1249 .clkdm_name = "l4_wkup_clkdm",
1250 .flags = HWMOD_SWSUP_SIDLE,
1251 .main_clk = "wdt1_fck",
1254 .modulemode = MODULEMODE_SWCTRL,
1259 static void omap_hwmod_am33xx_clkctrl(void)
1261 CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
1262 CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET);
1263 CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET);
1264 CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET);
1265 CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET);
1266 CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1267 CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1268 CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
1269 CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1270 CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1271 CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1272 CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1273 CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1274 CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1275 CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1276 CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1277 CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1278 CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1279 CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1280 CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1281 CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1282 CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1283 CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1284 CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1285 CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1286 CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1287 CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1288 CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1289 CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1290 CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1291 CLKCTRL(am33xx_smartreflex0_hwmod,
1292 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1293 CLKCTRL(am33xx_smartreflex1_hwmod,
1294 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1295 CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1296 CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1297 CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1298 CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1299 CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1300 PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
1301 CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1302 CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1303 CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1304 CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1305 CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
1306 CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1307 CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1308 CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1309 CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1310 CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1311 CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1312 CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1313 CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1314 CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1315 CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1316 CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1317 CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
1320 static void omap_hwmod_am33xx_rst(void)
1322 RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
1323 RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
1324 RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
1327 void omap_hwmod_am33xx_reg(void)
1329 omap_hwmod_am33xx_clkctrl();
1330 omap_hwmod_am33xx_rst();
1333 static void omap_hwmod_am43xx_clkctrl(void)
1335 CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET);
1336 CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET);
1337 CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET);
1338 CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET);
1339 CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET);
1340 CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1341 CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1342 CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
1343 CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1344 CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1345 CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1346 CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1347 CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1348 CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1349 CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1350 CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1351 CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1352 CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1353 CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1354 CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1355 CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1356 CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1357 CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1358 CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1359 CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1360 CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1361 CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1362 CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1363 CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1364 CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1365 CLKCTRL(am33xx_smartreflex0_hwmod,
1366 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1367 CLKCTRL(am33xx_smartreflex1_hwmod,
1368 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1369 CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1370 CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1371 CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1372 CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1373 CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1374 CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1375 CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1376 CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1377 CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1378 CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
1379 CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1380 CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1381 CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1382 CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1383 CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1384 CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1385 CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1386 CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1387 CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1388 CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1389 CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1390 CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
1393 static void omap_hwmod_am43xx_rst(void)
1395 RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
1396 RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
1397 RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET);
1398 RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
1401 void omap_hwmod_am43xx_reg(void)
1403 omap_hwmod_am43xx_clkctrl();
1404 omap_hwmod_am43xx_rst();