arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  * Note that this file is currently not in sync with autogeneration scripts.
  16  * The above note to be removed, once it is synced up.
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 #include <linux/io.h>
  24 #include <linux/platform_data/gpio-omap.h>
  25 #include <linux/power/smartreflex.h>
  26 #include <linux/i2c-omap.h>
  27
  28 #include <linux/omap-dma.h>
  29
  30 #include <linux/platform_data/spi-omap2-mcspi.h>
  31 #include <linux/platform_data/asoc-ti-mcbsp.h>
  32 #include <linux/platform_data/iommu-omap.h>
  33 #include <plat/dmtimer.h>
  34
  35 #include "omap_hwmod.h"
  36 #include "omap_hwmod_common_data.h"
  37 #include "cm1_44xx.h"
  38 #include "cm2_44xx.h"
  39 #include "prm44xx.h"
  40 #include "prm-regbits-44xx.h"
  41 #include "i2c.h"
  42 #include "mmc.h"
  43 #include "wd_timer.h"
  44
  45 /* Base offset for all OMAP4 interrupts external to MPUSS */
  46 #define OMAP44XX_IRQ_GIC_START  32
  47
  48 /* Base offset for all OMAP4 dma requests */
  49 #define OMAP44XX_DMA_REQ_START  1
  50
  51 /*
  52  * IP blocks
  53  */
  54
  55 /*
  56  * 'dmm' class
  57  * instance(s): dmm
  58  */
  59 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  60         .name   = "dmm",
  61 };
  62
  63 /* dmm */
  64 static struct omap_hwmod omap44xx_dmm_hwmod = {
  65         .name           = "dmm",
  66         .class          = &omap44xx_dmm_hwmod_class,
  67         .clkdm_name     = "l3_emif_clkdm",
  68         .prcm = {
  69                 .omap4 = {
  70                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  71                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  72                 },
  73         },
  74 };
  75
  76 /*
  77  * 'l3' class
  78  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  79  */
  80 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
  81         .name   = "l3",
  82 };
  83
  84 /* l3_instr */
  85 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
  86         .name           = "l3_instr",
  87         .class          = &omap44xx_l3_hwmod_class,
  88         .clkdm_name     = "l3_instr_clkdm",
  89         .prcm = {
  90                 .omap4 = {
  91                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  92                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  93                         .modulemode   = MODULEMODE_HWCTRL,
  94                 },
  95         },
  96 };
  97
  98 /* l3_main_1 */
  99 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 100         .name           = "l3_main_1",
 101         .class          = &omap44xx_l3_hwmod_class,
 102         .clkdm_name     = "l3_1_clkdm",
 103         .prcm = {
 104                 .omap4 = {
 105                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 106                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 107                 },
 108         },
 109 };
 110
 111 /* l3_main_2 */
 112 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 113         .name           = "l3_main_2",
 114         .class          = &omap44xx_l3_hwmod_class,
 115         .clkdm_name     = "l3_2_clkdm",
 116         .prcm = {
 117                 .omap4 = {
 118                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 119                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 120                 },
 121         },
 122 };
 123
 124 /* l3_main_3 */
 125 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 126         .name           = "l3_main_3",
 127         .class          = &omap44xx_l3_hwmod_class,
 128         .clkdm_name     = "l3_instr_clkdm",
 129         .prcm = {
 130                 .omap4 = {
 131                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 132                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 133                         .modulemode   = MODULEMODE_HWCTRL,
 134                 },
 135         },
 136 };
 137
 138 /*
 139  * 'l4' class
 140  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 141  */
 142 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 143         .name   = "l4",
 144 };
 145
 146 /* l4_abe */
 147 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 148         .name           = "l4_abe",
 149         .class          = &omap44xx_l4_hwmod_class,
 150         .clkdm_name     = "abe_clkdm",
 151         .prcm = {
 152                 .omap4 = {
 153                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 154                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 155                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 156                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 157                 },
 158         },
 159 };
 160
 161 /* l4_cfg */
 162 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 163         .name           = "l4_cfg",
 164         .class          = &omap44xx_l4_hwmod_class,
 165         .clkdm_name     = "l4_cfg_clkdm",
 166         .prcm = {
 167                 .omap4 = {
 168                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 169                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 170                 },
 171         },
 172 };
 173
 174 /* l4_per */
 175 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 176         .name           = "l4_per",
 177         .class          = &omap44xx_l4_hwmod_class,
 178         .clkdm_name     = "l4_per_clkdm",
 179         .prcm = {
 180                 .omap4 = {
 181                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 182                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 183                 },
 184         },
 185 };
 186
 187 /* l4_wkup */
 188 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 189         .name           = "l4_wkup",
 190         .class          = &omap44xx_l4_hwmod_class,
 191         .clkdm_name     = "l4_wkup_clkdm",
 192         .prcm = {
 193                 .omap4 = {
 194                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 195                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 196                 },
 197         },
 198 };
 199
 200 /*
 201  * 'mpu_bus' class
 202  * instance(s): mpu_private
 203  */
 204 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 205         .name   = "mpu_bus",
 206 };
 207
 208 /* mpu_private */
 209 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 210         .name           = "mpu_private",
 211         .class          = &omap44xx_mpu_bus_hwmod_class,
 212         .clkdm_name     = "mpuss_clkdm",
 213         .prcm = {
 214                 .omap4 = {
 215                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 216                 },
 217         },
 218 };
 219
 220 /*
 221  * 'ocp_wp_noc' class
 222  * instance(s): ocp_wp_noc
 223  */
 224 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 225         .name   = "ocp_wp_noc",
 226 };
 227
 228 /* ocp_wp_noc */
 229 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 230         .name           = "ocp_wp_noc",
 231         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 232         .clkdm_name     = "l3_instr_clkdm",
 233         .prcm = {
 234                 .omap4 = {
 235                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 236                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 237                         .modulemode   = MODULEMODE_HWCTRL,
 238                 },
 239         },
 240 };
 241
 242 /*
 243  * Modules omap_hwmod structures
 244  *
 245  * The following IPs are excluded for the moment because:
 246  * - They do not need an explicit SW control using omap_hwmod API.
 247  * - They still need to be validated with the driver
 248  *   properly adapted to omap_hwmod / omap_device
 249  *
 250  * usim
 251  */
 252
 253 /*
 254  * 'aess' class
 255  * audio engine sub system
 256  */
 257
 258 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 259         .rev_offs       = 0x0000,
 260         .sysc_offs      = 0x0010,
 261         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 262         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 263                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 264                            MSTANDBY_SMART_WKUP),
 265         .sysc_fields    = &omap_hwmod_sysc_type2,
 266 };
 267
 268 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 269         .name   = "aess",
 270         .sysc   = &omap44xx_aess_sysc,
 271         .enable_preprogram = omap_hwmod_aess_preprogram,
 272 };
 273
 274 /* aess */
 275 static struct omap_hwmod omap44xx_aess_hwmod = {
 276         .name           = "aess",
 277         .class          = &omap44xx_aess_hwmod_class,
 278         .clkdm_name     = "abe_clkdm",
 279         .main_clk       = "aess_fclk",
 280         .prcm = {
 281                 .omap4 = {
 282                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 283                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 284                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 285                         .modulemode   = MODULEMODE_SWCTRL,
 286                 },
 287         },
 288 };
 289
 290 /*
 291  * 'c2c' class
 292  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 293  * soc
 294  */
 295
 296 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 297         .name   = "c2c",
 298 };
 299
 300 /* c2c */
 301 static struct omap_hwmod omap44xx_c2c_hwmod = {
 302         .name           = "c2c",
 303         .class          = &omap44xx_c2c_hwmod_class,
 304         .clkdm_name     = "d2d_clkdm",
 305         .prcm = {
 306                 .omap4 = {
 307                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 308                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 309                 },
 310         },
 311 };
 312
 313 /*
 314  * 'counter' class
 315  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 316  */
 317
 318 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 319         .rev_offs       = 0x0000,
 320         .sysc_offs      = 0x0004,
 321         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 322         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 323         .sysc_fields    = &omap_hwmod_sysc_type1,
 324 };
 325
 326 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 327         .name   = "counter",
 328         .sysc   = &omap44xx_counter_sysc,
 329 };
 330
 331 /* counter_32k */
 332 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 333         .name           = "counter_32k",
 334         .class          = &omap44xx_counter_hwmod_class,
 335         .clkdm_name     = "l4_wkup_clkdm",
 336         .flags          = HWMOD_SWSUP_SIDLE,
 337         .main_clk       = "sys_32k_ck",
 338         .prcm = {
 339                 .omap4 = {
 340                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 341                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 342                 },
 343         },
 344 };
 345
 346 /*
 347  * 'ctrl_module' class
 348  * attila core control module + core pad control module + wkup pad control
 349  * module + attila wkup control module
 350  */
 351
 352 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 353         .rev_offs       = 0x0000,
 354         .sysc_offs      = 0x0010,
 355         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 356         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 357                            SIDLE_SMART_WKUP),
 358         .sysc_fields    = &omap_hwmod_sysc_type2,
 359 };
 360
 361 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 362         .name   = "ctrl_module",
 363         .sysc   = &omap44xx_ctrl_module_sysc,
 364 };
 365
 366 /* ctrl_module_core */
 367 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 368         .name           = "ctrl_module_core",
 369         .class          = &omap44xx_ctrl_module_hwmod_class,
 370         .clkdm_name     = "l4_cfg_clkdm",
 371         .prcm = {
 372                 .omap4 = {
 373                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 374                 },
 375         },
 376 };
 377
 378 /* ctrl_module_pad_core */
 379 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 380         .name           = "ctrl_module_pad_core",
 381         .class          = &omap44xx_ctrl_module_hwmod_class,
 382         .clkdm_name     = "l4_cfg_clkdm",
 383         .prcm = {
 384                 .omap4 = {
 385                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 386                 },
 387         },
 388 };
 389
 390 /* ctrl_module_wkup */
 391 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 392         .name           = "ctrl_module_wkup",
 393         .class          = &omap44xx_ctrl_module_hwmod_class,
 394         .clkdm_name     = "l4_wkup_clkdm",
 395         .prcm = {
 396                 .omap4 = {
 397                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 398                 },
 399         },
 400 };
 401
 402 /* ctrl_module_pad_wkup */
 403 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 404         .name           = "ctrl_module_pad_wkup",
 405         .class          = &omap44xx_ctrl_module_hwmod_class,
 406         .clkdm_name     = "l4_wkup_clkdm",
 407         .prcm = {
 408                 .omap4 = {
 409                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 410                 },
 411         },
 412 };
 413
 414 /*
 415  * 'debugss' class
 416  * debug and emulation sub system
 417  */
 418
 419 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 420         .name   = "debugss",
 421 };
 422
 423 /* debugss */
 424 static struct omap_hwmod omap44xx_debugss_hwmod = {
 425         .name           = "debugss",
 426         .class          = &omap44xx_debugss_hwmod_class,
 427         .clkdm_name     = "emu_sys_clkdm",
 428         .main_clk       = "trace_clk_div_ck",
 429         .prcm = {
 430                 .omap4 = {
 431                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 432                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 433                 },
 434         },
 435 };
 436
 437 /*
 438  * 'dma' class
 439  * dma controller for data exchange between memory to memory (i.e. internal or
 440  * external memory) and gp peripherals to memory or memory to gp peripherals
 441  */
 442
 443 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 444         .rev_offs       = 0x0000,
 445         .sysc_offs      = 0x002c,
 446         .syss_offs      = 0x0028,
 447         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 448                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 449                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 450                            SYSS_HAS_RESET_STATUS),
 451         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 452                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 453         .sysc_fields    = &omap_hwmod_sysc_type1,
 454 };
 455
 456 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 457         .name   = "dma",
 458         .sysc   = &omap44xx_dma_sysc,
 459 };
 460
 461 /* dma dev_attr */
 462 static struct omap_dma_dev_attr dma_dev_attr = {
 463         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 464                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 465         .lch_count      = 32,
 466 };
 467
 468 /* dma_system */
 469 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 470         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 471         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 472         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 473         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 474         { .irq = -1 }
 475 };
 476
 477 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 478         .name           = "dma_system",
 479         .class          = &omap44xx_dma_hwmod_class,
 480         .clkdm_name     = "l3_dma_clkdm",
 481         .mpu_irqs       = omap44xx_dma_system_irqs,
 482         .main_clk       = "l3_div_ck",
 483         .prcm = {
 484                 .omap4 = {
 485                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 486                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 487                 },
 488         },
 489         .dev_attr       = &dma_dev_attr,
 490 };
 491
 492 /*
 493  * 'dmic' class
 494  * digital microphone controller
 495  */
 496
 497 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 498         .rev_offs       = 0x0000,
 499         .sysc_offs      = 0x0010,
 500         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 501                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 502         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 503                            SIDLE_SMART_WKUP),
 504         .sysc_fields    = &omap_hwmod_sysc_type2,
 505 };
 506
 507 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 508         .name   = "dmic",
 509         .sysc   = &omap44xx_dmic_sysc,
 510 };
 511
 512 /* dmic */
 513 static struct omap_hwmod omap44xx_dmic_hwmod = {
 514         .name           = "dmic",
 515         .class          = &omap44xx_dmic_hwmod_class,
 516         .clkdm_name     = "abe_clkdm",
 517         .main_clk       = "func_dmic_abe_gfclk",
 518         .prcm = {
 519                 .omap4 = {
 520                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 521                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 522                         .modulemode   = MODULEMODE_SWCTRL,
 523                 },
 524         },
 525 };
 526
 527 /*
 528  * 'dsp' class
 529  * dsp sub-system
 530  */
 531
 532 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 533         .name   = "dsp",
 534 };
 535
 536 /* dsp */
 537 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 538         { .name = "dsp", .rst_shift = 0 },
 539 };
 540
 541 static struct omap_hwmod omap44xx_dsp_hwmod = {
 542         .name           = "dsp",
 543         .class          = &omap44xx_dsp_hwmod_class,
 544         .clkdm_name     = "tesla_clkdm",
 545         .rst_lines      = omap44xx_dsp_resets,
 546         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 547         .main_clk       = "dpll_iva_m4x2_ck",
 548         .prcm = {
 549                 .omap4 = {
 550                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 551                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 552                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 553                         .modulemode   = MODULEMODE_HWCTRL,
 554                 },
 555         },
 556 };
 557
 558 /*
 559  * 'dss' class
 560  * display sub-system
 561  */
 562
 563 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 564         .rev_offs       = 0x0000,
 565         .syss_offs      = 0x0014,
 566         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 567 };
 568
 569 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 570         .name   = "dss",
 571         .sysc   = &omap44xx_dss_sysc,
 572         .reset  = omap_dss_reset,
 573 };
 574
 575 /* dss */
 576 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 577         { .role = "sys_clk", .clk = "dss_sys_clk" },
 578         { .role = "tv_clk", .clk = "dss_tv_clk" },
 579         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 580 };
 581
 582 static struct omap_hwmod omap44xx_dss_hwmod = {
 583         .name           = "dss_core",
 584         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 585         .class          = &omap44xx_dss_hwmod_class,
 586         .clkdm_name     = "l3_dss_clkdm",
 587         .main_clk       = "dss_dss_clk",
 588         .prcm = {
 589                 .omap4 = {
 590                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 591                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 592                 },
 593         },
 594         .opt_clks       = dss_opt_clks,
 595         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 596 };
 597
 598 /*
 599  * 'dispc' class
 600  * display controller
 601  */
 602
 603 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 604         .rev_offs       = 0x0000,
 605         .sysc_offs      = 0x0010,
 606         .syss_offs      = 0x0014,
 607         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 608                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 609                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 610                            SYSS_HAS_RESET_STATUS),
 611         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 612                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 613         .sysc_fields    = &omap_hwmod_sysc_type1,
 614 };
 615
 616 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 617         .name   = "dispc",
 618         .sysc   = &omap44xx_dispc_sysc,
 619 };
 620
 621 /* dss_dispc */
 622 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 623         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 624         { .irq = -1 }
 625 };
 626
 627 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 628         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 629         { .dma_req = -1 }
 630 };
 631
 632 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 633         .manager_count          = 3,
 634         .has_framedonetv_irq    = 1
 635 };
 636
 637 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 638         .name           = "dss_dispc",
 639         .class          = &omap44xx_dispc_hwmod_class,
 640         .clkdm_name     = "l3_dss_clkdm",
 641         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 642         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 643         .main_clk       = "dss_dss_clk",
 644         .prcm = {
 645                 .omap4 = {
 646                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 647                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 648                 },
 649         },
 650         .dev_attr       = &omap44xx_dss_dispc_dev_attr,
 651         .parent_hwmod   = &omap44xx_dss_hwmod,
 652 };
 653
 654 /*
 655  * 'dsi' class
 656  * display serial interface controller
 657  */
 658
 659 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 660         .rev_offs       = 0x0000,
 661         .sysc_offs      = 0x0010,
 662         .syss_offs      = 0x0014,
 663         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 664                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 665                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 666         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 667         .sysc_fields    = &omap_hwmod_sysc_type1,
 668 };
 669
 670 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 671         .name   = "dsi",
 672         .sysc   = &omap44xx_dsi_sysc,
 673 };
 674
 675 /* dss_dsi1 */
 676 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 677         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 678         { .irq = -1 }
 679 };
 680
 681 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 682         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 683         { .dma_req = -1 }
 684 };
 685
 686 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 687         { .role = "sys_clk", .clk = "dss_sys_clk" },
 688 };
 689
 690 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 691         .name           = "dss_dsi1",
 692         .class          = &omap44xx_dsi_hwmod_class,
 693         .clkdm_name     = "l3_dss_clkdm",
 694         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 695         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 696         .main_clk       = "dss_dss_clk",
 697         .prcm = {
 698                 .omap4 = {
 699                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 700                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 701                 },
 702         },
 703         .opt_clks       = dss_dsi1_opt_clks,
 704         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 705         .parent_hwmod   = &omap44xx_dss_hwmod,
 706 };
 707
 708 /* dss_dsi2 */
 709 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 710         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 711         { .irq = -1 }
 712 };
 713
 714 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 715         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 716         { .dma_req = -1 }
 717 };
 718
 719 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 720         { .role = "sys_clk", .clk = "dss_sys_clk" },
 721 };
 722
 723 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 724         .name           = "dss_dsi2",
 725         .class          = &omap44xx_dsi_hwmod_class,
 726         .clkdm_name     = "l3_dss_clkdm",
 727         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 728         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 729         .main_clk       = "dss_dss_clk",
 730         .prcm = {
 731                 .omap4 = {
 732                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 733                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 734                 },
 735         },
 736         .opt_clks       = dss_dsi2_opt_clks,
 737         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 738         .parent_hwmod   = &omap44xx_dss_hwmod,
 739 };
 740
 741 /*
 742  * 'hdmi' class
 743  * hdmi controller
 744  */
 745
 746 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 747         .rev_offs       = 0x0000,
 748         .sysc_offs      = 0x0010,
 749         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 750                            SYSC_HAS_SOFTRESET),
 751         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 752                            SIDLE_SMART_WKUP),
 753         .sysc_fields    = &omap_hwmod_sysc_type2,
 754 };
 755
 756 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 757         .name   = "hdmi",
 758         .sysc   = &omap44xx_hdmi_sysc,
 759 };
 760
 761 /* dss_hdmi */
 762 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 763         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 764         { .irq = -1 }
 765 };
 766
 767 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 768         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 769         { .dma_req = -1 }
 770 };
 771
 772 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 773         { .role = "sys_clk", .clk = "dss_sys_clk" },
 774 };
 775
 776 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 777         .name           = "dss_hdmi",
 778         .class          = &omap44xx_hdmi_hwmod_class,
 779         .clkdm_name     = "l3_dss_clkdm",
 780         /*
 781          * HDMI audio requires to use no-idle mode. Hence,
 782          * set idle mode by software.
 783          */
 784         .flags          = HWMOD_SWSUP_SIDLE,
 785         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 786         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 787         .main_clk       = "dss_48mhz_clk",
 788         .prcm = {
 789                 .omap4 = {
 790                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 791                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 792                 },
 793         },
 794         .opt_clks       = dss_hdmi_opt_clks,
 795         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 796         .parent_hwmod   = &omap44xx_dss_hwmod,
 797 };
 798
 799 /*
 800  * 'rfbi' class
 801  * remote frame buffer interface
 802  */
 803
 804 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 805         .rev_offs       = 0x0000,
 806         .sysc_offs      = 0x0010,
 807         .syss_offs      = 0x0014,
 808         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 809                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 810         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 811         .sysc_fields    = &omap_hwmod_sysc_type1,
 812 };
 813
 814 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 815         .name   = "rfbi",
 816         .sysc   = &omap44xx_rfbi_sysc,
 817 };
 818
 819 /* dss_rfbi */
 820 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 821         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 822         { .dma_req = -1 }
 823 };
 824
 825 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 826         { .role = "ick", .clk = "dss_fck" },
 827 };
 828
 829 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 830         .name           = "dss_rfbi",
 831         .class          = &omap44xx_rfbi_hwmod_class,
 832         .clkdm_name     = "l3_dss_clkdm",
 833         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 834         .main_clk       = "dss_dss_clk",
 835         .prcm = {
 836                 .omap4 = {
 837                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 838                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 839                 },
 840         },
 841         .opt_clks       = dss_rfbi_opt_clks,
 842         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 843         .parent_hwmod   = &omap44xx_dss_hwmod,
 844 };
 845
 846 /*
 847  * 'venc' class
 848  * video encoder
 849  */
 850
 851 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 852         .name   = "venc",
 853 };
 854
 855 /* dss_venc */
 856 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 857         .name           = "dss_venc",
 858         .class          = &omap44xx_venc_hwmod_class,
 859         .clkdm_name     = "l3_dss_clkdm",
 860         .main_clk       = "dss_tv_clk",
 861         .prcm = {
 862                 .omap4 = {
 863                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 864                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 865                 },
 866         },
 867         .parent_hwmod   = &omap44xx_dss_hwmod,
 868 };
 869
 870 /*
 871  * 'elm' class
 872  * bch error location module
 873  */
 874
 875 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 876         .rev_offs       = 0x0000,
 877         .sysc_offs      = 0x0010,
 878         .syss_offs      = 0x0014,
 879         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 880                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 881                            SYSS_HAS_RESET_STATUS),
 882         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 883         .sysc_fields    = &omap_hwmod_sysc_type1,
 884 };
 885
 886 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 887         .name   = "elm",
 888         .sysc   = &omap44xx_elm_sysc,
 889 };
 890
 891 /* elm */
 892 static struct omap_hwmod omap44xx_elm_hwmod = {
 893         .name           = "elm",
 894         .class          = &omap44xx_elm_hwmod_class,
 895         .clkdm_name     = "l4_per_clkdm",
 896         .prcm = {
 897                 .omap4 = {
 898                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
 899                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
 900                 },
 901         },
 902 };
 903
 904 /*
 905  * 'emif' class
 906  * external memory interface no1
 907  */
 908
 909 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 910         .rev_offs       = 0x0000,
 911 };
 912
 913 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 914         .name   = "emif",
 915         .sysc   = &omap44xx_emif_sysc,
 916 };
 917
 918 /* emif1 */
 919 static struct omap_hwmod omap44xx_emif1_hwmod = {
 920         .name           = "emif1",
 921         .class          = &omap44xx_emif_hwmod_class,
 922         .clkdm_name     = "l3_emif_clkdm",
 923         .flags          = HWMOD_INIT_NO_IDLE,
 924         .main_clk       = "ddrphy_ck",
 925         .prcm = {
 926                 .omap4 = {
 927                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
 928                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
 929                         .modulemode   = MODULEMODE_HWCTRL,
 930                 },
 931         },
 932 };
 933
 934 /* emif2 */
 935 static struct omap_hwmod omap44xx_emif2_hwmod = {
 936         .name           = "emif2",
 937         .class          = &omap44xx_emif_hwmod_class,
 938         .clkdm_name     = "l3_emif_clkdm",
 939         .flags          = HWMOD_INIT_NO_IDLE,
 940         .main_clk       = "ddrphy_ck",
 941         .prcm = {
 942                 .omap4 = {
 943                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
 944                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
 945                         .modulemode   = MODULEMODE_HWCTRL,
 946                 },
 947         },
 948 };
 949
 950 /*
 951  * 'fdif' class
 952  * face detection hw accelerator module
 953  */
 954
 955 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
 956         .rev_offs       = 0x0000,
 957         .sysc_offs      = 0x0010,
 958         /*
 959          * FDIF needs 100 OCP clk cycles delay after a softreset before
 960          * accessing sysconfig again.
 961          * The lowest frequency at the moment for L3 bus is 100 MHz, so
 962          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
 963          *
 964          * TODO: Indicate errata when available.
 965          */
 966         .srst_udelay    = 2,
 967         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
 968                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 969         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 970                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 971         .sysc_fields    = &omap_hwmod_sysc_type2,
 972 };
 973
 974 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
 975         .name   = "fdif",
 976         .sysc   = &omap44xx_fdif_sysc,
 977 };
 978
 979 /* fdif */
 980 static struct omap_hwmod omap44xx_fdif_hwmod = {
 981         .name           = "fdif",
 982         .class          = &omap44xx_fdif_hwmod_class,
 983         .clkdm_name     = "iss_clkdm",
 984         .main_clk       = "fdif_fck",
 985         .prcm = {
 986                 .omap4 = {
 987                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
 988                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
 989                         .modulemode   = MODULEMODE_SWCTRL,
 990                 },
 991         },
 992 };
 993
 994 /*
 995  * 'gpio' class
 996  * general purpose io module
 997  */
 998
 999 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1000         .rev_offs       = 0x0000,
1001         .sysc_offs      = 0x0010,
1002         .syss_offs      = 0x0114,
1003         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1004                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1005                            SYSS_HAS_RESET_STATUS),
1006         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1007                            SIDLE_SMART_WKUP),
1008         .sysc_fields    = &omap_hwmod_sysc_type1,
1009 };
1010
1011 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1012         .name   = "gpio",
1013         .sysc   = &omap44xx_gpio_sysc,
1014         .rev    = 2,
1015 };
1016
1017 /* gpio dev_attr */
1018 static struct omap_gpio_dev_attr gpio_dev_attr = {
1019         .bank_width     = 32,
1020         .dbck_flag      = true,
1021 };
1022
1023 /* gpio1 */
1024 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1025         { .role = "dbclk", .clk = "gpio1_dbclk" },
1026 };
1027
1028 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1029         .name           = "gpio1",
1030         .class          = &omap44xx_gpio_hwmod_class,
1031         .clkdm_name     = "l4_wkup_clkdm",
1032         .main_clk       = "l4_wkup_clk_mux_ck",
1033         .prcm = {
1034                 .omap4 = {
1035                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1036                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1037                         .modulemode   = MODULEMODE_HWCTRL,
1038                 },
1039         },
1040         .opt_clks       = gpio1_opt_clks,
1041         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1042         .dev_attr       = &gpio_dev_attr,
1043 };
1044
1045 /* gpio2 */
1046 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1047         { .role = "dbclk", .clk = "gpio2_dbclk" },
1048 };
1049
1050 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1051         .name           = "gpio2",
1052         .class          = &omap44xx_gpio_hwmod_class,
1053         .clkdm_name     = "l4_per_clkdm",
1054         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1055         .main_clk       = "l4_div_ck",
1056         .prcm = {
1057                 .omap4 = {
1058                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1059                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1060                         .modulemode   = MODULEMODE_HWCTRL,
1061                 },
1062         },
1063         .opt_clks       = gpio2_opt_clks,
1064         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1065         .dev_attr       = &gpio_dev_attr,
1066 };
1067
1068 /* gpio3 */
1069 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1070         { .role = "dbclk", .clk = "gpio3_dbclk" },
1071 };
1072
1073 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1074         .name           = "gpio3",
1075         .class          = &omap44xx_gpio_hwmod_class,
1076         .clkdm_name     = "l4_per_clkdm",
1077         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1078         .main_clk       = "l4_div_ck",
1079         .prcm = {
1080                 .omap4 = {
1081                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1082                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1083                         .modulemode   = MODULEMODE_HWCTRL,
1084                 },
1085         },
1086         .opt_clks       = gpio3_opt_clks,
1087         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1088         .dev_attr       = &gpio_dev_attr,
1089 };
1090
1091 /* gpio4 */
1092 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1093         { .role = "dbclk", .clk = "gpio4_dbclk" },
1094 };
1095
1096 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1097         .name           = "gpio4",
1098         .class          = &omap44xx_gpio_hwmod_class,
1099         .clkdm_name     = "l4_per_clkdm",
1100         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1101         .main_clk       = "l4_div_ck",
1102         .prcm = {
1103                 .omap4 = {
1104                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1105                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1106                         .modulemode   = MODULEMODE_HWCTRL,
1107                 },
1108         },
1109         .opt_clks       = gpio4_opt_clks,
1110         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1111         .dev_attr       = &gpio_dev_attr,
1112 };
1113
1114 /* gpio5 */
1115 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1116         { .role = "dbclk", .clk = "gpio5_dbclk" },
1117 };
1118
1119 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1120         .name           = "gpio5",
1121         .class          = &omap44xx_gpio_hwmod_class,
1122         .clkdm_name     = "l4_per_clkdm",
1123         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1124         .main_clk       = "l4_div_ck",
1125         .prcm = {
1126                 .omap4 = {
1127                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1128                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1129                         .modulemode   = MODULEMODE_HWCTRL,
1130                 },
1131         },
1132         .opt_clks       = gpio5_opt_clks,
1133         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1134         .dev_attr       = &gpio_dev_attr,
1135 };
1136
1137 /* gpio6 */
1138 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1139         { .role = "dbclk", .clk = "gpio6_dbclk" },
1140 };
1141
1142 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1143         .name           = "gpio6",
1144         .class          = &omap44xx_gpio_hwmod_class,
1145         .clkdm_name     = "l4_per_clkdm",
1146         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1147         .main_clk       = "l4_div_ck",
1148         .prcm = {
1149                 .omap4 = {
1150                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1151                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1152                         .modulemode   = MODULEMODE_HWCTRL,
1153                 },
1154         },
1155         .opt_clks       = gpio6_opt_clks,
1156         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1157         .dev_attr       = &gpio_dev_attr,
1158 };
1159
1160 /*
1161  * 'gpmc' class
1162  * general purpose memory controller
1163  */
1164
1165 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1166         .rev_offs       = 0x0000,
1167         .sysc_offs      = 0x0010,
1168         .syss_offs      = 0x0014,
1169         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1170                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1171         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1172         .sysc_fields    = &omap_hwmod_sysc_type1,
1173 };
1174
1175 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1176         .name   = "gpmc",
1177         .sysc   = &omap44xx_gpmc_sysc,
1178 };
1179
1180 /* gpmc */
1181 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1182         .name           = "gpmc",
1183         .class          = &omap44xx_gpmc_hwmod_class,
1184         .clkdm_name     = "l3_2_clkdm",
1185         /*
1186          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1187          * block.  It is not being added due to any known bugs with
1188          * resetting the GPMC IP block, but rather because any timings
1189          * set by the bootloader are not being correctly programmed by
1190          * the kernel from the board file or DT data.
1191          * HWMOD_INIT_NO_RESET should be removed ASAP.
1192          */
1193         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1194         .prcm = {
1195                 .omap4 = {
1196                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1197                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1198                         .modulemode   = MODULEMODE_HWCTRL,
1199                 },
1200         },
1201 };
1202
1203 /*
1204  * 'gpu' class
1205  * 2d/3d graphics accelerator
1206  */
1207
1208 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1209         .rev_offs       = 0x1fc00,
1210         .sysc_offs      = 0x1fc10,
1211         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1212         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1213                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1214                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1215         .sysc_fields    = &omap_hwmod_sysc_type2,
1216 };
1217
1218 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1219         .name   = "gpu",
1220         .sysc   = &omap44xx_gpu_sysc,
1221 };
1222
1223 /* gpu */
1224 static struct omap_hwmod omap44xx_gpu_hwmod = {
1225         .name           = "gpu",
1226         .class          = &omap44xx_gpu_hwmod_class,
1227         .clkdm_name     = "l3_gfx_clkdm",
1228         .main_clk       = "sgx_clk_mux",
1229         .prcm = {
1230                 .omap4 = {
1231                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1232                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1233                         .modulemode   = MODULEMODE_SWCTRL,
1234                 },
1235         },
1236 };
1237
1238 /*
1239  * 'hdq1w' class
1240  * hdq / 1-wire serial interface controller
1241  */
1242
1243 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1244         .rev_offs       = 0x0000,
1245         .sysc_offs      = 0x0014,
1246         .syss_offs      = 0x0018,
1247         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1248                            SYSS_HAS_RESET_STATUS),
1249         .sysc_fields    = &omap_hwmod_sysc_type1,
1250 };
1251
1252 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1253         .name   = "hdq1w",
1254         .sysc   = &omap44xx_hdq1w_sysc,
1255 };
1256
1257 /* hdq1w */
1258 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1259         .name           = "hdq1w",
1260         .class          = &omap44xx_hdq1w_hwmod_class,
1261         .clkdm_name     = "l4_per_clkdm",
1262         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1263         .main_clk       = "func_12m_fclk",
1264         .prcm = {
1265                 .omap4 = {
1266                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1267                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1268                         .modulemode   = MODULEMODE_SWCTRL,
1269                 },
1270         },
1271 };
1272
1273 /*
1274  * 'hsi' class
1275  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1276  * serial if)
1277  */
1278
1279 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1280         .rev_offs       = 0x0000,
1281         .sysc_offs      = 0x0010,
1282         .syss_offs      = 0x0014,
1283         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1284                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1285                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1286         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1287                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1288                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1289         .sysc_fields    = &omap_hwmod_sysc_type1,
1290 };
1291
1292 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1293         .name   = "hsi",
1294         .sysc   = &omap44xx_hsi_sysc,
1295 };
1296
1297 /* hsi */
1298 static struct omap_hwmod omap44xx_hsi_hwmod = {
1299         .name           = "hsi",
1300         .class          = &omap44xx_hsi_hwmod_class,
1301         .clkdm_name     = "l3_init_clkdm",
1302         .main_clk       = "hsi_fck",
1303         .prcm = {
1304                 .omap4 = {
1305                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1306                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1307                         .modulemode   = MODULEMODE_HWCTRL,
1308                 },
1309         },
1310 };
1311
1312 /*
1313  * 'i2c' class
1314  * multimaster high-speed i2c controller
1315  */
1316
1317 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1318         .sysc_offs      = 0x0010,
1319         .syss_offs      = 0x0090,
1320         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1321                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1322                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1323         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1324                            SIDLE_SMART_WKUP),
1325         .clockact       = CLOCKACT_TEST_ICLK,
1326         .sysc_fields    = &omap_hwmod_sysc_type1,
1327 };
1328
1329 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1330         .name   = "i2c",
1331         .sysc   = &omap44xx_i2c_sysc,
1332         .rev    = OMAP_I2C_IP_VERSION_2,
1333         .reset  = &omap_i2c_reset,
1334 };
1335
1336 static struct omap_i2c_dev_attr i2c_dev_attr = {
1337         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1338 };
1339
1340 /* i2c1 */
1341 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1342         .name           = "i2c1",
1343         .class          = &omap44xx_i2c_hwmod_class,
1344         .clkdm_name     = "l4_per_clkdm",
1345         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1346         .main_clk       = "func_96m_fclk",
1347         .prcm = {
1348                 .omap4 = {
1349                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1350                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1351                         .modulemode   = MODULEMODE_SWCTRL,
1352                 },
1353         },
1354         .dev_attr       = &i2c_dev_attr,
1355 };
1356
1357 /* i2c2 */
1358 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1359         .name           = "i2c2",
1360         .class          = &omap44xx_i2c_hwmod_class,
1361         .clkdm_name     = "l4_per_clkdm",
1362         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1363         .main_clk       = "func_96m_fclk",
1364         .prcm = {
1365                 .omap4 = {
1366                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1367                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1368                         .modulemode   = MODULEMODE_SWCTRL,
1369                 },
1370         },
1371         .dev_attr       = &i2c_dev_attr,
1372 };
1373
1374 /* i2c3 */
1375 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1376         .name           = "i2c3",
1377         .class          = &omap44xx_i2c_hwmod_class,
1378         .clkdm_name     = "l4_per_clkdm",
1379         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1380         .main_clk       = "func_96m_fclk",
1381         .prcm = {
1382                 .omap4 = {
1383                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1384                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1385                         .modulemode   = MODULEMODE_SWCTRL,
1386                 },
1387         },
1388         .dev_attr       = &i2c_dev_attr,
1389 };
1390
1391 /* i2c4 */
1392 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1393         .name           = "i2c4",
1394         .class          = &omap44xx_i2c_hwmod_class,
1395         .clkdm_name     = "l4_per_clkdm",
1396         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1397         .main_clk       = "func_96m_fclk",
1398         .prcm = {
1399                 .omap4 = {
1400                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1401                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1402                         .modulemode   = MODULEMODE_SWCTRL,
1403                 },
1404         },
1405         .dev_attr       = &i2c_dev_attr,
1406 };
1407
1408 /*
1409  * 'ipu' class
1410  * imaging processor unit
1411  */
1412
1413 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1414         .name   = "ipu",
1415 };
1416
1417 /* ipu */
1418 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1419         { .name = "cpu0", .rst_shift = 0 },
1420         { .name = "cpu1", .rst_shift = 1 },
1421 };
1422
1423 static struct omap_hwmod omap44xx_ipu_hwmod = {
1424         .name           = "ipu",
1425         .class          = &omap44xx_ipu_hwmod_class,
1426         .clkdm_name     = "ducati_clkdm",
1427         .rst_lines      = omap44xx_ipu_resets,
1428         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1429         .main_clk       = "ducati_clk_mux_ck",
1430         .prcm = {
1431                 .omap4 = {
1432                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1433                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1434                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1435                         .modulemode   = MODULEMODE_HWCTRL,
1436                 },
1437         },
1438 };
1439
1440 /*
1441  * 'iss' class
1442  * external images sensor pixel data processor
1443  */
1444
1445 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1446         .rev_offs       = 0x0000,
1447         .sysc_offs      = 0x0010,
1448         /*
1449          * ISS needs 100 OCP clk cycles delay after a softreset before
1450          * accessing sysconfig again.
1451          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1452          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1453          *
1454          * TODO: Indicate errata when available.
1455          */
1456         .srst_udelay    = 2,
1457         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1458                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1459         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1460                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1461                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1462         .sysc_fields    = &omap_hwmod_sysc_type2,
1463 };
1464
1465 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1466         .name   = "iss",
1467         .sysc   = &omap44xx_iss_sysc,
1468 };
1469
1470 /* iss */
1471 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1472         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1473 };
1474
1475 static struct omap_hwmod omap44xx_iss_hwmod = {
1476         .name           = "iss",
1477         .class          = &omap44xx_iss_hwmod_class,
1478         .clkdm_name     = "iss_clkdm",
1479         .main_clk       = "ducati_clk_mux_ck",
1480         .prcm = {
1481                 .omap4 = {
1482                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1483                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1484                         .modulemode   = MODULEMODE_SWCTRL,
1485                 },
1486         },
1487         .opt_clks       = iss_opt_clks,
1488         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1489 };
1490
1491 /*
1492  * 'iva' class
1493  * multi-standard video encoder/decoder hardware accelerator
1494  */
1495
1496 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1497         .name   = "iva",
1498 };
1499
1500 /* iva */
1501 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1502         { .name = "seq0", .rst_shift = 0 },
1503         { .name = "seq1", .rst_shift = 1 },
1504         { .name = "logic", .rst_shift = 2 },
1505 };
1506
1507 static struct omap_hwmod omap44xx_iva_hwmod = {
1508         .name           = "iva",
1509         .class          = &omap44xx_iva_hwmod_class,
1510         .clkdm_name     = "ivahd_clkdm",
1511         .rst_lines      = omap44xx_iva_resets,
1512         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1513         .main_clk       = "dpll_iva_m5x2_ck",
1514         .prcm = {
1515                 .omap4 = {
1516                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1517                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1518                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1519                         .modulemode   = MODULEMODE_HWCTRL,
1520                 },
1521         },
1522 };
1523
1524 /*
1525  * 'kbd' class
1526  * keyboard controller
1527  */
1528
1529 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1530         .rev_offs       = 0x0000,
1531         .sysc_offs      = 0x0010,
1532         .syss_offs      = 0x0014,
1533         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1534                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1535                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1536                            SYSS_HAS_RESET_STATUS),
1537         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1538         .sysc_fields    = &omap_hwmod_sysc_type1,
1539 };
1540
1541 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1542         .name   = "kbd",
1543         .sysc   = &omap44xx_kbd_sysc,
1544 };
1545
1546 /* kbd */
1547 static struct omap_hwmod omap44xx_kbd_hwmod = {
1548         .name           = "kbd",
1549         .class          = &omap44xx_kbd_hwmod_class,
1550         .clkdm_name     = "l4_wkup_clkdm",
1551         .main_clk       = "sys_32k_ck",
1552         .prcm = {
1553                 .omap4 = {
1554                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1555                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1556                         .modulemode   = MODULEMODE_SWCTRL,
1557                 },
1558         },
1559 };
1560
1561 /*
1562  * 'mailbox' class
1563  * mailbox module allowing communication between the on-chip processors using a
1564  * queued mailbox-interrupt mechanism.
1565  */
1566
1567 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1568         .rev_offs       = 0x0000,
1569         .sysc_offs      = 0x0010,
1570         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1571                            SYSC_HAS_SOFTRESET),
1572         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1573         .sysc_fields    = &omap_hwmod_sysc_type2,
1574 };
1575
1576 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1577         .name   = "mailbox",
1578         .sysc   = &omap44xx_mailbox_sysc,
1579 };
1580
1581 /* mailbox */
1582 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1583         .name           = "mailbox",
1584         .class          = &omap44xx_mailbox_hwmod_class,
1585         .clkdm_name     = "l4_cfg_clkdm",
1586         .prcm = {
1587                 .omap4 = {
1588                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1589                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1590                 },
1591         },
1592 };
1593
1594 /*
1595  * 'mcasp' class
1596  * multi-channel audio serial port controller
1597  */
1598
1599 /* The IP is not compliant to type1 / type2 scheme */
1600 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1601         .sidle_shift    = 0,
1602 };
1603
1604 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1605         .sysc_offs      = 0x0004,
1606         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1607         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1608                            SIDLE_SMART_WKUP),
1609         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1610 };
1611
1612 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1613         .name   = "mcasp",
1614         .sysc   = &omap44xx_mcasp_sysc,
1615 };
1616
1617 /* mcasp */
1618 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1619         .name           = "mcasp",
1620         .class          = &omap44xx_mcasp_hwmod_class,
1621         .clkdm_name     = "abe_clkdm",
1622         .main_clk       = "func_mcasp_abe_gfclk",
1623         .prcm = {
1624                 .omap4 = {
1625                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1626                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1627                         .modulemode   = MODULEMODE_SWCTRL,
1628                 },
1629         },
1630 };
1631
1632 /*
1633  * 'mcbsp' class
1634  * multi channel buffered serial port controller
1635  */
1636
1637 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1638         .sysc_offs      = 0x008c,
1639         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1640                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1641         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1642         .sysc_fields    = &omap_hwmod_sysc_type1,
1643 };
1644
1645 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1646         .name   = "mcbsp",
1647         .sysc   = &omap44xx_mcbsp_sysc,
1648         .rev    = MCBSP_CONFIG_TYPE4,
1649 };
1650
1651 /* mcbsp1 */
1652 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1653         { .role = "pad_fck", .clk = "pad_clks_ck" },
1654         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1655 };
1656
1657 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1658         .name           = "mcbsp1",
1659         .class          = &omap44xx_mcbsp_hwmod_class,
1660         .clkdm_name     = "abe_clkdm",
1661         .main_clk       = "func_mcbsp1_gfclk",
1662         .prcm = {
1663                 .omap4 = {
1664                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1665                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1666                         .modulemode   = MODULEMODE_SWCTRL,
1667                 },
1668         },
1669         .opt_clks       = mcbsp1_opt_clks,
1670         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1671 };
1672
1673 /* mcbsp2 */
1674 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1675         { .role = "pad_fck", .clk = "pad_clks_ck" },
1676         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1677 };
1678
1679 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1680         .name           = "mcbsp2",
1681         .class          = &omap44xx_mcbsp_hwmod_class,
1682         .clkdm_name     = "abe_clkdm",
1683         .main_clk       = "func_mcbsp2_gfclk",
1684         .prcm = {
1685                 .omap4 = {
1686                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1687                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1688                         .modulemode   = MODULEMODE_SWCTRL,
1689                 },
1690         },
1691         .opt_clks       = mcbsp2_opt_clks,
1692         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
1693 };
1694
1695 /* mcbsp3 */
1696 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1697         { .role = "pad_fck", .clk = "pad_clks_ck" },
1698         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1699 };
1700
1701 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
1702         .name           = "mcbsp3",
1703         .class          = &omap44xx_mcbsp_hwmod_class,
1704         .clkdm_name     = "abe_clkdm",
1705         .main_clk       = "func_mcbsp3_gfclk",
1706         .prcm = {
1707                 .omap4 = {
1708                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
1709                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1710                         .modulemode   = MODULEMODE_SWCTRL,
1711                 },
1712         },
1713         .opt_clks       = mcbsp3_opt_clks,
1714         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
1715 };
1716
1717 /* mcbsp4 */
1718 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
1719         { .role = "pad_fck", .clk = "pad_clks_ck" },
1720         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
1721 };
1722
1723 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
1724         .name           = "mcbsp4",
1725         .class          = &omap44xx_mcbsp_hwmod_class,
1726         .clkdm_name     = "l4_per_clkdm",
1727         .main_clk       = "per_mcbsp4_gfclk",
1728         .prcm = {
1729                 .omap4 = {
1730                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
1731                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
1732                         .modulemode   = MODULEMODE_SWCTRL,
1733                 },
1734         },
1735         .opt_clks       = mcbsp4_opt_clks,
1736         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
1737 };
1738
1739 /*
1740  * 'mcpdm' class
1741  * multi channel pdm controller (proprietary interface with phoenix power
1742  * ic)
1743  */
1744
1745 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
1746         .rev_offs       = 0x0000,
1747         .sysc_offs      = 0x0010,
1748         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1749                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1750         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1751                            SIDLE_SMART_WKUP),
1752         .sysc_fields    = &omap_hwmod_sysc_type2,
1753 };
1754
1755 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
1756         .name   = "mcpdm",
1757         .sysc   = &omap44xx_mcpdm_sysc,
1758 };
1759
1760 /* mcpdm */
1761 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
1762         .name           = "mcpdm",
1763         .class          = &omap44xx_mcpdm_hwmod_class,
1764         .clkdm_name     = "abe_clkdm",
1765         /*
1766          * It's suspected that the McPDM requires an off-chip main
1767          * functional clock, controlled via I2C.  This IP block is
1768          * currently reset very early during boot, before I2C is
1769          * available, so it doesn't seem that we have any choice in
1770          * the kernel other than to avoid resetting it.
1771          *
1772          * Also, McPDM needs to be configured to NO_IDLE mode when it
1773          * is in used otherwise vital clocks will be gated which
1774          * results 'slow motion' audio playback.
1775          */
1776         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1777         .main_clk       = "pad_clks_ck",
1778         .prcm = {
1779                 .omap4 = {
1780                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
1781                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
1782                         .modulemode   = MODULEMODE_SWCTRL,
1783                 },
1784         },
1785 };
1786
1787 /*
1788  * 'mcspi' class
1789  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1790  * bus
1791  */
1792
1793 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
1794         .rev_offs       = 0x0000,
1795         .sysc_offs      = 0x0010,
1796         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1797                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1798         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1799                            SIDLE_SMART_WKUP),
1800         .sysc_fields    = &omap_hwmod_sysc_type2,
1801 };
1802
1803 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
1804         .name   = "mcspi",
1805         .sysc   = &omap44xx_mcspi_sysc,
1806         .rev    = OMAP4_MCSPI_REV,
1807 };
1808
1809 /* mcspi1 */
1810 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
1811         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
1812         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
1813         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
1814         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
1815         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
1816         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
1817         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
1818         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
1819         { .dma_req = -1 }
1820 };
1821
1822 /* mcspi1 dev_attr */
1823 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1824         .num_chipselect = 4,
1825 };
1826
1827 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
1828         .name           = "mcspi1",
1829         .class          = &omap44xx_mcspi_hwmod_class,
1830         .clkdm_name     = "l4_per_clkdm",
1831         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
1832         .main_clk       = "func_48m_fclk",
1833         .prcm = {
1834                 .omap4 = {
1835                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1836                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1837                         .modulemode   = MODULEMODE_SWCTRL,
1838                 },
1839         },
1840         .dev_attr       = &mcspi1_dev_attr,
1841 };
1842
1843 /* mcspi2 */
1844 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
1845         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
1846         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
1847         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
1848         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
1849         { .dma_req = -1 }
1850 };
1851
1852 /* mcspi2 dev_attr */
1853 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1854         .num_chipselect = 2,
1855 };
1856
1857 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
1858         .name           = "mcspi2",
1859         .class          = &omap44xx_mcspi_hwmod_class,
1860         .clkdm_name     = "l4_per_clkdm",
1861         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
1862         .main_clk       = "func_48m_fclk",
1863         .prcm = {
1864                 .omap4 = {
1865                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1866                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1867                         .modulemode   = MODULEMODE_SWCTRL,
1868                 },
1869         },
1870         .dev_attr       = &mcspi2_dev_attr,
1871 };
1872
1873 /* mcspi3 */
1874 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
1875         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
1876         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
1877         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
1878         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
1879         { .dma_req = -1 }
1880 };
1881
1882 /* mcspi3 dev_attr */
1883 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1884         .num_chipselect = 2,
1885 };
1886
1887 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
1888         .name           = "mcspi3",
1889         .class          = &omap44xx_mcspi_hwmod_class,
1890         .clkdm_name     = "l4_per_clkdm",
1891         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
1892         .main_clk       = "func_48m_fclk",
1893         .prcm = {
1894                 .omap4 = {
1895                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1896                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1897                         .modulemode   = MODULEMODE_SWCTRL,
1898                 },
1899         },
1900         .dev_attr       = &mcspi3_dev_attr,
1901 };
1902
1903 /* mcspi4 */
1904 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
1905         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
1906         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
1907         { .dma_req = -1 }
1908 };
1909
1910 /* mcspi4 dev_attr */
1911 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1912         .num_chipselect = 1,
1913 };
1914
1915 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
1916         .name           = "mcspi4",
1917         .class          = &omap44xx_mcspi_hwmod_class,
1918         .clkdm_name     = "l4_per_clkdm",
1919         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
1920         .main_clk       = "func_48m_fclk",
1921         .prcm = {
1922                 .omap4 = {
1923                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1924                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1925                         .modulemode   = MODULEMODE_SWCTRL,
1926                 },
1927         },
1928         .dev_attr       = &mcspi4_dev_attr,
1929 };
1930
1931 /*
1932  * 'mmc' class
1933  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1934  */
1935
1936 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
1937         .rev_offs       = 0x0000,
1938         .sysc_offs      = 0x0010,
1939         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1940                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1941                            SYSC_HAS_SOFTRESET),
1942         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1943                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1944                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1945         .sysc_fields    = &omap_hwmod_sysc_type2,
1946 };
1947
1948 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
1949         .name   = "mmc",
1950         .sysc   = &omap44xx_mmc_sysc,
1951 };
1952
1953 /* mmc1 */
1954 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
1955         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
1956         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
1957         { .dma_req = -1 }
1958 };
1959
1960 /* mmc1 dev_attr */
1961 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1962         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1963 };
1964
1965 static struct omap_hwmod omap44xx_mmc1_hwmod = {
1966         .name           = "mmc1",
1967         .class          = &omap44xx_mmc_hwmod_class,
1968         .clkdm_name     = "l3_init_clkdm",
1969         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
1970         .main_clk       = "hsmmc1_fclk",
1971         .prcm = {
1972                 .omap4 = {
1973                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1974                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1975                         .modulemode   = MODULEMODE_SWCTRL,
1976                 },
1977         },
1978         .dev_attr       = &mmc1_dev_attr,
1979 };
1980
1981 /* mmc2 */
1982 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
1983         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
1984         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
1985         { .dma_req = -1 }
1986 };
1987
1988 static struct omap_hwmod omap44xx_mmc2_hwmod = {
1989         .name           = "mmc2",
1990         .class          = &omap44xx_mmc_hwmod_class,
1991         .clkdm_name     = "l3_init_clkdm",
1992         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
1993         .main_clk       = "hsmmc2_fclk",
1994         .prcm = {
1995                 .omap4 = {
1996                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1997                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1998                         .modulemode   = MODULEMODE_SWCTRL,
1999                 },
2000         },
2001 };
2002
2003 /* mmc3 */
2004 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2005         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2006         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2007         { .dma_req = -1 }
2008 };
2009
2010 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2011         .name           = "mmc3",
2012         .class          = &omap44xx_mmc_hwmod_class,
2013         .clkdm_name     = "l4_per_clkdm",
2014         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2015         .main_clk       = "func_48m_fclk",
2016         .prcm = {
2017                 .omap4 = {
2018                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2019                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2020                         .modulemode   = MODULEMODE_SWCTRL,
2021                 },
2022         },
2023 };
2024
2025 /* mmc4 */
2026 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2027         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2028         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2029         { .dma_req = -1 }
2030 };
2031
2032 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2033         .name           = "mmc4",
2034         .class          = &omap44xx_mmc_hwmod_class,
2035         .clkdm_name     = "l4_per_clkdm",
2036         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2037         .main_clk       = "func_48m_fclk",
2038         .prcm = {
2039                 .omap4 = {
2040                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2041                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2042                         .modulemode   = MODULEMODE_SWCTRL,
2043                 },
2044         },
2045 };
2046
2047 /* mmc5 */
2048 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2049         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2050         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2051         { .dma_req = -1 }
2052 };
2053
2054 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2055         .name           = "mmc5",
2056         .class          = &omap44xx_mmc_hwmod_class,
2057         .clkdm_name     = "l4_per_clkdm",
2058         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2059         .main_clk       = "func_48m_fclk",
2060         .prcm = {
2061                 .omap4 = {
2062                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2063                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2064                         .modulemode   = MODULEMODE_SWCTRL,
2065                 },
2066         },
2067 };
2068
2069 /*
2070  * 'mmu' class
2071  * The memory management unit performs virtual to physical address translation
2072  * for its requestors.
2073  */
2074
2075 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2076         .rev_offs       = 0x000,
2077         .sysc_offs      = 0x010,
2078         .syss_offs      = 0x014,
2079         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2080                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2081         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2082         .sysc_fields    = &omap_hwmod_sysc_type1,
2083 };
2084
2085 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2086         .name = "mmu",
2087         .sysc = &mmu_sysc,
2088 };
2089
2090 /* mmu ipu */
2091
2092 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2093         .nr_tlb_entries = 32,
2094 };
2095
2096 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2097 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2098         { .name = "mmu_cache", .rst_shift = 2 },
2099 };
2100
2101 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2102         {
2103                 .pa_start       = 0x55082000,
2104                 .pa_end         = 0x550820ff,
2105                 .flags          = ADDR_TYPE_RT,
2106         },
2107         { }
2108 };
2109
2110 /* l3_main_2 -> mmu_ipu */
2111 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2112         .master         = &omap44xx_l3_main_2_hwmod,
2113         .slave          = &omap44xx_mmu_ipu_hwmod,
2114         .clk            = "l3_div_ck",
2115         .addr           = omap44xx_mmu_ipu_addrs,
2116         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2117 };
2118
2119 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2120         .name           = "mmu_ipu",
2121         .class          = &omap44xx_mmu_hwmod_class,
2122         .clkdm_name     = "ducati_clkdm",
2123         .rst_lines      = omap44xx_mmu_ipu_resets,
2124         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2125         .main_clk       = "ducati_clk_mux_ck",
2126         .prcm = {
2127                 .omap4 = {
2128                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2129                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2130                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2131                         .modulemode   = MODULEMODE_HWCTRL,
2132                 },
2133         },
2134         .dev_attr       = &mmu_ipu_dev_attr,
2135 };
2136
2137 /* mmu dsp */
2138
2139 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2140         .nr_tlb_entries = 32,
2141 };
2142
2143 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2144 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2145         { .name = "mmu_cache", .rst_shift = 1 },
2146 };
2147
2148 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2149         {
2150                 .pa_start       = 0x4a066000,
2151                 .pa_end         = 0x4a0660ff,
2152                 .flags          = ADDR_TYPE_RT,
2153         },
2154         { }
2155 };
2156
2157 /* l4_cfg -> dsp */
2158 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2159         .master         = &omap44xx_l4_cfg_hwmod,
2160         .slave          = &omap44xx_mmu_dsp_hwmod,
2161         .clk            = "l4_div_ck",
2162         .addr           = omap44xx_mmu_dsp_addrs,
2163         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2164 };
2165
2166 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2167         .name           = "mmu_dsp",
2168         .class          = &omap44xx_mmu_hwmod_class,
2169         .clkdm_name     = "tesla_clkdm",
2170         .rst_lines      = omap44xx_mmu_dsp_resets,
2171         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2172         .main_clk       = "dpll_iva_m4x2_ck",
2173         .prcm = {
2174                 .omap4 = {
2175                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2176                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2177                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2178                         .modulemode   = MODULEMODE_HWCTRL,
2179                 },
2180         },
2181         .dev_attr       = &mmu_dsp_dev_attr,
2182 };
2183
2184 /*
2185  * 'mpu' class
2186  * mpu sub-system
2187  */
2188
2189 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2190         .name   = "mpu",
2191 };
2192
2193 /* mpu */
2194 static struct omap_hwmod omap44xx_mpu_hwmod = {
2195         .name           = "mpu",
2196         .class          = &omap44xx_mpu_hwmod_class,
2197         .clkdm_name     = "mpuss_clkdm",
2198         .flags          = HWMOD_INIT_NO_IDLE,
2199         .main_clk       = "dpll_mpu_m2_ck",
2200         .prcm = {
2201                 .omap4 = {
2202                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2203                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2204                 },
2205         },
2206 };
2207
2208 /*
2209  * 'ocmc_ram' class
2210  * top-level core on-chip ram
2211  */
2212
2213 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2214         .name   = "ocmc_ram",
2215 };
2216
2217 /* ocmc_ram */
2218 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2219         .name           = "ocmc_ram",
2220         .class          = &omap44xx_ocmc_ram_hwmod_class,
2221         .clkdm_name     = "l3_2_clkdm",
2222         .prcm = {
2223                 .omap4 = {
2224                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2225                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2226                 },
2227         },
2228 };
2229
2230 /*
2231  * 'ocp2scp' class
2232  * bridge to transform ocp interface protocol to scp (serial control port)
2233  * protocol
2234  */
2235
2236 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2237         .rev_offs       = 0x0000,
2238         .sysc_offs      = 0x0010,
2239         .syss_offs      = 0x0014,
2240         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2241                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2242         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2243         .sysc_fields    = &omap_hwmod_sysc_type1,
2244 };
2245
2246 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2247         .name   = "ocp2scp",
2248         .sysc   = &omap44xx_ocp2scp_sysc,
2249 };
2250
2251 /* ocp2scp_usb_phy */
2252 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2253         .name           = "ocp2scp_usb_phy",
2254         .class          = &omap44xx_ocp2scp_hwmod_class,
2255         .clkdm_name     = "l3_init_clkdm",
2256         /*
2257          * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
2258          * block as an "optional clock," and normally should never be
2259          * specified as the main_clk for an OMAP IP block.  However it
2260          * turns out that this clock is actually the main clock for
2261          * the ocp2scp_usb_phy IP block:
2262          * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
2263          * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
2264          * to be the best workaround.
2265          */
2266         .main_clk       = "ocp2scp_usb_phy_phy_48m",
2267         .prcm = {
2268                 .omap4 = {
2269                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2270                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2271                         .modulemode   = MODULEMODE_HWCTRL,
2272                 },
2273         },
2274 };
2275
2276 /*
2277  * 'prcm' class
2278  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2279  * + clock manager 1 (in always on power domain) + local prm in mpu
2280  */
2281
2282 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2283         .name   = "prcm",
2284 };
2285
2286 /* prcm_mpu */
2287 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2288         .name           = "prcm_mpu",
2289         .class          = &omap44xx_prcm_hwmod_class,
2290         .clkdm_name     = "l4_wkup_clkdm",
2291         .flags          = HWMOD_NO_IDLEST,
2292         .prcm = {
2293                 .omap4 = {
2294                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2295                 },
2296         },
2297 };
2298
2299 /* cm_core_aon */
2300 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2301         .name           = "cm_core_aon",
2302         .class          = &omap44xx_prcm_hwmod_class,
2303         .flags          = HWMOD_NO_IDLEST,
2304         .prcm = {
2305                 .omap4 = {
2306                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2307                 },
2308         },
2309 };
2310
2311 /* cm_core */
2312 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2313         .name           = "cm_core",
2314         .class          = &omap44xx_prcm_hwmod_class,
2315         .flags          = HWMOD_NO_IDLEST,
2316         .prcm = {
2317                 .omap4 = {
2318                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2319                 },
2320         },
2321 };
2322
2323 /* prm */
2324 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2325         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2326         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2327 };
2328
2329 static struct omap_hwmod omap44xx_prm_hwmod = {
2330         .name           = "prm",
2331         .class          = &omap44xx_prcm_hwmod_class,
2332         .rst_lines      = omap44xx_prm_resets,
2333         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2334 };
2335
2336 /*
2337  * 'scrm' class
2338  * system clock and reset manager
2339  */
2340
2341 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2342         .name   = "scrm",
2343 };
2344
2345 /* scrm */
2346 static struct omap_hwmod omap44xx_scrm_hwmod = {
2347         .name           = "scrm",
2348         .class          = &omap44xx_scrm_hwmod_class,
2349         .clkdm_name     = "l4_wkup_clkdm",
2350         .prcm = {
2351                 .omap4 = {
2352                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2353                 },
2354         },
2355 };
2356
2357 /*
2358  * 'sl2if' class
2359  * shared level 2 memory interface
2360  */
2361
2362 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2363         .name   = "sl2if",
2364 };
2365
2366 /* sl2if */
2367 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2368         .name           = "sl2if",
2369         .class          = &omap44xx_sl2if_hwmod_class,
2370         .clkdm_name     = "ivahd_clkdm",
2371         .prcm = {
2372                 .omap4 = {
2373                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2374                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2375                         .modulemode   = MODULEMODE_HWCTRL,
2376                 },
2377         },
2378 };
2379
2380 /*
2381  * 'slimbus' class
2382  * bidirectional, multi-drop, multi-channel two-line serial interface between
2383  * the device and external components
2384  */
2385
2386 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2387         .rev_offs       = 0x0000,
2388         .sysc_offs      = 0x0010,
2389         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2390                            SYSC_HAS_SOFTRESET),
2391         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2392                            SIDLE_SMART_WKUP),
2393         .sysc_fields    = &omap_hwmod_sysc_type2,
2394 };
2395
2396 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2397         .name   = "slimbus",
2398         .sysc   = &omap44xx_slimbus_sysc,
2399 };
2400
2401 /* slimbus1 */
2402 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2403         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2404         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2405         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2406         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2407 };
2408
2409 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2410         .name           = "slimbus1",
2411         .class          = &omap44xx_slimbus_hwmod_class,
2412         .clkdm_name     = "abe_clkdm",
2413         .prcm = {
2414                 .omap4 = {
2415                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2416                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2417                         .modulemode   = MODULEMODE_SWCTRL,
2418                 },
2419         },
2420         .opt_clks       = slimbus1_opt_clks,
2421         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2422 };
2423
2424 /* slimbus2 */
2425 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2426         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2427         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2428         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2429 };
2430
2431 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2432         .name           = "slimbus2",
2433         .class          = &omap44xx_slimbus_hwmod_class,
2434         .clkdm_name     = "l4_per_clkdm",
2435         .prcm = {
2436                 .omap4 = {
2437                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2438                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2439                         .modulemode   = MODULEMODE_SWCTRL,
2440                 },
2441         },
2442         .opt_clks       = slimbus2_opt_clks,
2443         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2444 };
2445
2446 /*
2447  * 'smartreflex' class
2448  * smartreflex module (monitor silicon performance and outputs a measure of
2449  * performance error)
2450  */
2451
2452 /* The IP is not compliant to type1 / type2 scheme */
2453 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2454         .sidle_shift    = 24,
2455         .enwkup_shift   = 26,
2456 };
2457
2458 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2459         .sysc_offs      = 0x0038,
2460         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2461         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2462                            SIDLE_SMART_WKUP),
2463         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2464 };
2465
2466 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2467         .name   = "smartreflex",
2468         .sysc   = &omap44xx_smartreflex_sysc,
2469         .rev    = 2,
2470 };
2471
2472 /* smartreflex_core */
2473 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2474         .sensor_voltdm_name   = "core",
2475 };
2476
2477 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2478         .name           = "smartreflex_core",
2479         .class          = &omap44xx_smartreflex_hwmod_class,
2480         .clkdm_name     = "l4_ao_clkdm",
2481
2482         .main_clk       = "smartreflex_core_fck",
2483         .prcm = {
2484                 .omap4 = {
2485                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2486                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2487                         .modulemode   = MODULEMODE_SWCTRL,
2488                 },
2489         },
2490         .dev_attr       = &smartreflex_core_dev_attr,
2491 };
2492
2493 /* smartreflex_iva */
2494 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2495         .sensor_voltdm_name     = "iva",
2496 };
2497
2498 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2499         .name           = "smartreflex_iva",
2500         .class          = &omap44xx_smartreflex_hwmod_class,
2501         .clkdm_name     = "l4_ao_clkdm",
2502         .main_clk       = "smartreflex_iva_fck",
2503         .prcm = {
2504                 .omap4 = {
2505                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2506                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2507                         .modulemode   = MODULEMODE_SWCTRL,
2508                 },
2509         },
2510         .dev_attr       = &smartreflex_iva_dev_attr,
2511 };
2512
2513 /* smartreflex_mpu */
2514 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2515         .sensor_voltdm_name     = "mpu",
2516 };
2517
2518 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2519         .name           = "smartreflex_mpu",
2520         .class          = &omap44xx_smartreflex_hwmod_class,
2521         .clkdm_name     = "l4_ao_clkdm",
2522         .main_clk       = "smartreflex_mpu_fck",
2523         .prcm = {
2524                 .omap4 = {
2525                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2526                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2527                         .modulemode   = MODULEMODE_SWCTRL,
2528                 },
2529         },
2530         .dev_attr       = &smartreflex_mpu_dev_attr,
2531 };
2532
2533 /*
2534  * 'spinlock' class
2535  * spinlock provides hardware assistance for synchronizing the processes
2536  * running on multiple processors
2537  */
2538
2539 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2540         .rev_offs       = 0x0000,
2541         .sysc_offs      = 0x0010,
2542         .syss_offs      = 0x0014,
2543         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2544                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2545                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2546         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2547         .sysc_fields    = &omap_hwmod_sysc_type1,
2548 };
2549
2550 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2551         .name   = "spinlock",
2552         .sysc   = &omap44xx_spinlock_sysc,
2553 };
2554
2555 /* spinlock */
2556 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2557         .name           = "spinlock",
2558         .class          = &omap44xx_spinlock_hwmod_class,
2559         .clkdm_name     = "l4_cfg_clkdm",
2560         .prcm = {
2561                 .omap4 = {
2562                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2563                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2564                 },
2565         },
2566 };
2567
2568 /*
2569  * 'timer' class
2570  * general purpose timer module with accurate 1ms tick
2571  * This class contains several variants: ['timer_1ms', 'timer']
2572  */
2573
2574 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2575         .rev_offs       = 0x0000,
2576         .sysc_offs      = 0x0010,
2577         .syss_offs      = 0x0014,
2578         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2579                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2580                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2581                            SYSS_HAS_RESET_STATUS),
2582         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2583         .clockact       = CLOCKACT_TEST_ICLK,
2584         .sysc_fields    = &omap_hwmod_sysc_type1,
2585 };
2586
2587 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2588         .name   = "timer",
2589         .sysc   = &omap44xx_timer_1ms_sysc,
2590 };
2591
2592 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2593         .rev_offs       = 0x0000,
2594         .sysc_offs      = 0x0010,
2595         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2596                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2597         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2598                            SIDLE_SMART_WKUP),
2599         .sysc_fields    = &omap_hwmod_sysc_type2,
2600 };
2601
2602 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2603         .name   = "timer",
2604         .sysc   = &omap44xx_timer_sysc,
2605 };
2606
2607 /* always-on timers dev attribute */
2608 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2609         .timer_capability       = OMAP_TIMER_ALWON,
2610 };
2611
2612 /* pwm timers dev attribute */
2613 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2614         .timer_capability       = OMAP_TIMER_HAS_PWM,
2615 };
2616
2617 /* timers with DSP interrupt dev attribute */
2618 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
2619         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
2620 };
2621
2622 /* pwm timers with DSP interrupt dev attribute */
2623 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
2624         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
2625 };
2626
2627 /* timer1 */
2628 static struct omap_hwmod omap44xx_timer1_hwmod = {
2629         .name           = "timer1",
2630         .class          = &omap44xx_timer_1ms_hwmod_class,
2631         .clkdm_name     = "l4_wkup_clkdm",
2632         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2633         .main_clk       = "dmt1_clk_mux",
2634         .prcm = {
2635                 .omap4 = {
2636                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2637                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2638                         .modulemode   = MODULEMODE_SWCTRL,
2639                 },
2640         },
2641         .dev_attr       = &capability_alwon_dev_attr,
2642 };
2643
2644 /* timer2 */
2645 static struct omap_hwmod omap44xx_timer2_hwmod = {
2646         .name           = "timer2",
2647         .class          = &omap44xx_timer_1ms_hwmod_class,
2648         .clkdm_name     = "l4_per_clkdm",
2649         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2650         .main_clk       = "cm2_dm2_mux",
2651         .prcm = {
2652                 .omap4 = {
2653                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2654                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2655                         .modulemode   = MODULEMODE_SWCTRL,
2656                 },
2657         },
2658 };
2659
2660 /* timer3 */
2661 static struct omap_hwmod omap44xx_timer3_hwmod = {
2662         .name           = "timer3",
2663         .class          = &omap44xx_timer_hwmod_class,
2664         .clkdm_name     = "l4_per_clkdm",
2665         .main_clk       = "cm2_dm3_mux",
2666         .prcm = {
2667                 .omap4 = {
2668                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2669                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2670                         .modulemode   = MODULEMODE_SWCTRL,
2671                 },
2672         },
2673 };
2674
2675 /* timer4 */
2676 static struct omap_hwmod omap44xx_timer4_hwmod = {
2677         .name           = "timer4",
2678         .class          = &omap44xx_timer_hwmod_class,
2679         .clkdm_name     = "l4_per_clkdm",
2680         .main_clk       = "cm2_dm4_mux",
2681         .prcm = {
2682                 .omap4 = {
2683                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2684                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2685                         .modulemode   = MODULEMODE_SWCTRL,
2686                 },
2687         },
2688 };
2689
2690 /* timer5 */
2691 static struct omap_hwmod omap44xx_timer5_hwmod = {
2692         .name           = "timer5",
2693         .class          = &omap44xx_timer_hwmod_class,
2694         .clkdm_name     = "abe_clkdm",
2695         .main_clk       = "timer5_sync_mux",
2696         .prcm = {
2697                 .omap4 = {
2698                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
2699                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
2700                         .modulemode   = MODULEMODE_SWCTRL,
2701                 },
2702         },
2703         .dev_attr       = &capability_dsp_dev_attr,
2704 };
2705
2706 /* timer6 */
2707 static struct omap_hwmod omap44xx_timer6_hwmod = {
2708         .name           = "timer6",
2709         .class          = &omap44xx_timer_hwmod_class,
2710         .clkdm_name     = "abe_clkdm",
2711         .main_clk       = "timer6_sync_mux",
2712         .prcm = {
2713                 .omap4 = {
2714                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
2715                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
2716                         .modulemode   = MODULEMODE_SWCTRL,
2717                 },
2718         },
2719         .dev_attr       = &capability_dsp_dev_attr,
2720 };
2721
2722 /* timer7 */
2723 static struct omap_hwmod omap44xx_timer7_hwmod = {
2724         .name           = "timer7",
2725         .class          = &omap44xx_timer_hwmod_class,
2726         .clkdm_name     = "abe_clkdm",
2727         .main_clk       = "timer7_sync_mux",
2728         .prcm = {
2729                 .omap4 = {
2730                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
2731                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
2732                         .modulemode   = MODULEMODE_SWCTRL,
2733                 },
2734         },
2735         .dev_attr       = &capability_dsp_dev_attr,
2736 };
2737
2738 /* timer8 */
2739 static struct omap_hwmod omap44xx_timer8_hwmod = {
2740         .name           = "timer8",
2741         .class          = &omap44xx_timer_hwmod_class,
2742         .clkdm_name     = "abe_clkdm",
2743         .main_clk       = "timer8_sync_mux",
2744         .prcm = {
2745                 .omap4 = {
2746                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
2747                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
2748                         .modulemode   = MODULEMODE_SWCTRL,
2749                 },
2750         },
2751         .dev_attr       = &capability_dsp_pwm_dev_attr,
2752 };
2753
2754 /* timer9 */
2755 static struct omap_hwmod omap44xx_timer9_hwmod = {
2756         .name           = "timer9",
2757         .class          = &omap44xx_timer_hwmod_class,
2758         .clkdm_name     = "l4_per_clkdm",
2759         .main_clk       = "cm2_dm9_mux",
2760         .prcm = {
2761                 .omap4 = {
2762                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
2763                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
2764                         .modulemode   = MODULEMODE_SWCTRL,
2765                 },
2766         },
2767         .dev_attr       = &capability_pwm_dev_attr,
2768 };
2769
2770 /* timer10 */
2771 static struct omap_hwmod omap44xx_timer10_hwmod = {
2772         .name           = "timer10",
2773         .class          = &omap44xx_timer_1ms_hwmod_class,
2774         .clkdm_name     = "l4_per_clkdm",
2775         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2776         .main_clk       = "cm2_dm10_mux",
2777         .prcm = {
2778                 .omap4 = {
2779                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
2780                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
2781                         .modulemode   = MODULEMODE_SWCTRL,
2782                 },
2783         },
2784         .dev_attr       = &capability_pwm_dev_attr,
2785 };
2786
2787 /* timer11 */
2788 static struct omap_hwmod omap44xx_timer11_hwmod = {
2789         .name           = "timer11",
2790         .class          = &omap44xx_timer_hwmod_class,
2791         .clkdm_name     = "l4_per_clkdm",
2792         .main_clk       = "cm2_dm11_mux",
2793         .prcm = {
2794                 .omap4 = {
2795                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
2796                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
2797                         .modulemode   = MODULEMODE_SWCTRL,
2798                 },
2799         },
2800         .dev_attr       = &capability_pwm_dev_attr,
2801 };
2802
2803 /*
2804  * 'uart' class
2805  * universal asynchronous receiver/transmitter (uart)
2806  */
2807
2808 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
2809         .rev_offs       = 0x0050,
2810         .sysc_offs      = 0x0054,
2811         .syss_offs      = 0x0058,
2812         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2813                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2814                            SYSS_HAS_RESET_STATUS),
2815         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2816                            SIDLE_SMART_WKUP),
2817         .sysc_fields    = &omap_hwmod_sysc_type1,
2818 };
2819
2820 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
2821         .name   = "uart",
2822         .sysc   = &omap44xx_uart_sysc,
2823 };
2824
2825 /* uart1 */
2826 static struct omap_hwmod omap44xx_uart1_hwmod = {
2827         .name           = "uart1",
2828         .class          = &omap44xx_uart_hwmod_class,
2829         .clkdm_name     = "l4_per_clkdm",
2830         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2831         .main_clk       = "func_48m_fclk",
2832         .prcm = {
2833                 .omap4 = {
2834                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
2835                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
2836                         .modulemode   = MODULEMODE_SWCTRL,
2837                 },
2838         },
2839 };
2840
2841 /* uart2 */
2842 static struct omap_hwmod omap44xx_uart2_hwmod = {
2843         .name           = "uart2",
2844         .class          = &omap44xx_uart_hwmod_class,
2845         .clkdm_name     = "l4_per_clkdm",
2846         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2847         .main_clk       = "func_48m_fclk",
2848         .prcm = {
2849                 .omap4 = {
2850                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
2851                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
2852                         .modulemode   = MODULEMODE_SWCTRL,
2853                 },
2854         },
2855 };
2856
2857 /* uart3 */
2858 static struct omap_hwmod omap44xx_uart3_hwmod = {
2859         .name           = "uart3",
2860         .class          = &omap44xx_uart_hwmod_class,
2861         .clkdm_name     = "l4_per_clkdm",
2862         .flags          = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2863         .main_clk       = "func_48m_fclk",
2864         .prcm = {
2865                 .omap4 = {
2866                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
2867                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
2868                         .modulemode   = MODULEMODE_SWCTRL,
2869                 },
2870         },
2871 };
2872
2873 /* uart4 */
2874 static struct omap_hwmod omap44xx_uart4_hwmod = {
2875         .name           = "uart4",
2876         .class          = &omap44xx_uart_hwmod_class,
2877         .clkdm_name     = "l4_per_clkdm",
2878         .flags          = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2879         .main_clk       = "func_48m_fclk",
2880         .prcm = {
2881                 .omap4 = {
2882                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
2883                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
2884                         .modulemode   = MODULEMODE_SWCTRL,
2885                 },
2886         },
2887 };
2888
2889 /*
2890  * 'usb_host_fs' class
2891  * full-speed usb host controller
2892  */
2893
2894 /* The IP is not compliant to type1 / type2 scheme */
2895 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
2896         .midle_shift    = 4,
2897         .sidle_shift    = 2,
2898         .srst_shift     = 1,
2899 };
2900
2901 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
2902         .rev_offs       = 0x0000,
2903         .sysc_offs      = 0x0210,
2904         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2905                            SYSC_HAS_SOFTRESET),
2906         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2907                            SIDLE_SMART_WKUP),
2908         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
2909 };
2910
2911 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
2912         .name   = "usb_host_fs",
2913         .sysc   = &omap44xx_usb_host_fs_sysc,
2914 };
2915
2916 /* usb_host_fs */
2917 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
2918         .name           = "usb_host_fs",
2919         .class          = &omap44xx_usb_host_fs_hwmod_class,
2920         .clkdm_name     = "l3_init_clkdm",
2921         .main_clk       = "usb_host_fs_fck",
2922         .prcm = {
2923                 .omap4 = {
2924                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
2925                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
2926                         .modulemode   = MODULEMODE_SWCTRL,
2927                 },
2928         },
2929 };
2930
2931 /*
2932  * 'usb_host_hs' class
2933  * high-speed multi-port usb host controller
2934  */
2935
2936 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
2937         .rev_offs       = 0x0000,
2938         .sysc_offs      = 0x0010,
2939         .syss_offs      = 0x0014,
2940         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2941                            SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
2942         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2943                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2944                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2945         .sysc_fields    = &omap_hwmod_sysc_type2,
2946 };
2947
2948 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
2949         .name   = "usb_host_hs",
2950         .sysc   = &omap44xx_usb_host_hs_sysc,
2951 };
2952
2953 /* usb_host_hs */
2954 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
2955         .name           = "usb_host_hs",
2956         .class          = &omap44xx_usb_host_hs_hwmod_class,
2957         .clkdm_name     = "l3_init_clkdm",
2958         .main_clk       = "usb_host_hs_fck",
2959         .prcm = {
2960                 .omap4 = {
2961                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
2962                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
2963                         .modulemode   = MODULEMODE_SWCTRL,
2964                 },
2965         },
2966
2967         /*
2968          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
2969          * id: i660
2970          *
2971          * Description:
2972          * In the following configuration :
2973          * - USBHOST module is set to smart-idle mode
2974          * - PRCM asserts idle_req to the USBHOST module ( This typically
2975          *   happens when the system is going to a low power mode : all ports
2976          *   have been suspended, the master part of the USBHOST module has
2977          *   entered the standby state, and SW has cut the functional clocks)
2978          * - an USBHOST interrupt occurs before the module is able to answer
2979          *   idle_ack, typically a remote wakeup IRQ.
2980          * Then the USB HOST module will enter a deadlock situation where it
2981          * is no more accessible nor functional.
2982          *
2983          * Workaround:
2984          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2985          */
2986
2987         /*
2988          * Errata: USB host EHCI may stall when entering smart-standby mode
2989          * Id: i571
2990          *
2991          * Description:
2992          * When the USBHOST module is set to smart-standby mode, and when it is
2993          * ready to enter the standby state (i.e. all ports are suspended and
2994          * all attached devices are in suspend mode), then it can wrongly assert
2995          * the Mstandby signal too early while there are still some residual OCP
2996          * transactions ongoing. If this condition occurs, the internal state
2997          * machine may go to an undefined state and the USB link may be stuck
2998          * upon the next resume.
2999          *
3000          * Workaround:
3001          * Don't use smart standby; use only force standby,
3002          * hence HWMOD_SWSUP_MSTANDBY
3003          */
3004
3005         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3006 };
3007
3008 /*
3009  * 'usb_otg_hs' class
3010  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3011  */
3012
3013 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3014         .rev_offs       = 0x0400,
3015         .sysc_offs      = 0x0404,
3016         .syss_offs      = 0x0408,
3017         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3018                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3019                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3020         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3021                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3022                            MSTANDBY_SMART),
3023         .sysc_fields    = &omap_hwmod_sysc_type1,
3024 };
3025
3026 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3027         .name   = "usb_otg_hs",
3028         .sysc   = &omap44xx_usb_otg_hs_sysc,
3029 };
3030
3031 /* usb_otg_hs */
3032 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3033         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3034 };
3035
3036 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3037         .name           = "usb_otg_hs",
3038         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3039         .clkdm_name     = "l3_init_clkdm",
3040         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3041         .main_clk       = "usb_otg_hs_ick",
3042         .prcm = {
3043                 .omap4 = {
3044                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3045                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3046                         .modulemode   = MODULEMODE_HWCTRL,
3047                 },
3048         },
3049         .opt_clks       = usb_otg_hs_opt_clks,
3050         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3051 };
3052
3053 /*
3054  * 'usb_tll_hs' class
3055  * usb_tll_hs module is the adapter on the usb_host_hs ports
3056  */
3057
3058 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3059         .rev_offs       = 0x0000,
3060         .sysc_offs      = 0x0010,
3061         .syss_offs      = 0x0014,
3062         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3063                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3064                            SYSC_HAS_AUTOIDLE),
3065         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3066         .sysc_fields    = &omap_hwmod_sysc_type1,
3067 };
3068
3069 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3070         .name   = "usb_tll_hs",
3071         .sysc   = &omap44xx_usb_tll_hs_sysc,
3072 };
3073
3074 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3075         .name           = "usb_tll_hs",
3076         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3077         .clkdm_name     = "l3_init_clkdm",
3078         .main_clk       = "usb_tll_hs_ick",
3079         .prcm = {
3080                 .omap4 = {
3081                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3082                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3083                         .modulemode   = MODULEMODE_HWCTRL,
3084                 },
3085         },
3086 };
3087
3088 /*
3089  * 'wd_timer' class
3090  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3091  * overflow condition
3092  */
3093
3094 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3095         .rev_offs       = 0x0000,
3096         .sysc_offs      = 0x0010,
3097         .syss_offs      = 0x0014,
3098         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3099                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3100         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3101                            SIDLE_SMART_WKUP),
3102         .sysc_fields    = &omap_hwmod_sysc_type1,
3103 };
3104
3105 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3106         .name           = "wd_timer",
3107         .sysc           = &omap44xx_wd_timer_sysc,
3108         .pre_shutdown   = &omap2_wd_timer_disable,
3109         .reset          = &omap2_wd_timer_reset,
3110 };
3111
3112 /* wd_timer2 */
3113 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3114         .name           = "wd_timer2",
3115         .class          = &omap44xx_wd_timer_hwmod_class,
3116         .clkdm_name     = "l4_wkup_clkdm",
3117         .main_clk       = "sys_32k_ck",
3118         .prcm = {
3119                 .omap4 = {
3120                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3121                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3122                         .modulemode   = MODULEMODE_SWCTRL,
3123                 },
3124         },
3125 };
3126
3127 /* wd_timer3 */
3128 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3129         .name           = "wd_timer3",
3130         .class          = &omap44xx_wd_timer_hwmod_class,
3131         .clkdm_name     = "abe_clkdm",
3132         .main_clk       = "sys_32k_ck",
3133         .prcm = {
3134                 .omap4 = {
3135                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3136                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3137                         .modulemode   = MODULEMODE_SWCTRL,
3138                 },
3139         },
3140 };
3141
3142
3143 /*
3144  * interfaces
3145  */
3146
3147 /* l3_main_1 -> dmm */
3148 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3149         .master         = &omap44xx_l3_main_1_hwmod,
3150         .slave          = &omap44xx_dmm_hwmod,
3151         .clk            = "l3_div_ck",
3152         .user           = OCP_USER_SDMA,
3153 };
3154
3155 /* mpu -> dmm */
3156 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3157         .master         = &omap44xx_mpu_hwmod,
3158         .slave          = &omap44xx_dmm_hwmod,
3159         .clk            = "l3_div_ck",
3160         .user           = OCP_USER_MPU,
3161 };
3162
3163 /* iva -> l3_instr */
3164 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3165         .master         = &omap44xx_iva_hwmod,
3166         .slave          = &omap44xx_l3_instr_hwmod,
3167         .clk            = "l3_div_ck",
3168         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3169 };
3170
3171 /* l3_main_3 -> l3_instr */
3172 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3173         .master         = &omap44xx_l3_main_3_hwmod,
3174         .slave          = &omap44xx_l3_instr_hwmod,
3175         .clk            = "l3_div_ck",
3176         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3177 };
3178
3179 /* ocp_wp_noc -> l3_instr */
3180 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3181         .master         = &omap44xx_ocp_wp_noc_hwmod,
3182         .slave          = &omap44xx_l3_instr_hwmod,
3183         .clk            = "l3_div_ck",
3184         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3185 };
3186
3187 /* dsp -> l3_main_1 */
3188 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3189         .master         = &omap44xx_dsp_hwmod,
3190         .slave          = &omap44xx_l3_main_1_hwmod,
3191         .clk            = "l3_div_ck",
3192         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3193 };
3194
3195 /* dss -> l3_main_1 */
3196 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3197         .master         = &omap44xx_dss_hwmod,
3198         .slave          = &omap44xx_l3_main_1_hwmod,
3199         .clk            = "l3_div_ck",
3200         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3201 };
3202
3203 /* l3_main_2 -> l3_main_1 */
3204 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3205         .master         = &omap44xx_l3_main_2_hwmod,
3206         .slave          = &omap44xx_l3_main_1_hwmod,
3207         .clk            = "l3_div_ck",
3208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3209 };
3210
3211 /* l4_cfg -> l3_main_1 */
3212 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3213         .master         = &omap44xx_l4_cfg_hwmod,
3214         .slave          = &omap44xx_l3_main_1_hwmod,
3215         .clk            = "l4_div_ck",
3216         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3217 };
3218
3219 /* mmc1 -> l3_main_1 */
3220 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3221         .master         = &omap44xx_mmc1_hwmod,
3222         .slave          = &omap44xx_l3_main_1_hwmod,
3223         .clk            = "l3_div_ck",
3224         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3225 };
3226
3227 /* mmc2 -> l3_main_1 */
3228 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3229         .master         = &omap44xx_mmc2_hwmod,
3230         .slave          = &omap44xx_l3_main_1_hwmod,
3231         .clk            = "l3_div_ck",
3232         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3233 };
3234
3235 /* mpu -> l3_main_1 */
3236 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3237         .master         = &omap44xx_mpu_hwmod,
3238         .slave          = &omap44xx_l3_main_1_hwmod,
3239         .clk            = "l3_div_ck",
3240         .user           = OCP_USER_MPU,
3241 };
3242
3243 /* debugss -> l3_main_2 */
3244 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3245         .master         = &omap44xx_debugss_hwmod,
3246         .slave          = &omap44xx_l3_main_2_hwmod,
3247         .clk            = "dbgclk_mux_ck",
3248         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3249 };
3250
3251 /* dma_system -> l3_main_2 */
3252 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3253         .master         = &omap44xx_dma_system_hwmod,
3254         .slave          = &omap44xx_l3_main_2_hwmod,
3255         .clk            = "l3_div_ck",
3256         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3257 };
3258
3259 /* fdif -> l3_main_2 */
3260 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3261         .master         = &omap44xx_fdif_hwmod,
3262         .slave          = &omap44xx_l3_main_2_hwmod,
3263         .clk            = "l3_div_ck",
3264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3265 };
3266
3267 /* gpu -> l3_main_2 */
3268 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3269         .master         = &omap44xx_gpu_hwmod,
3270         .slave          = &omap44xx_l3_main_2_hwmod,
3271         .clk            = "l3_div_ck",
3272         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3273 };
3274
3275 /* hsi -> l3_main_2 */
3276 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3277         .master         = &omap44xx_hsi_hwmod,
3278         .slave          = &omap44xx_l3_main_2_hwmod,
3279         .clk            = "l3_div_ck",
3280         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3281 };
3282
3283 /* ipu -> l3_main_2 */
3284 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3285         .master         = &omap44xx_ipu_hwmod,
3286         .slave          = &omap44xx_l3_main_2_hwmod,
3287         .clk            = "l3_div_ck",
3288         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3289 };
3290
3291 /* iss -> l3_main_2 */
3292 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3293         .master         = &omap44xx_iss_hwmod,
3294         .slave          = &omap44xx_l3_main_2_hwmod,
3295         .clk            = "l3_div_ck",
3296         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3297 };
3298
3299 /* iva -> l3_main_2 */
3300 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3301         .master         = &omap44xx_iva_hwmod,
3302         .slave          = &omap44xx_l3_main_2_hwmod,
3303         .clk            = "l3_div_ck",
3304         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3305 };
3306
3307 /* l3_main_1 -> l3_main_2 */
3308 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3309         .master         = &omap44xx_l3_main_1_hwmod,
3310         .slave          = &omap44xx_l3_main_2_hwmod,
3311         .clk            = "l3_div_ck",
3312         .user           = OCP_USER_MPU,
3313 };
3314
3315 /* l4_cfg -> l3_main_2 */
3316 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3317         .master         = &omap44xx_l4_cfg_hwmod,
3318         .slave          = &omap44xx_l3_main_2_hwmod,
3319         .clk            = "l4_div_ck",
3320         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3321 };
3322
3323 /* usb_host_fs -> l3_main_2 */
3324 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3325         .master         = &omap44xx_usb_host_fs_hwmod,
3326         .slave          = &omap44xx_l3_main_2_hwmod,
3327         .clk            = "l3_div_ck",
3328         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3329 };
3330
3331 /* usb_host_hs -> l3_main_2 */
3332 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3333         .master         = &omap44xx_usb_host_hs_hwmod,
3334         .slave          = &omap44xx_l3_main_2_hwmod,
3335         .clk            = "l3_div_ck",
3336         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3337 };
3338
3339 /* usb_otg_hs -> l3_main_2 */
3340 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3341         .master         = &omap44xx_usb_otg_hs_hwmod,
3342         .slave          = &omap44xx_l3_main_2_hwmod,
3343         .clk            = "l3_div_ck",
3344         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3345 };
3346
3347 /* l3_main_1 -> l3_main_3 */
3348 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3349         .master         = &omap44xx_l3_main_1_hwmod,
3350         .slave          = &omap44xx_l3_main_3_hwmod,
3351         .clk            = "l3_div_ck",
3352         .user           = OCP_USER_MPU,
3353 };
3354
3355 /* l3_main_2 -> l3_main_3 */
3356 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3357         .master         = &omap44xx_l3_main_2_hwmod,
3358         .slave          = &omap44xx_l3_main_3_hwmod,
3359         .clk            = "l3_div_ck",
3360         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3361 };
3362
3363 /* l4_cfg -> l3_main_3 */
3364 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3365         .master         = &omap44xx_l4_cfg_hwmod,
3366         .slave          = &omap44xx_l3_main_3_hwmod,
3367         .clk            = "l4_div_ck",
3368         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3369 };
3370
3371 /* aess -> l4_abe */
3372 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3373         .master         = &omap44xx_aess_hwmod,
3374         .slave          = &omap44xx_l4_abe_hwmod,
3375         .clk            = "ocp_abe_iclk",
3376         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3377 };
3378
3379 /* dsp -> l4_abe */
3380 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3381         .master         = &omap44xx_dsp_hwmod,
3382         .slave          = &omap44xx_l4_abe_hwmod,
3383         .clk            = "ocp_abe_iclk",
3384         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3385 };
3386
3387 /* l3_main_1 -> l4_abe */
3388 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3389         .master         = &omap44xx_l3_main_1_hwmod,
3390         .slave          = &omap44xx_l4_abe_hwmod,
3391         .clk            = "l3_div_ck",
3392         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3393 };
3394
3395 /* mpu -> l4_abe */
3396 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3397         .master         = &omap44xx_mpu_hwmod,
3398         .slave          = &omap44xx_l4_abe_hwmod,
3399         .clk            = "ocp_abe_iclk",
3400         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3401 };
3402
3403 /* l3_main_1 -> l4_cfg */
3404 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3405         .master         = &omap44xx_l3_main_1_hwmod,
3406         .slave          = &omap44xx_l4_cfg_hwmod,
3407         .clk            = "l3_div_ck",
3408         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3409 };
3410
3411 /* l3_main_2 -> l4_per */
3412 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3413         .master         = &omap44xx_l3_main_2_hwmod,
3414         .slave          = &omap44xx_l4_per_hwmod,
3415         .clk            = "l3_div_ck",
3416         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3417 };
3418
3419 /* l4_cfg -> l4_wkup */
3420 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3421         .master         = &omap44xx_l4_cfg_hwmod,
3422         .slave          = &omap44xx_l4_wkup_hwmod,
3423         .clk            = "l4_div_ck",
3424         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3425 };
3426
3427 /* mpu -> mpu_private */
3428 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3429         .master         = &omap44xx_mpu_hwmod,
3430         .slave          = &omap44xx_mpu_private_hwmod,
3431         .clk            = "l3_div_ck",
3432         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3433 };
3434
3435 /* l4_cfg -> ocp_wp_noc */
3436 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3437         .master         = &omap44xx_l4_cfg_hwmod,
3438         .slave          = &omap44xx_ocp_wp_noc_hwmod,
3439         .clk            = "l4_div_ck",
3440         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3441 };
3442
3443 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
3444         {
3445                 .name           = "dmem",
3446                 .pa_start       = 0x40180000,
3447                 .pa_end         = 0x4018ffff
3448         },
3449         {
3450                 .name           = "cmem",
3451                 .pa_start       = 0x401a0000,
3452                 .pa_end         = 0x401a1fff
3453         },
3454         {
3455                 .name           = "smem",
3456                 .pa_start       = 0x401c0000,
3457                 .pa_end         = 0x401c5fff
3458         },
3459         {
3460                 .name           = "pmem",
3461                 .pa_start       = 0x401e0000,
3462                 .pa_end         = 0x401e1fff
3463         },
3464         {
3465                 .name           = "mpu",
3466                 .pa_start       = 0x401f1000,
3467                 .pa_end         = 0x401f13ff,
3468                 .flags          = ADDR_TYPE_RT
3469         },
3470         { }
3471 };
3472
3473 /* l4_abe -> aess */
3474 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
3475         .master         = &omap44xx_l4_abe_hwmod,
3476         .slave          = &omap44xx_aess_hwmod,
3477         .clk            = "ocp_abe_iclk",
3478         .addr           = omap44xx_aess_addrs,
3479         .user           = OCP_USER_MPU,
3480 };
3481
3482 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
3483         {
3484                 .name           = "dmem_dma",
3485                 .pa_start       = 0x49080000,
3486                 .pa_end         = 0x4908ffff
3487         },
3488         {
3489                 .name           = "cmem_dma",
3490                 .pa_start       = 0x490a0000,
3491                 .pa_end         = 0x490a1fff
3492         },
3493         {
3494                 .name           = "smem_dma",
3495                 .pa_start       = 0x490c0000,
3496                 .pa_end         = 0x490c5fff
3497         },
3498         {
3499                 .name           = "pmem_dma",
3500                 .pa_start       = 0x490e0000,
3501                 .pa_end         = 0x490e1fff
3502         },
3503         {
3504                 .name           = "dma",
3505                 .pa_start       = 0x490f1000,
3506                 .pa_end         = 0x490f13ff,
3507                 .flags          = ADDR_TYPE_RT
3508         },
3509         { }
3510 };
3511
3512 /* l4_abe -> aess (dma) */
3513 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
3514         .master         = &omap44xx_l4_abe_hwmod,
3515         .slave          = &omap44xx_aess_hwmod,
3516         .clk            = "ocp_abe_iclk",
3517         .addr           = omap44xx_aess_dma_addrs,
3518         .user           = OCP_USER_SDMA,
3519 };
3520
3521 /* l3_main_2 -> c2c */
3522 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
3523         .master         = &omap44xx_l3_main_2_hwmod,
3524         .slave          = &omap44xx_c2c_hwmod,
3525         .clk            = "l3_div_ck",
3526         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3527 };
3528
3529 /* l4_wkup -> counter_32k */
3530 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
3531         .master         = &omap44xx_l4_wkup_hwmod,
3532         .slave          = &omap44xx_counter_32k_hwmod,
3533         .clk            = "l4_wkup_clk_mux_ck",
3534         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3535 };
3536
3537 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
3538         {
3539                 .pa_start       = 0x4a002000,
3540                 .pa_end         = 0x4a0027ff,
3541                 .flags          = ADDR_TYPE_RT
3542         },
3543         { }
3544 };
3545
3546 /* l4_cfg -> ctrl_module_core */
3547 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
3548         .master         = &omap44xx_l4_cfg_hwmod,
3549         .slave          = &omap44xx_ctrl_module_core_hwmod,
3550         .clk            = "l4_div_ck",
3551         .addr           = omap44xx_ctrl_module_core_addrs,
3552         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3553 };
3554
3555 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
3556         {
3557                 .pa_start       = 0x4a100000,
3558                 .pa_end         = 0x4a1007ff,
3559                 .flags          = ADDR_TYPE_RT
3560         },
3561         { }
3562 };
3563
3564 /* l4_cfg -> ctrl_module_pad_core */
3565 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
3566         .master         = &omap44xx_l4_cfg_hwmod,
3567         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
3568         .clk            = "l4_div_ck",
3569         .addr           = omap44xx_ctrl_module_pad_core_addrs,
3570         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3571 };
3572
3573 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
3574         {
3575                 .pa_start       = 0x4a30c000,
3576                 .pa_end         = 0x4a30c7ff,
3577                 .flags          = ADDR_TYPE_RT
3578         },
3579         { }
3580 };
3581
3582 /* l4_wkup -> ctrl_module_wkup */
3583 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
3584         .master         = &omap44xx_l4_wkup_hwmod,
3585         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
3586         .clk            = "l4_wkup_clk_mux_ck",
3587         .addr           = omap44xx_ctrl_module_wkup_addrs,
3588         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3589 };
3590
3591 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
3592         {
3593                 .pa_start       = 0x4a31e000,
3594                 .pa_end         = 0x4a31e7ff,
3595                 .flags          = ADDR_TYPE_RT
3596         },
3597         { }
3598 };
3599
3600 /* l4_wkup -> ctrl_module_pad_wkup */
3601 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
3602         .master         = &omap44xx_l4_wkup_hwmod,
3603         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
3604         .clk            = "l4_wkup_clk_mux_ck",
3605         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
3606         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3607 };
3608
3609 /* l3_instr -> debugss */
3610 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
3611         .master         = &omap44xx_l3_instr_hwmod,
3612         .slave          = &omap44xx_debugss_hwmod,
3613         .clk            = "l3_div_ck",
3614         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3615 };
3616
3617 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
3618         {
3619                 .pa_start       = 0x4a056000,
3620                 .pa_end         = 0x4a056fff,
3621                 .flags          = ADDR_TYPE_RT
3622         },
3623         { }
3624 };
3625
3626 /* l4_cfg -> dma_system */
3627 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
3628         .master         = &omap44xx_l4_cfg_hwmod,
3629         .slave          = &omap44xx_dma_system_hwmod,
3630         .clk            = "l4_div_ck",
3631         .addr           = omap44xx_dma_system_addrs,
3632         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3633 };
3634
3635 /* l4_abe -> dmic */
3636 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
3637         .master         = &omap44xx_l4_abe_hwmod,
3638         .slave          = &omap44xx_dmic_hwmod,
3639         .clk            = "ocp_abe_iclk",
3640         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3641 };
3642
3643 /* dsp -> iva */
3644 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
3645         .master         = &omap44xx_dsp_hwmod,
3646         .slave          = &omap44xx_iva_hwmod,
3647         .clk            = "dpll_iva_m5x2_ck",
3648         .user           = OCP_USER_DSP,
3649 };
3650
3651 /* dsp -> sl2if */
3652 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
3653         .master         = &omap44xx_dsp_hwmod,
3654         .slave          = &omap44xx_sl2if_hwmod,
3655         .clk            = "dpll_iva_m5x2_ck",
3656         .user           = OCP_USER_DSP,
3657 };
3658
3659 /* l4_cfg -> dsp */
3660 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
3661         .master         = &omap44xx_l4_cfg_hwmod,
3662         .slave          = &omap44xx_dsp_hwmod,
3663         .clk            = "l4_div_ck",
3664         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3665 };
3666
3667 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
3668         {
3669                 .pa_start       = 0x58000000,
3670                 .pa_end         = 0x5800007f,
3671                 .flags          = ADDR_TYPE_RT
3672         },
3673         { }
3674 };
3675
3676 /* l3_main_2 -> dss */
3677 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
3678         .master         = &omap44xx_l3_main_2_hwmod,
3679         .slave          = &omap44xx_dss_hwmod,
3680         .clk            = "dss_fck",
3681         .addr           = omap44xx_dss_dma_addrs,
3682         .user           = OCP_USER_SDMA,
3683 };
3684
3685 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
3686         {
3687                 .pa_start       = 0x48040000,
3688                 .pa_end         = 0x4804007f,
3689                 .flags          = ADDR_TYPE_RT
3690         },
3691         { }
3692 };
3693
3694 /* l4_per -> dss */
3695 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
3696         .master         = &omap44xx_l4_per_hwmod,
3697         .slave          = &omap44xx_dss_hwmod,
3698         .clk            = "l4_div_ck",
3699         .addr           = omap44xx_dss_addrs,
3700         .user           = OCP_USER_MPU,
3701 };
3702
3703 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
3704         {
3705                 .pa_start       = 0x58001000,
3706                 .pa_end         = 0x58001fff,
3707                 .flags          = ADDR_TYPE_RT
3708         },
3709         { }
3710 };
3711
3712 /* l3_main_2 -> dss_dispc */
3713 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
3714         .master         = &omap44xx_l3_main_2_hwmod,
3715         .slave          = &omap44xx_dss_dispc_hwmod,
3716         .clk            = "dss_fck",
3717         .addr           = omap44xx_dss_dispc_dma_addrs,
3718         .user           = OCP_USER_SDMA,
3719 };
3720
3721 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
3722         {
3723                 .pa_start       = 0x48041000,
3724                 .pa_end         = 0x48041fff,
3725                 .flags          = ADDR_TYPE_RT
3726         },
3727         { }
3728 };
3729
3730 /* l4_per -> dss_dispc */
3731 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
3732         .master         = &omap44xx_l4_per_hwmod,
3733         .slave          = &omap44xx_dss_dispc_hwmod,
3734         .clk            = "l4_div_ck",
3735         .addr           = omap44xx_dss_dispc_addrs,
3736         .user           = OCP_USER_MPU,
3737 };
3738
3739 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
3740         {
3741                 .pa_start       = 0x58004000,
3742                 .pa_end         = 0x580041ff,
3743                 .flags          = ADDR_TYPE_RT
3744         },
3745         { }
3746 };
3747
3748 /* l3_main_2 -> dss_dsi1 */
3749 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
3750         .master         = &omap44xx_l3_main_2_hwmod,
3751         .slave          = &omap44xx_dss_dsi1_hwmod,
3752         .clk            = "dss_fck",
3753         .addr           = omap44xx_dss_dsi1_dma_addrs,
3754         .user           = OCP_USER_SDMA,
3755 };
3756
3757 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
3758         {
3759                 .pa_start       = 0x48044000,
3760                 .pa_end         = 0x480441ff,
3761                 .flags          = ADDR_TYPE_RT
3762         },
3763         { }
3764 };
3765
3766 /* l4_per -> dss_dsi1 */
3767 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
3768         .master         = &omap44xx_l4_per_hwmod,
3769         .slave          = &omap44xx_dss_dsi1_hwmod,
3770         .clk            = "l4_div_ck",
3771         .addr           = omap44xx_dss_dsi1_addrs,
3772         .user           = OCP_USER_MPU,
3773 };
3774
3775 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
3776         {
3777                 .pa_start       = 0x58005000,
3778                 .pa_end         = 0x580051ff,
3779                 .flags          = ADDR_TYPE_RT
3780         },
3781         { }
3782 };
3783
3784 /* l3_main_2 -> dss_dsi2 */
3785 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
3786         .master         = &omap44xx_l3_main_2_hwmod,
3787         .slave          = &omap44xx_dss_dsi2_hwmod,
3788         .clk            = "dss_fck",
3789         .addr           = omap44xx_dss_dsi2_dma_addrs,
3790         .user           = OCP_USER_SDMA,
3791 };
3792
3793 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
3794         {
3795                 .pa_start       = 0x48045000,
3796                 .pa_end         = 0x480451ff,
3797                 .flags          = ADDR_TYPE_RT
3798         },
3799         { }
3800 };
3801
3802 /* l4_per -> dss_dsi2 */
3803 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
3804         .master         = &omap44xx_l4_per_hwmod,
3805         .slave          = &omap44xx_dss_dsi2_hwmod,
3806         .clk            = "l4_div_ck",
3807         .addr           = omap44xx_dss_dsi2_addrs,
3808         .user           = OCP_USER_MPU,
3809 };
3810
3811 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
3812         {
3813                 .pa_start       = 0x58006000,
3814                 .pa_end         = 0x58006fff,
3815                 .flags          = ADDR_TYPE_RT
3816         },
3817         { }
3818 };
3819
3820 /* l3_main_2 -> dss_hdmi */
3821 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
3822         .master         = &omap44xx_l3_main_2_hwmod,
3823         .slave          = &omap44xx_dss_hdmi_hwmod,
3824         .clk            = "dss_fck",
3825         .addr           = omap44xx_dss_hdmi_dma_addrs,
3826         .user           = OCP_USER_SDMA,
3827 };
3828
3829 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
3830         {
3831                 .pa_start       = 0x48046000,
3832                 .pa_end         = 0x48046fff,
3833                 .flags          = ADDR_TYPE_RT
3834         },
3835         { }
3836 };
3837
3838 /* l4_per -> dss_hdmi */
3839 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
3840         .master         = &omap44xx_l4_per_hwmod,
3841         .slave          = &omap44xx_dss_hdmi_hwmod,
3842         .clk            = "l4_div_ck",
3843         .addr           = omap44xx_dss_hdmi_addrs,
3844         .user           = OCP_USER_MPU,
3845 };
3846
3847 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
3848         {
3849                 .pa_start       = 0x58002000,
3850                 .pa_end         = 0x580020ff,
3851                 .flags          = ADDR_TYPE_RT
3852         },
3853         { }
3854 };
3855
3856 /* l3_main_2 -> dss_rfbi */
3857 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
3858         .master         = &omap44xx_l3_main_2_hwmod,
3859         .slave          = &omap44xx_dss_rfbi_hwmod,
3860         .clk            = "dss_fck",
3861         .addr           = omap44xx_dss_rfbi_dma_addrs,
3862         .user           = OCP_USER_SDMA,
3863 };
3864
3865 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
3866         {
3867                 .pa_start       = 0x48042000,
3868                 .pa_end         = 0x480420ff,
3869                 .flags          = ADDR_TYPE_RT
3870         },
3871         { }
3872 };
3873
3874 /* l4_per -> dss_rfbi */
3875 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
3876         .master         = &omap44xx_l4_per_hwmod,
3877         .slave          = &omap44xx_dss_rfbi_hwmod,
3878         .clk            = "l4_div_ck",
3879         .addr           = omap44xx_dss_rfbi_addrs,
3880         .user           = OCP_USER_MPU,
3881 };
3882
3883 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
3884         {
3885                 .pa_start       = 0x58003000,
3886                 .pa_end         = 0x580030ff,
3887                 .flags          = ADDR_TYPE_RT
3888         },
3889         { }
3890 };
3891
3892 /* l3_main_2 -> dss_venc */
3893 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
3894         .master         = &omap44xx_l3_main_2_hwmod,
3895         .slave          = &omap44xx_dss_venc_hwmod,
3896         .clk            = "dss_fck",
3897         .addr           = omap44xx_dss_venc_dma_addrs,
3898         .user           = OCP_USER_SDMA,
3899 };
3900
3901 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
3902         {
3903                 .pa_start       = 0x48043000,
3904                 .pa_end         = 0x480430ff,
3905                 .flags          = ADDR_TYPE_RT
3906         },
3907         { }
3908 };
3909
3910 /* l4_per -> dss_venc */
3911 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
3912         .master         = &omap44xx_l4_per_hwmod,
3913         .slave          = &omap44xx_dss_venc_hwmod,
3914         .clk            = "l4_div_ck",
3915         .addr           = omap44xx_dss_venc_addrs,
3916         .user           = OCP_USER_MPU,
3917 };
3918
3919 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
3920         {
3921                 .pa_start       = 0x48078000,
3922                 .pa_end         = 0x48078fff,
3923                 .flags          = ADDR_TYPE_RT
3924         },
3925         { }
3926 };
3927
3928 /* l4_per -> elm */
3929 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
3930         .master         = &omap44xx_l4_per_hwmod,
3931         .slave          = &omap44xx_elm_hwmod,
3932         .clk            = "l4_div_ck",
3933         .addr           = omap44xx_elm_addrs,
3934         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3935 };
3936
3937 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
3938         {
3939                 .pa_start       = 0x4a10a000,
3940                 .pa_end         = 0x4a10a1ff,
3941                 .flags          = ADDR_TYPE_RT
3942         },
3943         { }
3944 };
3945
3946 /* l4_cfg -> fdif */
3947 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
3948         .master         = &omap44xx_l4_cfg_hwmod,
3949         .slave          = &omap44xx_fdif_hwmod,
3950         .clk            = "l4_div_ck",
3951         .addr           = omap44xx_fdif_addrs,
3952         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3953 };
3954
3955 /* l4_wkup -> gpio1 */
3956 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
3957         .master         = &omap44xx_l4_wkup_hwmod,
3958         .slave          = &omap44xx_gpio1_hwmod,
3959         .clk            = "l4_wkup_clk_mux_ck",
3960         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3961 };
3962
3963 /* l4_per -> gpio2 */
3964 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
3965         .master         = &omap44xx_l4_per_hwmod,
3966         .slave          = &omap44xx_gpio2_hwmod,
3967         .clk            = "l4_div_ck",
3968         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3969 };
3970
3971 /* l4_per -> gpio3 */
3972 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
3973         .master         = &omap44xx_l4_per_hwmod,
3974         .slave          = &omap44xx_gpio3_hwmod,
3975         .clk            = "l4_div_ck",
3976         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3977 };
3978
3979 /* l4_per -> gpio4 */
3980 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
3981         .master         = &omap44xx_l4_per_hwmod,
3982         .slave          = &omap44xx_gpio4_hwmod,
3983         .clk            = "l4_div_ck",
3984         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3985 };
3986
3987 /* l4_per -> gpio5 */
3988 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
3989         .master         = &omap44xx_l4_per_hwmod,
3990         .slave          = &omap44xx_gpio5_hwmod,
3991         .clk            = "l4_div_ck",
3992         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3993 };
3994
3995 /* l4_per -> gpio6 */
3996 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
3997         .master         = &omap44xx_l4_per_hwmod,
3998         .slave          = &omap44xx_gpio6_hwmod,
3999         .clk            = "l4_div_ck",
4000         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4001 };
4002
4003 /* l3_main_2 -> gpmc */
4004 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4005         .master         = &omap44xx_l3_main_2_hwmod,
4006         .slave          = &omap44xx_gpmc_hwmod,
4007         .clk            = "l3_div_ck",
4008         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4009 };
4010
4011 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4012         {
4013                 .pa_start       = 0x56000000,
4014                 .pa_end         = 0x5600ffff,
4015                 .flags          = ADDR_TYPE_RT
4016         },
4017         { }
4018 };
4019
4020 /* l3_main_2 -> gpu */
4021 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4022         .master         = &omap44xx_l3_main_2_hwmod,
4023         .slave          = &omap44xx_gpu_hwmod,
4024         .clk            = "l3_div_ck",
4025         .addr           = omap44xx_gpu_addrs,
4026         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4027 };
4028
4029 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4030         {
4031                 .pa_start       = 0x480b2000,
4032                 .pa_end         = 0x480b201f,
4033                 .flags          = ADDR_TYPE_RT
4034         },
4035         { }
4036 };
4037
4038 /* l4_per -> hdq1w */
4039 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4040         .master         = &omap44xx_l4_per_hwmod,
4041         .slave          = &omap44xx_hdq1w_hwmod,
4042         .clk            = "l4_div_ck",
4043         .addr           = omap44xx_hdq1w_addrs,
4044         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4045 };
4046
4047 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4048         {
4049                 .pa_start       = 0x4a058000,
4050                 .pa_end         = 0x4a05bfff,
4051                 .flags          = ADDR_TYPE_RT
4052         },
4053         { }
4054 };
4055
4056 /* l4_cfg -> hsi */
4057 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4058         .master         = &omap44xx_l4_cfg_hwmod,
4059         .slave          = &omap44xx_hsi_hwmod,
4060         .clk            = "l4_div_ck",
4061         .addr           = omap44xx_hsi_addrs,
4062         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4063 };
4064
4065 /* l4_per -> i2c1 */
4066 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4067         .master         = &omap44xx_l4_per_hwmod,
4068         .slave          = &omap44xx_i2c1_hwmod,
4069         .clk            = "l4_div_ck",
4070         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4071 };
4072
4073 /* l4_per -> i2c2 */
4074 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4075         .master         = &omap44xx_l4_per_hwmod,
4076         .slave          = &omap44xx_i2c2_hwmod,
4077         .clk            = "l4_div_ck",
4078         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4079 };
4080
4081 /* l4_per -> i2c3 */
4082 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4083         .master         = &omap44xx_l4_per_hwmod,
4084         .slave          = &omap44xx_i2c3_hwmod,
4085         .clk            = "l4_div_ck",
4086         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4087 };
4088
4089 /* l4_per -> i2c4 */
4090 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4091         .master         = &omap44xx_l4_per_hwmod,
4092         .slave          = &omap44xx_i2c4_hwmod,
4093         .clk            = "l4_div_ck",
4094         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4095 };
4096
4097 /* l3_main_2 -> ipu */
4098 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4099         .master         = &omap44xx_l3_main_2_hwmod,
4100         .slave          = &omap44xx_ipu_hwmod,
4101         .clk            = "l3_div_ck",
4102         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4103 };
4104
4105 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4106         {
4107                 .pa_start       = 0x52000000,
4108                 .pa_end         = 0x520000ff,
4109                 .flags          = ADDR_TYPE_RT
4110         },
4111         { }
4112 };
4113
4114 /* l3_main_2 -> iss */
4115 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4116         .master         = &omap44xx_l3_main_2_hwmod,
4117         .slave          = &omap44xx_iss_hwmod,
4118         .clk            = "l3_div_ck",
4119         .addr           = omap44xx_iss_addrs,
4120         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4121 };
4122
4123 /* iva -> sl2if */
4124 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
4125         .master         = &omap44xx_iva_hwmod,
4126         .slave          = &omap44xx_sl2if_hwmod,
4127         .clk            = "dpll_iva_m5x2_ck",
4128         .user           = OCP_USER_IVA,
4129 };
4130
4131 /* l3_main_2 -> iva */
4132 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4133         .master         = &omap44xx_l3_main_2_hwmod,
4134         .slave          = &omap44xx_iva_hwmod,
4135         .clk            = "l3_div_ck",
4136         .user           = OCP_USER_MPU,
4137 };
4138
4139 /* l4_wkup -> kbd */
4140 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4141         .master         = &omap44xx_l4_wkup_hwmod,
4142         .slave          = &omap44xx_kbd_hwmod,
4143         .clk            = "l4_wkup_clk_mux_ck",
4144         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4145 };
4146
4147 /* l4_cfg -> mailbox */
4148 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4149         .master         = &omap44xx_l4_cfg_hwmod,
4150         .slave          = &omap44xx_mailbox_hwmod,
4151         .clk            = "l4_div_ck",
4152         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4153 };
4154
4155 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4156         {
4157                 .pa_start       = 0x40128000,
4158                 .pa_end         = 0x401283ff,
4159                 .flags          = ADDR_TYPE_RT
4160         },
4161         { }
4162 };
4163
4164 /* l4_abe -> mcasp */
4165 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4166         .master         = &omap44xx_l4_abe_hwmod,
4167         .slave          = &omap44xx_mcasp_hwmod,
4168         .clk            = "ocp_abe_iclk",
4169         .addr           = omap44xx_mcasp_addrs,
4170         .user           = OCP_USER_MPU,
4171 };
4172
4173 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4174         {
4175                 .pa_start       = 0x49028000,
4176                 .pa_end         = 0x490283ff,
4177                 .flags          = ADDR_TYPE_RT
4178         },
4179         { }
4180 };
4181
4182 /* l4_abe -> mcasp (dma) */
4183 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4184         .master         = &omap44xx_l4_abe_hwmod,
4185         .slave          = &omap44xx_mcasp_hwmod,
4186         .clk            = "ocp_abe_iclk",
4187         .addr           = omap44xx_mcasp_dma_addrs,
4188         .user           = OCP_USER_SDMA,
4189 };
4190
4191 /* l4_abe -> mcbsp1 */
4192 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4193         .master         = &omap44xx_l4_abe_hwmod,
4194         .slave          = &omap44xx_mcbsp1_hwmod,
4195         .clk            = "ocp_abe_iclk",
4196         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4197 };
4198
4199 /* l4_abe -> mcbsp2 */
4200 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4201         .master         = &omap44xx_l4_abe_hwmod,
4202         .slave          = &omap44xx_mcbsp2_hwmod,
4203         .clk            = "ocp_abe_iclk",
4204         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4205 };
4206
4207 /* l4_abe -> mcbsp3 */
4208 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
4209         .master         = &omap44xx_l4_abe_hwmod,
4210         .slave          = &omap44xx_mcbsp3_hwmod,
4211         .clk            = "ocp_abe_iclk",
4212         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4213 };
4214
4215 /* l4_per -> mcbsp4 */
4216 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
4217         .master         = &omap44xx_l4_per_hwmod,
4218         .slave          = &omap44xx_mcbsp4_hwmod,
4219         .clk            = "l4_div_ck",
4220         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4221 };
4222
4223 /* l4_abe -> mcpdm */
4224 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
4225         .master         = &omap44xx_l4_abe_hwmod,
4226         .slave          = &omap44xx_mcpdm_hwmod,
4227         .clk            = "ocp_abe_iclk",
4228         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4229 };
4230
4231 /* l4_per -> mcspi1 */
4232 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
4233         .master         = &omap44xx_l4_per_hwmod,
4234         .slave          = &omap44xx_mcspi1_hwmod,
4235         .clk            = "l4_div_ck",
4236         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4237 };
4238
4239 /* l4_per -> mcspi2 */
4240 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
4241         .master         = &omap44xx_l4_per_hwmod,
4242         .slave          = &omap44xx_mcspi2_hwmod,
4243         .clk            = "l4_div_ck",
4244         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4245 };
4246
4247 /* l4_per -> mcspi3 */
4248 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
4249         .master         = &omap44xx_l4_per_hwmod,
4250         .slave          = &omap44xx_mcspi3_hwmod,
4251         .clk            = "l4_div_ck",
4252         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4253 };
4254
4255 /* l4_per -> mcspi4 */
4256 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
4257         .master         = &omap44xx_l4_per_hwmod,
4258         .slave          = &omap44xx_mcspi4_hwmod,
4259         .clk            = "l4_div_ck",
4260         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4261 };
4262
4263 /* l4_per -> mmc1 */
4264 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
4265         .master         = &omap44xx_l4_per_hwmod,
4266         .slave          = &omap44xx_mmc1_hwmod,
4267         .clk            = "l4_div_ck",
4268         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4269 };
4270
4271 /* l4_per -> mmc2 */
4272 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
4273         .master         = &omap44xx_l4_per_hwmod,
4274         .slave          = &omap44xx_mmc2_hwmod,
4275         .clk            = "l4_div_ck",
4276         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4277 };
4278
4279 /* l4_per -> mmc3 */
4280 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
4281         .master         = &omap44xx_l4_per_hwmod,
4282         .slave          = &omap44xx_mmc3_hwmod,
4283         .clk            = "l4_div_ck",
4284         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4285 };
4286
4287 /* l4_per -> mmc4 */
4288 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
4289         .master         = &omap44xx_l4_per_hwmod,
4290         .slave          = &omap44xx_mmc4_hwmod,
4291         .clk            = "l4_div_ck",
4292         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4293 };
4294
4295 /* l4_per -> mmc5 */
4296 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
4297         .master         = &omap44xx_l4_per_hwmod,
4298         .slave          = &omap44xx_mmc5_hwmod,
4299         .clk            = "l4_div_ck",
4300         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4301 };
4302
4303 /* l3_main_2 -> ocmc_ram */
4304 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
4305         .master         = &omap44xx_l3_main_2_hwmod,
4306         .slave          = &omap44xx_ocmc_ram_hwmod,
4307         .clk            = "l3_div_ck",
4308         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4309 };
4310
4311 /* l4_cfg -> ocp2scp_usb_phy */
4312 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
4313         .master         = &omap44xx_l4_cfg_hwmod,
4314         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
4315         .clk            = "l4_div_ck",
4316         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4317 };
4318
4319 /* mpu_private -> prcm_mpu */
4320 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
4321         .master         = &omap44xx_mpu_private_hwmod,
4322         .slave          = &omap44xx_prcm_mpu_hwmod,
4323         .clk            = "l3_div_ck",
4324         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4325 };
4326
4327 /* l4_wkup -> cm_core_aon */
4328 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
4329         .master         = &omap44xx_l4_wkup_hwmod,
4330         .slave          = &omap44xx_cm_core_aon_hwmod,
4331         .clk            = "l4_wkup_clk_mux_ck",
4332         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4333 };
4334
4335 /* l4_cfg -> cm_core */
4336 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
4337         .master         = &omap44xx_l4_cfg_hwmod,
4338         .slave          = &omap44xx_cm_core_hwmod,
4339         .clk            = "l4_div_ck",
4340         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4341 };
4342
4343 /* l4_wkup -> prm */
4344 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
4345         .master         = &omap44xx_l4_wkup_hwmod,
4346         .slave          = &omap44xx_prm_hwmod,
4347         .clk            = "l4_wkup_clk_mux_ck",
4348         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4349 };
4350
4351 /* l4_wkup -> scrm */
4352 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
4353         .master         = &omap44xx_l4_wkup_hwmod,
4354         .slave          = &omap44xx_scrm_hwmod,
4355         .clk            = "l4_wkup_clk_mux_ck",
4356         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4357 };
4358
4359 /* l3_main_2 -> sl2if */
4360 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
4361         .master         = &omap44xx_l3_main_2_hwmod,
4362         .slave          = &omap44xx_sl2if_hwmod,
4363         .clk            = "l3_div_ck",
4364         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4365 };
4366
4367 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
4368         {
4369                 .pa_start       = 0x4012c000,
4370                 .pa_end         = 0x4012c3ff,
4371                 .flags          = ADDR_TYPE_RT
4372         },
4373         { }
4374 };
4375
4376 /* l4_abe -> slimbus1 */
4377 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
4378         .master         = &omap44xx_l4_abe_hwmod,
4379         .slave          = &omap44xx_slimbus1_hwmod,
4380         .clk            = "ocp_abe_iclk",
4381         .addr           = omap44xx_slimbus1_addrs,
4382         .user           = OCP_USER_MPU,
4383 };
4384
4385 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
4386         {
4387                 .pa_start       = 0x4902c000,
4388                 .pa_end         = 0x4902c3ff,
4389                 .flags          = ADDR_TYPE_RT
4390         },
4391         { }
4392 };
4393
4394 /* l4_abe -> slimbus1 (dma) */
4395 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
4396         .master         = &omap44xx_l4_abe_hwmod,
4397         .slave          = &omap44xx_slimbus1_hwmod,
4398         .clk            = "ocp_abe_iclk",
4399         .addr           = omap44xx_slimbus1_dma_addrs,
4400         .user           = OCP_USER_SDMA,
4401 };
4402
4403 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
4404         {
4405                 .pa_start       = 0x48076000,
4406                 .pa_end         = 0x480763ff,
4407                 .flags          = ADDR_TYPE_RT
4408         },
4409         { }
4410 };
4411
4412 /* l4_per -> slimbus2 */
4413 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
4414         .master         = &omap44xx_l4_per_hwmod,
4415         .slave          = &omap44xx_slimbus2_hwmod,
4416         .clk            = "l4_div_ck",
4417         .addr           = omap44xx_slimbus2_addrs,
4418         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4419 };
4420
4421 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
4422         {
4423                 .pa_start       = 0x4a0dd000,
4424                 .pa_end         = 0x4a0dd03f,
4425                 .flags          = ADDR_TYPE_RT
4426         },
4427         { }
4428 };
4429
4430 /* l4_cfg -> smartreflex_core */
4431 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
4432         .master         = &omap44xx_l4_cfg_hwmod,
4433         .slave          = &omap44xx_smartreflex_core_hwmod,
4434         .clk            = "l4_div_ck",
4435         .addr           = omap44xx_smartreflex_core_addrs,
4436         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4437 };
4438
4439 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4440         {
4441                 .pa_start       = 0x4a0db000,
4442                 .pa_end         = 0x4a0db03f,
4443                 .flags          = ADDR_TYPE_RT
4444         },
4445         { }
4446 };
4447
4448 /* l4_cfg -> smartreflex_iva */
4449 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4450         .master         = &omap44xx_l4_cfg_hwmod,
4451         .slave          = &omap44xx_smartreflex_iva_hwmod,
4452         .clk            = "l4_div_ck",
4453         .addr           = omap44xx_smartreflex_iva_addrs,
4454         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4455 };
4456
4457 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4458         {
4459                 .pa_start       = 0x4a0d9000,
4460                 .pa_end         = 0x4a0d903f,
4461                 .flags          = ADDR_TYPE_RT
4462         },
4463         { }
4464 };
4465
4466 /* l4_cfg -> smartreflex_mpu */
4467 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4468         .master         = &omap44xx_l4_cfg_hwmod,
4469         .slave          = &omap44xx_smartreflex_mpu_hwmod,
4470         .clk            = "l4_div_ck",
4471         .addr           = omap44xx_smartreflex_mpu_addrs,
4472         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4473 };
4474
4475 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4476         {
4477                 .pa_start       = 0x4a0f6000,
4478                 .pa_end         = 0x4a0f6fff,
4479                 .flags          = ADDR_TYPE_RT
4480         },
4481         { }
4482 };
4483
4484 /* l4_cfg -> spinlock */
4485 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4486         .master         = &omap44xx_l4_cfg_hwmod,
4487         .slave          = &omap44xx_spinlock_hwmod,
4488         .clk            = "l4_div_ck",
4489         .addr           = omap44xx_spinlock_addrs,
4490         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4491 };
4492
4493 /* l4_wkup -> timer1 */
4494 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4495         .master         = &omap44xx_l4_wkup_hwmod,
4496         .slave          = &omap44xx_timer1_hwmod,
4497         .clk            = "l4_wkup_clk_mux_ck",
4498         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4499 };
4500
4501 /* l4_per -> timer2 */
4502 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4503         .master         = &omap44xx_l4_per_hwmod,
4504         .slave          = &omap44xx_timer2_hwmod,
4505         .clk            = "l4_div_ck",
4506         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4507 };
4508
4509 /* l4_per -> timer3 */
4510 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4511         .master         = &omap44xx_l4_per_hwmod,
4512         .slave          = &omap44xx_timer3_hwmod,
4513         .clk            = "l4_div_ck",
4514         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4515 };
4516
4517 /* l4_per -> timer4 */
4518 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4519         .master         = &omap44xx_l4_per_hwmod,
4520         .slave          = &omap44xx_timer4_hwmod,
4521         .clk            = "l4_div_ck",
4522         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4523 };
4524
4525 /* l4_abe -> timer5 */
4526 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4527         .master         = &omap44xx_l4_abe_hwmod,
4528         .slave          = &omap44xx_timer5_hwmod,
4529         .clk            = "ocp_abe_iclk",
4530         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4531 };
4532
4533 /* l4_abe -> timer6 */
4534 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4535         .master         = &omap44xx_l4_abe_hwmod,
4536         .slave          = &omap44xx_timer6_hwmod,
4537         .clk            = "ocp_abe_iclk",
4538         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4539 };
4540
4541 /* l4_abe -> timer7 */
4542 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4543         .master         = &omap44xx_l4_abe_hwmod,
4544         .slave          = &omap44xx_timer7_hwmod,
4545         .clk            = "ocp_abe_iclk",
4546         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4547 };
4548
4549 /* l4_abe -> timer8 */
4550 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4551         .master         = &omap44xx_l4_abe_hwmod,
4552         .slave          = &omap44xx_timer8_hwmod,
4553         .clk            = "ocp_abe_iclk",
4554         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4555 };
4556
4557 /* l4_per -> timer9 */
4558 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4559         .master         = &omap44xx_l4_per_hwmod,
4560         .slave          = &omap44xx_timer9_hwmod,
4561         .clk            = "l4_div_ck",
4562         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4563 };
4564
4565 /* l4_per -> timer10 */
4566 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4567         .master         = &omap44xx_l4_per_hwmod,
4568         .slave          = &omap44xx_timer10_hwmod,
4569         .clk            = "l4_div_ck",
4570         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4571 };
4572
4573 /* l4_per -> timer11 */
4574 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4575         .master         = &omap44xx_l4_per_hwmod,
4576         .slave          = &omap44xx_timer11_hwmod,
4577         .clk            = "l4_div_ck",
4578         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4579 };
4580
4581 /* l4_per -> uart1 */
4582 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4583         .master         = &omap44xx_l4_per_hwmod,
4584         .slave          = &omap44xx_uart1_hwmod,
4585         .clk            = "l4_div_ck",
4586         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4587 };
4588
4589 /* l4_per -> uart2 */
4590 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4591         .master         = &omap44xx_l4_per_hwmod,
4592         .slave          = &omap44xx_uart2_hwmod,
4593         .clk            = "l4_div_ck",
4594         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4595 };
4596
4597 /* l4_per -> uart3 */
4598 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4599         .master         = &omap44xx_l4_per_hwmod,
4600         .slave          = &omap44xx_uart3_hwmod,
4601         .clk            = "l4_div_ck",
4602         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4603 };
4604
4605 /* l4_per -> uart4 */
4606 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4607         .master         = &omap44xx_l4_per_hwmod,
4608         .slave          = &omap44xx_uart4_hwmod,
4609         .clk            = "l4_div_ck",
4610         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4611 };
4612
4613 /* l4_cfg -> usb_host_fs */
4614 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
4615         .master         = &omap44xx_l4_cfg_hwmod,
4616         .slave          = &omap44xx_usb_host_fs_hwmod,
4617         .clk            = "l4_div_ck",
4618         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4619 };
4620
4621 /* l4_cfg -> usb_host_hs */
4622 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
4623         .master         = &omap44xx_l4_cfg_hwmod,
4624         .slave          = &omap44xx_usb_host_hs_hwmod,
4625         .clk            = "l4_div_ck",
4626         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4627 };
4628
4629 /* l4_cfg -> usb_otg_hs */
4630 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4631         .master         = &omap44xx_l4_cfg_hwmod,
4632         .slave          = &omap44xx_usb_otg_hs_hwmod,
4633         .clk            = "l4_div_ck",
4634         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4635 };
4636
4637 /* l4_cfg -> usb_tll_hs */
4638 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
4639         .master         = &omap44xx_l4_cfg_hwmod,
4640         .slave          = &omap44xx_usb_tll_hs_hwmod,
4641         .clk            = "l4_div_ck",
4642         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4643 };
4644
4645 /* l4_wkup -> wd_timer2 */
4646 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4647         .master         = &omap44xx_l4_wkup_hwmod,
4648         .slave          = &omap44xx_wd_timer2_hwmod,
4649         .clk            = "l4_wkup_clk_mux_ck",
4650         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4651 };
4652
4653 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4654         {
4655                 .pa_start       = 0x40130000,
4656                 .pa_end         = 0x4013007f,
4657                 .flags          = ADDR_TYPE_RT
4658         },
4659         { }
4660 };
4661
4662 /* l4_abe -> wd_timer3 */
4663 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4664         .master         = &omap44xx_l4_abe_hwmod,
4665         .slave          = &omap44xx_wd_timer3_hwmod,
4666         .clk            = "ocp_abe_iclk",
4667         .addr           = omap44xx_wd_timer3_addrs,
4668         .user           = OCP_USER_MPU,
4669 };
4670
4671 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4672         {
4673                 .pa_start       = 0x49030000,
4674                 .pa_end         = 0x4903007f,
4675                 .flags          = ADDR_TYPE_RT
4676         },
4677         { }
4678 };
4679
4680 /* l4_abe -> wd_timer3 (dma) */
4681 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4682         .master         = &omap44xx_l4_abe_hwmod,
4683         .slave          = &omap44xx_wd_timer3_hwmod,
4684         .clk            = "ocp_abe_iclk",
4685         .addr           = omap44xx_wd_timer3_dma_addrs,
4686         .user           = OCP_USER_SDMA,
4687 };
4688
4689 /* mpu -> emif1 */
4690 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
4691         .master         = &omap44xx_mpu_hwmod,
4692         .slave          = &omap44xx_emif1_hwmod,
4693         .clk            = "l3_div_ck",
4694         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4695 };
4696
4697 /* mpu -> emif2 */
4698 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
4699         .master         = &omap44xx_mpu_hwmod,
4700         .slave          = &omap44xx_emif2_hwmod,
4701         .clk            = "l3_div_ck",
4702         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4703 };
4704
4705 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4706         &omap44xx_l3_main_1__dmm,
4707         &omap44xx_mpu__dmm,
4708         &omap44xx_iva__l3_instr,
4709         &omap44xx_l3_main_3__l3_instr,
4710         &omap44xx_ocp_wp_noc__l3_instr,
4711         &omap44xx_dsp__l3_main_1,
4712         &omap44xx_dss__l3_main_1,
4713         &omap44xx_l3_main_2__l3_main_1,
4714         &omap44xx_l4_cfg__l3_main_1,
4715         &omap44xx_mmc1__l3_main_1,
4716         &omap44xx_mmc2__l3_main_1,
4717         &omap44xx_mpu__l3_main_1,
4718         &omap44xx_debugss__l3_main_2,
4719         &omap44xx_dma_system__l3_main_2,
4720         &omap44xx_fdif__l3_main_2,
4721         &omap44xx_gpu__l3_main_2,
4722         &omap44xx_hsi__l3_main_2,
4723         &omap44xx_ipu__l3_main_2,
4724         &omap44xx_iss__l3_main_2,
4725         &omap44xx_iva__l3_main_2,
4726         &omap44xx_l3_main_1__l3_main_2,
4727         &omap44xx_l4_cfg__l3_main_2,
4728         /* &omap44xx_usb_host_fs__l3_main_2, */
4729         &omap44xx_usb_host_hs__l3_main_2,
4730         &omap44xx_usb_otg_hs__l3_main_2,
4731         &omap44xx_l3_main_1__l3_main_3,
4732         &omap44xx_l3_main_2__l3_main_3,
4733         &omap44xx_l4_cfg__l3_main_3,
4734         &omap44xx_aess__l4_abe,
4735         &omap44xx_dsp__l4_abe,
4736         &omap44xx_l3_main_1__l4_abe,
4737         &omap44xx_mpu__l4_abe,
4738         &omap44xx_l3_main_1__l4_cfg,
4739         &omap44xx_l3_main_2__l4_per,
4740         &omap44xx_l4_cfg__l4_wkup,
4741         &omap44xx_mpu__mpu_private,
4742         &omap44xx_l4_cfg__ocp_wp_noc,
4743         &omap44xx_l4_abe__aess,
4744         &omap44xx_l4_abe__aess_dma,
4745         &omap44xx_l3_main_2__c2c,
4746         &omap44xx_l4_wkup__counter_32k,
4747         &omap44xx_l4_cfg__ctrl_module_core,
4748         &omap44xx_l4_cfg__ctrl_module_pad_core,
4749         &omap44xx_l4_wkup__ctrl_module_wkup,
4750         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
4751         &omap44xx_l3_instr__debugss,
4752         &omap44xx_l4_cfg__dma_system,
4753         &omap44xx_l4_abe__dmic,
4754         &omap44xx_dsp__iva,
4755         /* &omap44xx_dsp__sl2if, */
4756         &omap44xx_l4_cfg__dsp,
4757         &omap44xx_l3_main_2__dss,
4758         &omap44xx_l4_per__dss,
4759         &omap44xx_l3_main_2__dss_dispc,
4760         &omap44xx_l4_per__dss_dispc,
4761         &omap44xx_l3_main_2__dss_dsi1,
4762         &omap44xx_l4_per__dss_dsi1,
4763         &omap44xx_l3_main_2__dss_dsi2,
4764         &omap44xx_l4_per__dss_dsi2,
4765         &omap44xx_l3_main_2__dss_hdmi,
4766         &omap44xx_l4_per__dss_hdmi,
4767         &omap44xx_l3_main_2__dss_rfbi,
4768         &omap44xx_l4_per__dss_rfbi,
4769         &omap44xx_l3_main_2__dss_venc,
4770         &omap44xx_l4_per__dss_venc,
4771         &omap44xx_l4_per__elm,
4772         &omap44xx_l4_cfg__fdif,
4773         &omap44xx_l4_wkup__gpio1,
4774         &omap44xx_l4_per__gpio2,
4775         &omap44xx_l4_per__gpio3,
4776         &omap44xx_l4_per__gpio4,
4777         &omap44xx_l4_per__gpio5,
4778         &omap44xx_l4_per__gpio6,
4779         &omap44xx_l3_main_2__gpmc,
4780         &omap44xx_l3_main_2__gpu,
4781         &omap44xx_l4_per__hdq1w,
4782         &omap44xx_l4_cfg__hsi,
4783         &omap44xx_l4_per__i2c1,
4784         &omap44xx_l4_per__i2c2,
4785         &omap44xx_l4_per__i2c3,
4786         &omap44xx_l4_per__i2c4,
4787         &omap44xx_l3_main_2__ipu,
4788         &omap44xx_l3_main_2__iss,
4789         /* &omap44xx_iva__sl2if, */
4790         &omap44xx_l3_main_2__iva,
4791         &omap44xx_l4_wkup__kbd,
4792         &omap44xx_l4_cfg__mailbox,
4793         &omap44xx_l4_abe__mcasp,
4794         &omap44xx_l4_abe__mcasp_dma,
4795         &omap44xx_l4_abe__mcbsp1,
4796         &omap44xx_l4_abe__mcbsp2,
4797         &omap44xx_l4_abe__mcbsp3,
4798         &omap44xx_l4_per__mcbsp4,
4799         &omap44xx_l4_abe__mcpdm,
4800         &omap44xx_l4_per__mcspi1,
4801         &omap44xx_l4_per__mcspi2,
4802         &omap44xx_l4_per__mcspi3,
4803         &omap44xx_l4_per__mcspi4,
4804         &omap44xx_l4_per__mmc1,
4805         &omap44xx_l4_per__mmc2,
4806         &omap44xx_l4_per__mmc3,
4807         &omap44xx_l4_per__mmc4,
4808         &omap44xx_l4_per__mmc5,
4809         &omap44xx_l3_main_2__mmu_ipu,
4810         &omap44xx_l4_cfg__mmu_dsp,
4811         &omap44xx_l3_main_2__ocmc_ram,
4812         &omap44xx_l4_cfg__ocp2scp_usb_phy,
4813         &omap44xx_mpu_private__prcm_mpu,
4814         &omap44xx_l4_wkup__cm_core_aon,
4815         &omap44xx_l4_cfg__cm_core,
4816         &omap44xx_l4_wkup__prm,
4817         &omap44xx_l4_wkup__scrm,
4818         /* &omap44xx_l3_main_2__sl2if, */
4819         &omap44xx_l4_abe__slimbus1,
4820         &omap44xx_l4_abe__slimbus1_dma,
4821         &omap44xx_l4_per__slimbus2,
4822         &omap44xx_l4_cfg__smartreflex_core,
4823         &omap44xx_l4_cfg__smartreflex_iva,
4824         &omap44xx_l4_cfg__smartreflex_mpu,
4825         &omap44xx_l4_cfg__spinlock,
4826         &omap44xx_l4_wkup__timer1,
4827         &omap44xx_l4_per__timer2,
4828         &omap44xx_l4_per__timer3,
4829         &omap44xx_l4_per__timer4,
4830         &omap44xx_l4_abe__timer5,
4831         &omap44xx_l4_abe__timer6,
4832         &omap44xx_l4_abe__timer7,
4833         &omap44xx_l4_abe__timer8,
4834         &omap44xx_l4_per__timer9,
4835         &omap44xx_l4_per__timer10,
4836         &omap44xx_l4_per__timer11,
4837         &omap44xx_l4_per__uart1,
4838         &omap44xx_l4_per__uart2,
4839         &omap44xx_l4_per__uart3,
4840         &omap44xx_l4_per__uart4,
4841         /* &omap44xx_l4_cfg__usb_host_fs, */
4842         &omap44xx_l4_cfg__usb_host_hs,
4843         &omap44xx_l4_cfg__usb_otg_hs,
4844         &omap44xx_l4_cfg__usb_tll_hs,
4845         &omap44xx_l4_wkup__wd_timer2,
4846         &omap44xx_l4_abe__wd_timer3,
4847         &omap44xx_l4_abe__wd_timer3_dma,
4848         &omap44xx_mpu__emif1,
4849         &omap44xx_mpu__emif2,
4850         NULL,
4851 };
4852
4853 int __init omap44xx_hwmod_init(void)
4854 {
4855         omap_hwmod_init();
4856         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
4857 }
4858