arch/arm/mach-omap2/omap_hwmod_54xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP54xx chips
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley
   7  * Benoit Cousson
   8  *
   9  * This file is automatically generated from the OMAP hardware databases.
  10  * We respectfully ask that any modifications to this file be coordinated
  11  * with the public linux-omap@vger.kernel.org mailing list and the
  12  * authors above to ensure that the autogeneration scripts are kept
  13  * up-to-date with the file contents.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/platform_data/gpio-omap.h>
  22 #include <linux/platform_data/hsmmc-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/i2c-omap.h>
  25
  26 #include <linux/omap-dma.h>
  27 #include <linux/platform_data/spi-omap2-mcspi.h>
  28 #include <linux/platform_data/asoc-ti-mcbsp.h>
  29 #include <plat/dmtimer.h>
  30
  31 #include "omap_hwmod.h"
  32 #include "omap_hwmod_common_data.h"
  33 #include "cm1_54xx.h"
  34 #include "cm2_54xx.h"
  35 #include "prm54xx.h"
  36 #include "i2c.h"
  37 #include "wd_timer.h"
  38
  39 /* Base offset for all OMAP5 interrupts external to MPUSS */
  40 #define OMAP54XX_IRQ_GIC_START  32
  41
  42 /* Base offset for all OMAP5 dma requests */
  43 #define OMAP54XX_DMA_REQ_START  1
  44
  45
  46 /*
  47  * IP blocks
  48  */
  49
  50 /*
  51  * 'dmm' class
  52  * instance(s): dmm
  53  */
  54 static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
  55         .name   = "dmm",
  56 };
  57
  58 /* dmm */
  59 static struct omap_hwmod omap54xx_dmm_hwmod = {
  60         .name           = "dmm",
  61         .class          = &omap54xx_dmm_hwmod_class,
  62         .clkdm_name     = "emif_clkdm",
  63         .prcm = {
  64                 .omap4 = {
  65                         .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  66                         .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  67                 },
  68         },
  69 };
  70
  71 /*
  72  * 'l3' class
  73  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  74  */
  75 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
  76         .name   = "l3",
  77 };
  78
  79 /* l3_instr */
  80 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
  81         .name           = "l3_instr",
  82         .class          = &omap54xx_l3_hwmod_class,
  83         .clkdm_name     = "l3instr_clkdm",
  84         .prcm = {
  85                 .omap4 = {
  86                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  87                         .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  88                         .modulemode   = MODULEMODE_HWCTRL,
  89                 },
  90         },
  91 };
  92
  93 /* l3_main_1 */
  94 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
  95         .name           = "l3_main_1",
  96         .class          = &omap54xx_l3_hwmod_class,
  97         .clkdm_name     = "l3main1_clkdm",
  98         .prcm = {
  99                 .omap4 = {
 100                         .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
 101                         .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
 102                 },
 103         },
 104 };
 105
 106 /* l3_main_2 */
 107 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
 108         .name           = "l3_main_2",
 109         .class          = &omap54xx_l3_hwmod_class,
 110         .clkdm_name     = "l3main2_clkdm",
 111         .prcm = {
 112                 .omap4 = {
 113                         .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
 114                         .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
 115                 },
 116         },
 117 };
 118
 119 /* l3_main_3 */
 120 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
 121         .name           = "l3_main_3",
 122         .class          = &omap54xx_l3_hwmod_class,
 123         .clkdm_name     = "l3instr_clkdm",
 124         .prcm = {
 125                 .omap4 = {
 126                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
 127                         .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
 128                         .modulemode   = MODULEMODE_HWCTRL,
 129                 },
 130         },
 131 };
 132
 133 /*
 134  * 'l4' class
 135  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 136  */
 137 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
 138         .name   = "l4",
 139 };
 140
 141 /* l4_abe */
 142 static struct omap_hwmod omap54xx_l4_abe_hwmod = {
 143         .name           = "l4_abe",
 144         .class          = &omap54xx_l4_hwmod_class,
 145         .clkdm_name     = "abe_clkdm",
 146         .prcm = {
 147                 .omap4 = {
 148                         .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
 149                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 150                 },
 151         },
 152 };
 153
 154 /* l4_cfg */
 155 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
 156         .name           = "l4_cfg",
 157         .class          = &omap54xx_l4_hwmod_class,
 158         .clkdm_name     = "l4cfg_clkdm",
 159         .prcm = {
 160                 .omap4 = {
 161                         .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 162                         .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 163                 },
 164         },
 165 };
 166
 167 /* l4_per */
 168 static struct omap_hwmod omap54xx_l4_per_hwmod = {
 169         .name           = "l4_per",
 170         .class          = &omap54xx_l4_hwmod_class,
 171         .clkdm_name     = "l4per_clkdm",
 172         .prcm = {
 173                 .omap4 = {
 174                         .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
 175                         .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 176                 },
 177         },
 178 };
 179
 180 /* l4_wkup */
 181 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
 182         .name           = "l4_wkup",
 183         .class          = &omap54xx_l4_hwmod_class,
 184         .clkdm_name     = "wkupaon_clkdm",
 185         .prcm = {
 186                 .omap4 = {
 187                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 188                         .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 189                 },
 190         },
 191 };
 192
 193 /*
 194  * 'mpu_bus' class
 195  * instance(s): mpu_private
 196  */
 197 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
 198         .name   = "mpu_bus",
 199 };
 200
 201 /* mpu_private */
 202 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
 203         .name           = "mpu_private",
 204         .class          = &omap54xx_mpu_bus_hwmod_class,
 205         .clkdm_name     = "mpu_clkdm",
 206         .prcm = {
 207                 .omap4 = {
 208                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 209                 },
 210         },
 211 };
 212
 213 /*
 214  * 'counter' class
 215  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 216  */
 217
 218 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
 219         .rev_offs       = 0x0000,
 220         .sysc_offs      = 0x0010,
 221         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 222         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 223         .sysc_fields    = &omap_hwmod_sysc_type1,
 224 };
 225
 226 static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
 227         .name   = "counter",
 228         .sysc   = &omap54xx_counter_sysc,
 229 };
 230
 231 /* counter_32k */
 232 static struct omap_hwmod omap54xx_counter_32k_hwmod = {
 233         .name           = "counter_32k",
 234         .class          = &omap54xx_counter_hwmod_class,
 235         .clkdm_name     = "wkupaon_clkdm",
 236         .flags          = HWMOD_SWSUP_SIDLE,
 237         .main_clk       = "wkupaon_iclk_mux",
 238         .prcm = {
 239                 .omap4 = {
 240                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 241                         .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 242                 },
 243         },
 244 };
 245
 246 /*
 247  * 'dma' class
 248  * dma controller for data exchange between memory to memory (i.e. internal or
 249  * external memory) and gp peripherals to memory or memory to gp peripherals
 250  */
 251
 252 static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
 253         .rev_offs       = 0x0000,
 254         .sysc_offs      = 0x002c,
 255         .syss_offs      = 0x0028,
 256         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 257                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 258                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 259                            SYSS_HAS_RESET_STATUS),
 260         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 261                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 262         .sysc_fields    = &omap_hwmod_sysc_type1,
 263 };
 264
 265 static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
 266         .name   = "dma",
 267         .sysc   = &omap54xx_dma_sysc,
 268 };
 269
 270 /* dma dev_attr */
 271 static struct omap_dma_dev_attr dma_dev_attr = {
 272         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 273                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 274         .lch_count      = 32,
 275 };
 276
 277 /* dma_system */
 278 static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
 279         { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
 280         { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
 281         { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
 282         { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
 283         { .irq = -1 }
 284 };
 285
 286 static struct omap_hwmod omap54xx_dma_system_hwmod = {
 287         .name           = "dma_system",
 288         .class          = &omap54xx_dma_hwmod_class,
 289         .clkdm_name     = "dma_clkdm",
 290         .mpu_irqs       = omap54xx_dma_system_irqs,
 291         .main_clk       = "l3_iclk_div",
 292         .prcm = {
 293                 .omap4 = {
 294                         .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
 295                         .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
 296                 },
 297         },
 298         .dev_attr       = &dma_dev_attr,
 299 };
 300
 301 /*
 302  * 'dmic' class
 303  * digital microphone controller
 304  */
 305
 306 static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
 307         .rev_offs       = 0x0000,
 308         .sysc_offs      = 0x0010,
 309         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 310                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 311         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 312                            SIDLE_SMART_WKUP),
 313         .sysc_fields    = &omap_hwmod_sysc_type2,
 314 };
 315
 316 static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
 317         .name   = "dmic",
 318         .sysc   = &omap54xx_dmic_sysc,
 319 };
 320
 321 /* dmic */
 322 static struct omap_hwmod omap54xx_dmic_hwmod = {
 323         .name           = "dmic",
 324         .class          = &omap54xx_dmic_hwmod_class,
 325         .clkdm_name     = "abe_clkdm",
 326         .main_clk       = "dmic_gfclk",
 327         .prcm = {
 328                 .omap4 = {
 329                         .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
 330                         .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
 331                         .modulemode   = MODULEMODE_SWCTRL,
 332                 },
 333         },
 334 };
 335
 336 /*
 337  * 'dss' class
 338  * display sub-system
 339  */
 340 static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = {
 341         .rev_offs       = 0x0000,
 342         .syss_offs      = 0x0014,
 343         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 344 };
 345
 346 static struct omap_hwmod_class omap54xx_dss_hwmod_class = {
 347         .name   = "dss",
 348         .sysc   = &omap54xx_dss_sysc,
 349         .reset  = omap_dss_reset,
 350 };
 351
 352 /* dss */
 353 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 354         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
 355         { .role = "sys_clk", .clk = "dss_sys_clk" },
 356         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 357 };
 358
 359 static struct omap_hwmod omap54xx_dss_hwmod = {
 360         .name           = "dss_core",
 361         .class          = &omap54xx_dss_hwmod_class,
 362         .clkdm_name     = "dss_clkdm",
 363         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 364         .main_clk       = "dss_dss_clk",
 365         .prcm = {
 366                 .omap4 = {
 367                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 368                         .context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET,
 369                         .modulemode   = MODULEMODE_SWCTRL,
 370                 },
 371         },
 372         .opt_clks       = dss_opt_clks,
 373         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 374 };
 375
 376 /*
 377  * 'dispc' class
 378  * display controller
 379  */
 380
 381 static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = {
 382         .rev_offs       = 0x0000,
 383         .sysc_offs      = 0x0010,
 384         .syss_offs      = 0x0014,
 385         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 386                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 387                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 388                            SYSS_HAS_RESET_STATUS),
 389         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 390                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 391         .sysc_fields    = &omap_hwmod_sysc_type1,
 392 };
 393
 394 static struct omap_hwmod_class omap54xx_dispc_hwmod_class = {
 395         .name   = "dispc",
 396         .sysc   = &omap54xx_dispc_sysc,
 397 };
 398
 399 /* dss_dispc */
 400 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
 401         { .role = "sys_clk", .clk = "dss_sys_clk" },
 402 };
 403
 404 /* dss_dispc dev_attr */
 405 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
 406         .has_framedonetv_irq    = 1,
 407         .manager_count          = 4,
 408 };
 409
 410 static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
 411         .name           = "dss_dispc",
 412         .class          = &omap54xx_dispc_hwmod_class,
 413         .clkdm_name     = "dss_clkdm",
 414         .main_clk       = "dss_dss_clk",
 415         .prcm = {
 416                 .omap4 = {
 417                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 418                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 419                 },
 420         },
 421         .opt_clks       = dss_dispc_opt_clks,
 422         .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
 423         .dev_attr       = &dss_dispc_dev_attr,
 424         .parent_hwmod   = &omap54xx_dss_hwmod,
 425 };
 426
 427 /*
 428  * 'dsi1' class
 429  * display serial interface controller
 430  */
 431
 432 static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = {
 433         .rev_offs       = 0x0000,
 434         .sysc_offs      = 0x0010,
 435         .syss_offs      = 0x0014,
 436         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 437                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 438                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 439         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 440         .sysc_fields    = &omap_hwmod_sysc_type1,
 441 };
 442
 443 static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = {
 444         .name   = "dsi1",
 445         .sysc   = &omap54xx_dsi1_sysc,
 446 };
 447
 448 /* dss_dsi1_a */
 449 static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = {
 450         { .role = "sys_clk", .clk = "dss_sys_clk" },
 451 };
 452
 453 static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
 454         .name           = "dss_dsi1",
 455         .class          = &omap54xx_dsi1_hwmod_class,
 456         .clkdm_name     = "dss_clkdm",
 457         .main_clk       = "dss_dss_clk",
 458         .prcm = {
 459                 .omap4 = {
 460                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 461                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 462                 },
 463         },
 464         .opt_clks       = dss_dsi1_a_opt_clks,
 465         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_a_opt_clks),
 466         .parent_hwmod   = &omap54xx_dss_hwmod,
 467 };
 468
 469 /* dss_dsi1_c */
 470 static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = {
 471         { .role = "sys_clk", .clk = "dss_sys_clk" },
 472 };
 473
 474 static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
 475         .name           = "dss_dsi2",
 476         .class          = &omap54xx_dsi1_hwmod_class,
 477         .clkdm_name     = "dss_clkdm",
 478         .main_clk       = "dss_dss_clk",
 479         .prcm = {
 480                 .omap4 = {
 481                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 482                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 483                 },
 484         },
 485         .opt_clks       = dss_dsi1_c_opt_clks,
 486         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_c_opt_clks),
 487         .parent_hwmod   = &omap54xx_dss_hwmod,
 488 };
 489
 490 /*
 491  * 'hdmi' class
 492  * hdmi controller
 493  */
 494
 495 static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = {
 496         .rev_offs       = 0x0000,
 497         .sysc_offs      = 0x0010,
 498         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 499                            SYSC_HAS_SOFTRESET),
 500         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 501                            SIDLE_SMART_WKUP),
 502         .sysc_fields    = &omap_hwmod_sysc_type2,
 503 };
 504
 505 static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = {
 506         .name   = "hdmi",
 507         .sysc   = &omap54xx_hdmi_sysc,
 508 };
 509
 510 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 511         { .role = "sys_clk", .clk = "dss_sys_clk" },
 512 };
 513
 514 static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
 515         .name           = "dss_hdmi",
 516         .class          = &omap54xx_hdmi_hwmod_class,
 517         .clkdm_name     = "dss_clkdm",
 518         .main_clk       = "dss_48mhz_clk",
 519         .prcm = {
 520                 .omap4 = {
 521                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 522                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 523                 },
 524         },
 525         .opt_clks       = dss_hdmi_opt_clks,
 526         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 527         .parent_hwmod   = &omap54xx_dss_hwmod,
 528 };
 529
 530 /*
 531  * 'rfbi' class
 532  * remote frame buffer interface
 533  */
 534
 535 static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = {
 536         .rev_offs       = 0x0000,
 537         .sysc_offs      = 0x0010,
 538         .syss_offs      = 0x0014,
 539         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 540                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 541         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 542         .sysc_fields    = &omap_hwmod_sysc_type1,
 543 };
 544
 545 static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = {
 546         .name   = "rfbi",
 547         .sysc   = &omap54xx_rfbi_sysc,
 548 };
 549
 550 /* dss_rfbi */
 551 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 552         { .role = "ick", .clk = "l3_iclk_div" },
 553 };
 554
 555 static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
 556         .name           = "dss_rfbi",
 557         .class          = &omap54xx_rfbi_hwmod_class,
 558         .clkdm_name     = "dss_clkdm",
 559         .prcm = {
 560                 .omap4 = {
 561                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 562                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 563                 },
 564         },
 565         .opt_clks       = dss_rfbi_opt_clks,
 566         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 567         .parent_hwmod   = &omap54xx_dss_hwmod,
 568 };
 569
 570 /*
 571  * 'emif' class
 572  * external memory interface no1 (wrapper)
 573  */
 574
 575 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
 576         .rev_offs       = 0x0000,
 577 };
 578
 579 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
 580         .name   = "emif",
 581         .sysc   = &omap54xx_emif_sysc,
 582 };
 583
 584 /* emif1 */
 585 static struct omap_hwmod omap54xx_emif1_hwmod = {
 586         .name           = "emif1",
 587         .class          = &omap54xx_emif_hwmod_class,
 588         .clkdm_name     = "emif_clkdm",
 589         .flags          = HWMOD_INIT_NO_IDLE,
 590         .main_clk       = "dpll_core_h11x2_ck",
 591         .prcm = {
 592                 .omap4 = {
 593                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
 594                         .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
 595                         .modulemode   = MODULEMODE_HWCTRL,
 596                 },
 597         },
 598 };
 599
 600 /* emif2 */
 601 static struct omap_hwmod omap54xx_emif2_hwmod = {
 602         .name           = "emif2",
 603         .class          = &omap54xx_emif_hwmod_class,
 604         .clkdm_name     = "emif_clkdm",
 605         .flags          = HWMOD_INIT_NO_IDLE,
 606         .main_clk       = "dpll_core_h11x2_ck",
 607         .prcm = {
 608                 .omap4 = {
 609                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
 610                         .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
 611                         .modulemode   = MODULEMODE_HWCTRL,
 612                 },
 613         },
 614 };
 615
 616 /*
 617  * 'gpio' class
 618  * general purpose io module
 619  */
 620
 621 static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
 622         .rev_offs       = 0x0000,
 623         .sysc_offs      = 0x0010,
 624         .syss_offs      = 0x0114,
 625         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 626                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 627                            SYSS_HAS_RESET_STATUS),
 628         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 629                            SIDLE_SMART_WKUP),
 630         .sysc_fields    = &omap_hwmod_sysc_type1,
 631 };
 632
 633 static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
 634         .name   = "gpio",
 635         .sysc   = &omap54xx_gpio_sysc,
 636         .rev    = 2,
 637 };
 638
 639 /* gpio dev_attr */
 640 static struct omap_gpio_dev_attr gpio_dev_attr = {
 641         .bank_width     = 32,
 642         .dbck_flag      = true,
 643 };
 644
 645 /* gpio1 */
 646 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 647         { .role = "dbclk", .clk = "gpio1_dbclk" },
 648 };
 649
 650 static struct omap_hwmod omap54xx_gpio1_hwmod = {
 651         .name           = "gpio1",
 652         .class          = &omap54xx_gpio_hwmod_class,
 653         .clkdm_name     = "wkupaon_clkdm",
 654         .main_clk       = "wkupaon_iclk_mux",
 655         .prcm = {
 656                 .omap4 = {
 657                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
 658                         .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
 659                         .modulemode   = MODULEMODE_HWCTRL,
 660                 },
 661         },
 662         .opt_clks       = gpio1_opt_clks,
 663         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 664         .dev_attr       = &gpio_dev_attr,
 665 };
 666
 667 /* gpio2 */
 668 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 669         { .role = "dbclk", .clk = "gpio2_dbclk" },
 670 };
 671
 672 static struct omap_hwmod omap54xx_gpio2_hwmod = {
 673         .name           = "gpio2",
 674         .class          = &omap54xx_gpio_hwmod_class,
 675         .clkdm_name     = "l4per_clkdm",
 676         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 677         .main_clk       = "l4_root_clk_div",
 678         .prcm = {
 679                 .omap4 = {
 680                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
 681                         .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
 682                         .modulemode   = MODULEMODE_HWCTRL,
 683                 },
 684         },
 685         .opt_clks       = gpio2_opt_clks,
 686         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 687         .dev_attr       = &gpio_dev_attr,
 688 };
 689
 690 /* gpio3 */
 691 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 692         { .role = "dbclk", .clk = "gpio3_dbclk" },
 693 };
 694
 695 static struct omap_hwmod omap54xx_gpio3_hwmod = {
 696         .name           = "gpio3",
 697         .class          = &omap54xx_gpio_hwmod_class,
 698         .clkdm_name     = "l4per_clkdm",
 699         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 700         .main_clk       = "l4_root_clk_div",
 701         .prcm = {
 702                 .omap4 = {
 703                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
 704                         .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
 705                         .modulemode   = MODULEMODE_HWCTRL,
 706                 },
 707         },
 708         .opt_clks       = gpio3_opt_clks,
 709         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 710         .dev_attr       = &gpio_dev_attr,
 711 };
 712
 713 /* gpio4 */
 714 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 715         { .role = "dbclk", .clk = "gpio4_dbclk" },
 716 };
 717
 718 static struct omap_hwmod omap54xx_gpio4_hwmod = {
 719         .name           = "gpio4",
 720         .class          = &omap54xx_gpio_hwmod_class,
 721         .clkdm_name     = "l4per_clkdm",
 722         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 723         .main_clk       = "l4_root_clk_div",
 724         .prcm = {
 725                 .omap4 = {
 726                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
 727                         .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
 728                         .modulemode   = MODULEMODE_HWCTRL,
 729                 },
 730         },
 731         .opt_clks       = gpio4_opt_clks,
 732         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 733         .dev_attr       = &gpio_dev_attr,
 734 };
 735
 736 /* gpio5 */
 737 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 738         { .role = "dbclk", .clk = "gpio5_dbclk" },
 739 };
 740
 741 static struct omap_hwmod omap54xx_gpio5_hwmod = {
 742         .name           = "gpio5",
 743         .class          = &omap54xx_gpio_hwmod_class,
 744         .clkdm_name     = "l4per_clkdm",
 745         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 746         .main_clk       = "l4_root_clk_div",
 747         .prcm = {
 748                 .omap4 = {
 749                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
 750                         .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
 751                         .modulemode   = MODULEMODE_HWCTRL,
 752                 },
 753         },
 754         .opt_clks       = gpio5_opt_clks,
 755         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 756         .dev_attr       = &gpio_dev_attr,
 757 };
 758
 759 /* gpio6 */
 760 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 761         { .role = "dbclk", .clk = "gpio6_dbclk" },
 762 };
 763
 764 static struct omap_hwmod omap54xx_gpio6_hwmod = {
 765         .name           = "gpio6",
 766         .class          = &omap54xx_gpio_hwmod_class,
 767         .clkdm_name     = "l4per_clkdm",
 768         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 769         .main_clk       = "l4_root_clk_div",
 770         .prcm = {
 771                 .omap4 = {
 772                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
 773                         .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
 774                         .modulemode   = MODULEMODE_HWCTRL,
 775                 },
 776         },
 777         .opt_clks       = gpio6_opt_clks,
 778         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 779         .dev_attr       = &gpio_dev_attr,
 780 };
 781
 782 /* gpio7 */
 783 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
 784         { .role = "dbclk", .clk = "gpio7_dbclk" },
 785 };
 786
 787 static struct omap_hwmod omap54xx_gpio7_hwmod = {
 788         .name           = "gpio7",
 789         .class          = &omap54xx_gpio_hwmod_class,
 790         .clkdm_name     = "l4per_clkdm",
 791         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 792         .main_clk       = "l4_root_clk_div",
 793         .prcm = {
 794                 .omap4 = {
 795                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
 796                         .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
 797                         .modulemode   = MODULEMODE_HWCTRL,
 798                 },
 799         },
 800         .opt_clks       = gpio7_opt_clks,
 801         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
 802         .dev_attr       = &gpio_dev_attr,
 803 };
 804
 805 /* gpio8 */
 806 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
 807         { .role = "dbclk", .clk = "gpio8_dbclk" },
 808 };
 809
 810 static struct omap_hwmod omap54xx_gpio8_hwmod = {
 811         .name           = "gpio8",
 812         .class          = &omap54xx_gpio_hwmod_class,
 813         .clkdm_name     = "l4per_clkdm",
 814         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 815         .main_clk       = "l4_root_clk_div",
 816         .prcm = {
 817                 .omap4 = {
 818                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
 819                         .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
 820                         .modulemode   = MODULEMODE_HWCTRL,
 821                 },
 822         },
 823         .opt_clks       = gpio8_opt_clks,
 824         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
 825         .dev_attr       = &gpio_dev_attr,
 826 };
 827
 828 /*
 829  * 'i2c' class
 830  * multimaster high-speed i2c controller
 831  */
 832
 833 static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
 834         .sysc_offs      = 0x0010,
 835         .syss_offs      = 0x0090,
 836         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 837                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 838                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 839         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 840                            SIDLE_SMART_WKUP),
 841         .clockact       = CLOCKACT_TEST_ICLK,
 842         .sysc_fields    = &omap_hwmod_sysc_type1,
 843 };
 844
 845 static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
 846         .name   = "i2c",
 847         .sysc   = &omap54xx_i2c_sysc,
 848         .reset  = &omap_i2c_reset,
 849         .rev    = OMAP_I2C_IP_VERSION_2,
 850 };
 851
 852 /* i2c dev_attr */
 853 static struct omap_i2c_dev_attr i2c_dev_attr = {
 854         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
 855 };
 856
 857 /* i2c1 */
 858 static struct omap_hwmod omap54xx_i2c1_hwmod = {
 859         .name           = "i2c1",
 860         .class          = &omap54xx_i2c_hwmod_class,
 861         .clkdm_name     = "l4per_clkdm",
 862         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 863         .main_clk       = "func_96m_fclk",
 864         .prcm = {
 865                 .omap4 = {
 866                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
 867                         .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
 868                         .modulemode   = MODULEMODE_SWCTRL,
 869                 },
 870         },
 871         .dev_attr       = &i2c_dev_attr,
 872 };
 873
 874 /* i2c2 */
 875 static struct omap_hwmod omap54xx_i2c2_hwmod = {
 876         .name           = "i2c2",
 877         .class          = &omap54xx_i2c_hwmod_class,
 878         .clkdm_name     = "l4per_clkdm",
 879         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 880         .main_clk       = "func_96m_fclk",
 881         .prcm = {
 882                 .omap4 = {
 883                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
 884                         .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
 885                         .modulemode   = MODULEMODE_SWCTRL,
 886                 },
 887         },
 888         .dev_attr       = &i2c_dev_attr,
 889 };
 890
 891 /* i2c3 */
 892 static struct omap_hwmod omap54xx_i2c3_hwmod = {
 893         .name           = "i2c3",
 894         .class          = &omap54xx_i2c_hwmod_class,
 895         .clkdm_name     = "l4per_clkdm",
 896         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 897         .main_clk       = "func_96m_fclk",
 898         .prcm = {
 899                 .omap4 = {
 900                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
 901                         .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
 902                         .modulemode   = MODULEMODE_SWCTRL,
 903                 },
 904         },
 905         .dev_attr       = &i2c_dev_attr,
 906 };
 907
 908 /* i2c4 */
 909 static struct omap_hwmod omap54xx_i2c4_hwmod = {
 910         .name           = "i2c4",
 911         .class          = &omap54xx_i2c_hwmod_class,
 912         .clkdm_name     = "l4per_clkdm",
 913         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 914         .main_clk       = "func_96m_fclk",
 915         .prcm = {
 916                 .omap4 = {
 917                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
 918                         .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
 919                         .modulemode   = MODULEMODE_SWCTRL,
 920                 },
 921         },
 922         .dev_attr       = &i2c_dev_attr,
 923 };
 924
 925 /* i2c5 */
 926 static struct omap_hwmod omap54xx_i2c5_hwmod = {
 927         .name           = "i2c5",
 928         .class          = &omap54xx_i2c_hwmod_class,
 929         .clkdm_name     = "l4per_clkdm",
 930         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 931         .main_clk       = "func_96m_fclk",
 932         .prcm = {
 933                 .omap4 = {
 934                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
 935                         .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
 936                         .modulemode   = MODULEMODE_SWCTRL,
 937                 },
 938         },
 939         .dev_attr       = &i2c_dev_attr,
 940 };
 941
 942 /*
 943  * 'kbd' class
 944  * keyboard controller
 945  */
 946
 947 static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
 948         .rev_offs       = 0x0000,
 949         .sysc_offs      = 0x0010,
 950         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
 951                            SYSC_HAS_SOFTRESET),
 952         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 953         .sysc_fields    = &omap_hwmod_sysc_type1,
 954 };
 955
 956 static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
 957         .name   = "kbd",
 958         .sysc   = &omap54xx_kbd_sysc,
 959 };
 960
 961 /* kbd */
 962 static struct omap_hwmod omap54xx_kbd_hwmod = {
 963         .name           = "kbd",
 964         .class          = &omap54xx_kbd_hwmod_class,
 965         .clkdm_name     = "wkupaon_clkdm",
 966         .main_clk       = "sys_32k_ck",
 967         .prcm = {
 968                 .omap4 = {
 969                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
 970                         .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
 971                         .modulemode   = MODULEMODE_SWCTRL,
 972                 },
 973         },
 974 };
 975
 976 /*
 977  * 'mailbox' class
 978  * mailbox module allowing communication between the on-chip processors using a
 979  * queued mailbox-interrupt mechanism.
 980  */
 981
 982 static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
 983         .rev_offs       = 0x0000,
 984         .sysc_offs      = 0x0010,
 985         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 986                            SYSC_HAS_SOFTRESET),
 987         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 988         .sysc_fields    = &omap_hwmod_sysc_type2,
 989 };
 990
 991 static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
 992         .name   = "mailbox",
 993         .sysc   = &omap54xx_mailbox_sysc,
 994 };
 995
 996 /* mailbox */
 997 static struct omap_hwmod omap54xx_mailbox_hwmod = {
 998         .name           = "mailbox",
 999         .class          = &omap54xx_mailbox_hwmod_class,
1000         .clkdm_name     = "l4cfg_clkdm",
1001         .prcm = {
1002                 .omap4 = {
1003                         .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1004                         .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1005                 },
1006         },
1007 };
1008
1009 /*
1010  * 'mcbsp' class
1011  * multi channel buffered serial port controller
1012  */
1013
1014 static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
1015         .sysc_offs      = 0x008c,
1016         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1017                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1018         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1019         .sysc_fields    = &omap_hwmod_sysc_type1,
1020 };
1021
1022 static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
1023         .name   = "mcbsp",
1024         .sysc   = &omap54xx_mcbsp_sysc,
1025         .rev    = MCBSP_CONFIG_TYPE4,
1026 };
1027
1028 /* mcbsp1 */
1029 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1030         { .role = "pad_fck", .clk = "pad_clks_ck" },
1031         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1032 };
1033
1034 static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
1035         .name           = "mcbsp1",
1036         .class          = &omap54xx_mcbsp_hwmod_class,
1037         .clkdm_name     = "abe_clkdm",
1038         .main_clk       = "mcbsp1_gfclk",
1039         .prcm = {
1040                 .omap4 = {
1041                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
1042                         .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1043                         .modulemode   = MODULEMODE_SWCTRL,
1044                 },
1045         },
1046         .opt_clks       = mcbsp1_opt_clks,
1047         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1048 };
1049
1050 /* mcbsp2 */
1051 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1052         { .role = "pad_fck", .clk = "pad_clks_ck" },
1053         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1054 };
1055
1056 static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
1057         .name           = "mcbsp2",
1058         .class          = &omap54xx_mcbsp_hwmod_class,
1059         .clkdm_name     = "abe_clkdm",
1060         .main_clk       = "mcbsp2_gfclk",
1061         .prcm = {
1062                 .omap4 = {
1063                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
1064                         .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1065                         .modulemode   = MODULEMODE_SWCTRL,
1066                 },
1067         },
1068         .opt_clks       = mcbsp2_opt_clks,
1069         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
1070 };
1071
1072 /* mcbsp3 */
1073 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1074         { .role = "pad_fck", .clk = "pad_clks_ck" },
1075         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1076 };
1077
1078 static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
1079         .name           = "mcbsp3",
1080         .class          = &omap54xx_mcbsp_hwmod_class,
1081         .clkdm_name     = "abe_clkdm",
1082         .main_clk       = "mcbsp3_gfclk",
1083         .prcm = {
1084                 .omap4 = {
1085                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
1086                         .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1087                         .modulemode   = MODULEMODE_SWCTRL,
1088                 },
1089         },
1090         .opt_clks       = mcbsp3_opt_clks,
1091         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
1092 };
1093
1094 /*
1095  * 'mcpdm' class
1096  * multi channel pdm controller (proprietary interface with phoenix power
1097  * ic)
1098  */
1099
1100 static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
1101         .rev_offs       = 0x0000,
1102         .sysc_offs      = 0x0010,
1103         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1104                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1105         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1106                            SIDLE_SMART_WKUP),
1107         .sysc_fields    = &omap_hwmod_sysc_type2,
1108 };
1109
1110 static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
1111         .name   = "mcpdm",
1112         .sysc   = &omap54xx_mcpdm_sysc,
1113 };
1114
1115 /* mcpdm */
1116 static struct omap_hwmod omap54xx_mcpdm_hwmod = {
1117         .name           = "mcpdm",
1118         .class          = &omap54xx_mcpdm_hwmod_class,
1119         .clkdm_name     = "abe_clkdm",
1120         /*
1121          * It's suspected that the McPDM requires an off-chip main
1122          * functional clock, controlled via I2C.  This IP block is
1123          * currently reset very early during boot, before I2C is
1124          * available, so it doesn't seem that we have any choice in
1125          * the kernel other than to avoid resetting it.  XXX This is
1126          * really a hardware issue workaround: every IP block should
1127          * be able to source its main functional clock from either
1128          * on-chip or off-chip sources.  McPDM seems to be the only
1129          * current exception.
1130          */
1131
1132         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1133         .main_clk       = "pad_clks_ck",
1134         .prcm = {
1135                 .omap4 = {
1136                         .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
1137                         .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
1138                         .modulemode   = MODULEMODE_SWCTRL,
1139                 },
1140         },
1141 };
1142
1143 /*
1144  * 'mcspi' class
1145  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1146  * bus
1147  */
1148
1149 static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
1150         .rev_offs       = 0x0000,
1151         .sysc_offs      = 0x0010,
1152         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1153                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1154         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1155                            SIDLE_SMART_WKUP),
1156         .sysc_fields    = &omap_hwmod_sysc_type2,
1157 };
1158
1159 static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
1160         .name   = "mcspi",
1161         .sysc   = &omap54xx_mcspi_sysc,
1162         .rev    = OMAP4_MCSPI_REV,
1163 };
1164
1165 /* mcspi1 */
1166 /* mcspi1 dev_attr */
1167 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1168         .num_chipselect = 4,
1169 };
1170
1171 static struct omap_hwmod omap54xx_mcspi1_hwmod = {
1172         .name           = "mcspi1",
1173         .class          = &omap54xx_mcspi_hwmod_class,
1174         .clkdm_name     = "l4per_clkdm",
1175         .main_clk       = "func_48m_fclk",
1176         .prcm = {
1177                 .omap4 = {
1178                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1179                         .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1180                         .modulemode   = MODULEMODE_SWCTRL,
1181                 },
1182         },
1183         .dev_attr       = &mcspi1_dev_attr,
1184 };
1185
1186 /* mcspi2 */
1187 /* mcspi2 dev_attr */
1188 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1189         .num_chipselect = 2,
1190 };
1191
1192 static struct omap_hwmod omap54xx_mcspi2_hwmod = {
1193         .name           = "mcspi2",
1194         .class          = &omap54xx_mcspi_hwmod_class,
1195         .clkdm_name     = "l4per_clkdm",
1196         .main_clk       = "func_48m_fclk",
1197         .prcm = {
1198                 .omap4 = {
1199                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1200                         .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1201                         .modulemode   = MODULEMODE_SWCTRL,
1202                 },
1203         },
1204         .dev_attr       = &mcspi2_dev_attr,
1205 };
1206
1207 /* mcspi3 */
1208 /* mcspi3 dev_attr */
1209 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1210         .num_chipselect = 2,
1211 };
1212
1213 static struct omap_hwmod omap54xx_mcspi3_hwmod = {
1214         .name           = "mcspi3",
1215         .class          = &omap54xx_mcspi_hwmod_class,
1216         .clkdm_name     = "l4per_clkdm",
1217         .main_clk       = "func_48m_fclk",
1218         .prcm = {
1219                 .omap4 = {
1220                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1221                         .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1222                         .modulemode   = MODULEMODE_SWCTRL,
1223                 },
1224         },
1225         .dev_attr       = &mcspi3_dev_attr,
1226 };
1227
1228 /* mcspi4 */
1229 /* mcspi4 dev_attr */
1230 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1231         .num_chipselect = 1,
1232 };
1233
1234 static struct omap_hwmod omap54xx_mcspi4_hwmod = {
1235         .name           = "mcspi4",
1236         .class          = &omap54xx_mcspi_hwmod_class,
1237         .clkdm_name     = "l4per_clkdm",
1238         .main_clk       = "func_48m_fclk",
1239         .prcm = {
1240                 .omap4 = {
1241                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1242                         .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1243                         .modulemode   = MODULEMODE_SWCTRL,
1244                 },
1245         },
1246         .dev_attr       = &mcspi4_dev_attr,
1247 };
1248
1249 /*
1250  * 'mmc' class
1251  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1252  */
1253
1254 static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
1255         .rev_offs       = 0x0000,
1256         .sysc_offs      = 0x0010,
1257         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1258                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1259                            SYSC_HAS_SOFTRESET),
1260         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1261                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1262                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1263         .sysc_fields    = &omap_hwmod_sysc_type2,
1264 };
1265
1266 static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
1267         .name   = "mmc",
1268         .sysc   = &omap54xx_mmc_sysc,
1269 };
1270
1271 /* mmc1 */
1272 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1273         { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
1274 };
1275
1276 /* mmc1 dev_attr */
1277 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1278         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1279 };
1280
1281 static struct omap_hwmod omap54xx_mmc1_hwmod = {
1282         .name           = "mmc1",
1283         .class          = &omap54xx_mmc_hwmod_class,
1284         .clkdm_name     = "l3init_clkdm",
1285         .main_clk       = "mmc1_fclk",
1286         .prcm = {
1287                 .omap4 = {
1288                         .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1289                         .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1290                         .modulemode   = MODULEMODE_SWCTRL,
1291                 },
1292         },
1293         .opt_clks       = mmc1_opt_clks,
1294         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
1295         .dev_attr       = &mmc1_dev_attr,
1296 };
1297
1298 /* mmc2 */
1299 static struct omap_hwmod omap54xx_mmc2_hwmod = {
1300         .name           = "mmc2",
1301         .class          = &omap54xx_mmc_hwmod_class,
1302         .clkdm_name     = "l3init_clkdm",
1303         .main_clk       = "mmc2_fclk",
1304         .prcm = {
1305                 .omap4 = {
1306                         .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1307                         .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1308                         .modulemode   = MODULEMODE_SWCTRL,
1309                 },
1310         },
1311 };
1312
1313 /* mmc3 */
1314 static struct omap_hwmod omap54xx_mmc3_hwmod = {
1315         .name           = "mmc3",
1316         .class          = &omap54xx_mmc_hwmod_class,
1317         .clkdm_name     = "l4per_clkdm",
1318         .main_clk       = "func_48m_fclk",
1319         .prcm = {
1320                 .omap4 = {
1321                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1322                         .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1323                         .modulemode   = MODULEMODE_SWCTRL,
1324                 },
1325         },
1326 };
1327
1328 /* mmc4 */
1329 static struct omap_hwmod omap54xx_mmc4_hwmod = {
1330         .name           = "mmc4",
1331         .class          = &omap54xx_mmc_hwmod_class,
1332         .clkdm_name     = "l4per_clkdm",
1333         .main_clk       = "func_48m_fclk",
1334         .prcm = {
1335                 .omap4 = {
1336                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1337                         .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1338                         .modulemode   = MODULEMODE_SWCTRL,
1339                 },
1340         },
1341 };
1342
1343 /* mmc5 */
1344 static struct omap_hwmod omap54xx_mmc5_hwmod = {
1345         .name           = "mmc5",
1346         .class          = &omap54xx_mmc_hwmod_class,
1347         .clkdm_name     = "l4per_clkdm",
1348         .main_clk       = "func_96m_fclk",
1349         .prcm = {
1350                 .omap4 = {
1351                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
1352                         .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
1353                         .modulemode   = MODULEMODE_SWCTRL,
1354                 },
1355         },
1356 };
1357
1358 /*
1359  * 'mmu' class
1360  * The memory management unit performs virtual to physical address translation
1361  * for its requestors.
1362  */
1363
1364 static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc = {
1365         .rev_offs       = 0x0000,
1366         .sysc_offs      = 0x0010,
1367         .syss_offs      = 0x0014,
1368         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1369                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1370                            SYSS_HAS_RESET_STATUS),
1371         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1372         .sysc_fields    = &omap_hwmod_sysc_type1,
1373 };
1374
1375 static struct omap_hwmod_class omap54xx_mmu_hwmod_class = {
1376         .name = "mmu",
1377         .sysc = &omap54xx_mmu_sysc,
1378 };
1379
1380 static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = {
1381         { .name = "mmu_cache", .rst_shift = 1 },
1382 };
1383
1384 static struct omap_hwmod omap54xx_mmu_dsp_hwmod = {
1385         .name           = "mmu_dsp",
1386         .class          = &omap54xx_mmu_hwmod_class,
1387         .clkdm_name     = "dsp_clkdm",
1388         .rst_lines      = omap54xx_mmu_dsp_resets,
1389         .rst_lines_cnt  = ARRAY_SIZE(omap54xx_mmu_dsp_resets),
1390         .main_clk       = "dpll_iva_h11x2_ck",
1391         .prcm = {
1392                 .omap4 = {
1393                         .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET,
1394                         .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET,
1395                         .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET,
1396                         .modulemode   = MODULEMODE_HWCTRL,
1397                 },
1398         },
1399 };
1400
1401 /* mmu ipu */
1402 static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = {
1403         { .name = "mmu_cache", .rst_shift = 2 },
1404 };
1405
1406 static struct omap_hwmod omap54xx_mmu_ipu_hwmod = {
1407         .name           = "mmu_ipu",
1408         .class          = &omap54xx_mmu_hwmod_class,
1409         .clkdm_name     = "ipu_clkdm",
1410         .rst_lines      = omap54xx_mmu_ipu_resets,
1411         .rst_lines_cnt  = ARRAY_SIZE(omap54xx_mmu_ipu_resets),
1412         .main_clk       = "dpll_core_h22x2_ck",
1413         .prcm = {
1414                 .omap4 = {
1415                         .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET,
1416                         .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET,
1417                         .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET,
1418                         .modulemode   = MODULEMODE_HWCTRL,
1419                 },
1420         },
1421 };
1422
1423 /*
1424  * 'mpu' class
1425  * mpu sub-system
1426  */
1427
1428 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
1429         .name   = "mpu",
1430 };
1431
1432 /* mpu */
1433 static struct omap_hwmod omap54xx_mpu_hwmod = {
1434         .name           = "mpu",
1435         .class          = &omap54xx_mpu_hwmod_class,
1436         .clkdm_name     = "mpu_clkdm",
1437         .flags          = HWMOD_INIT_NO_IDLE,
1438         .main_clk       = "dpll_mpu_m2_ck",
1439         .prcm = {
1440                 .omap4 = {
1441                         .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1442                         .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
1443                 },
1444         },
1445 };
1446
1447 /*
1448  * 'spinlock' class
1449  * spinlock provides hardware assistance for synchronizing the processes
1450  * running on multiple processors
1451  */
1452
1453 static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = {
1454         .rev_offs       = 0x0000,
1455         .sysc_offs      = 0x0010,
1456         .syss_offs      = 0x0014,
1457         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1458                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1459                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1460         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1461         .sysc_fields    = &omap_hwmod_sysc_type1,
1462 };
1463
1464 static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = {
1465         .name   = "spinlock",
1466         .sysc   = &omap54xx_spinlock_sysc,
1467 };
1468
1469 /* spinlock */
1470 static struct omap_hwmod omap54xx_spinlock_hwmod = {
1471         .name           = "spinlock",
1472         .class          = &omap54xx_spinlock_hwmod_class,
1473         .clkdm_name     = "l4cfg_clkdm",
1474         .prcm = {
1475                 .omap4 = {
1476                         .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1477                         .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1478                 },
1479         },
1480 };
1481
1482 /*
1483  * 'ocp2scp' class
1484  * bridge to transform ocp interface protocol to scp (serial control port)
1485  * protocol
1486  */
1487
1488 static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {
1489         .rev_offs       = 0x0000,
1490         .sysc_offs      = 0x0010,
1491         .syss_offs      = 0x0014,
1492         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1493                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1494         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1495         .sysc_fields    = &omap_hwmod_sysc_type1,
1496 };
1497
1498 static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {
1499         .name   = "ocp2scp",
1500         .sysc   = &omap54xx_ocp2scp_sysc,
1501 };
1502
1503 /* ocp2scp1 */
1504 static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {
1505         .name           = "ocp2scp1",
1506         .class          = &omap54xx_ocp2scp_hwmod_class,
1507         .clkdm_name     = "l3init_clkdm",
1508         .main_clk       = "l4_root_clk_div",
1509         .prcm = {
1510                 .omap4 = {
1511                         .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1512                         .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1513                         .modulemode   = MODULEMODE_HWCTRL,
1514                 },
1515         },
1516 };
1517
1518 /*
1519  * 'timer' class
1520  * general purpose timer module with accurate 1ms tick
1521  * This class contains several variants: ['timer_1ms', 'timer']
1522  */
1523
1524 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
1525         .rev_offs       = 0x0000,
1526         .sysc_offs      = 0x0010,
1527         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1528                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1529         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1530                            SIDLE_SMART_WKUP),
1531         .sysc_fields    = &omap_hwmod_sysc_type2,
1532         .clockact       = CLOCKACT_TEST_ICLK,
1533 };
1534
1535 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
1536         .name   = "timer",
1537         .sysc   = &omap54xx_timer_1ms_sysc,
1538 };
1539
1540 static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
1541         .rev_offs       = 0x0000,
1542         .sysc_offs      = 0x0010,
1543         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1544                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1545         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1546                            SIDLE_SMART_WKUP),
1547         .sysc_fields    = &omap_hwmod_sysc_type2,
1548 };
1549
1550 static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
1551         .name   = "timer",
1552         .sysc   = &omap54xx_timer_sysc,
1553 };
1554
1555 /* timer1 */
1556 static struct omap_hwmod omap54xx_timer1_hwmod = {
1557         .name           = "timer1",
1558         .class          = &omap54xx_timer_1ms_hwmod_class,
1559         .clkdm_name     = "wkupaon_clkdm",
1560         .main_clk       = "timer1_gfclk_mux",
1561         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1562         .prcm = {
1563                 .omap4 = {
1564                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1565                         .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1566                         .modulemode   = MODULEMODE_SWCTRL,
1567                 },
1568         },
1569 };
1570
1571 /* timer2 */
1572 static struct omap_hwmod omap54xx_timer2_hwmod = {
1573         .name           = "timer2",
1574         .class          = &omap54xx_timer_1ms_hwmod_class,
1575         .clkdm_name     = "l4per_clkdm",
1576         .main_clk       = "timer2_gfclk_mux",
1577         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1578         .prcm = {
1579                 .omap4 = {
1580                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1581                         .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1582                         .modulemode   = MODULEMODE_SWCTRL,
1583                 },
1584         },
1585 };
1586
1587 /* timer3 */
1588 static struct omap_hwmod omap54xx_timer3_hwmod = {
1589         .name           = "timer3",
1590         .class          = &omap54xx_timer_hwmod_class,
1591         .clkdm_name     = "l4per_clkdm",
1592         .main_clk       = "timer3_gfclk_mux",
1593         .prcm = {
1594                 .omap4 = {
1595                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1596                         .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1597                         .modulemode   = MODULEMODE_SWCTRL,
1598                 },
1599         },
1600 };
1601
1602 /* timer4 */
1603 static struct omap_hwmod omap54xx_timer4_hwmod = {
1604         .name           = "timer4",
1605         .class          = &omap54xx_timer_hwmod_class,
1606         .clkdm_name     = "l4per_clkdm",
1607         .main_clk       = "timer4_gfclk_mux",
1608         .prcm = {
1609                 .omap4 = {
1610                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1611                         .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1612                         .modulemode   = MODULEMODE_SWCTRL,
1613                 },
1614         },
1615 };
1616
1617 /* timer5 */
1618 static struct omap_hwmod omap54xx_timer5_hwmod = {
1619         .name           = "timer5",
1620         .class          = &omap54xx_timer_hwmod_class,
1621         .clkdm_name     = "abe_clkdm",
1622         .main_clk       = "timer5_gfclk_mux",
1623         .prcm = {
1624                 .omap4 = {
1625                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
1626                         .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
1627                         .modulemode   = MODULEMODE_SWCTRL,
1628                 },
1629         },
1630 };
1631
1632 /* timer6 */
1633 static struct omap_hwmod omap54xx_timer6_hwmod = {
1634         .name           = "timer6",
1635         .class          = &omap54xx_timer_hwmod_class,
1636         .clkdm_name     = "abe_clkdm",
1637         .main_clk       = "timer6_gfclk_mux",
1638         .prcm = {
1639                 .omap4 = {
1640                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
1641                         .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
1642                         .modulemode   = MODULEMODE_SWCTRL,
1643                 },
1644         },
1645 };
1646
1647 /* timer7 */
1648 static struct omap_hwmod omap54xx_timer7_hwmod = {
1649         .name           = "timer7",
1650         .class          = &omap54xx_timer_hwmod_class,
1651         .clkdm_name     = "abe_clkdm",
1652         .main_clk       = "timer7_gfclk_mux",
1653         .prcm = {
1654                 .omap4 = {
1655                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
1656                         .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
1657                         .modulemode   = MODULEMODE_SWCTRL,
1658                 },
1659         },
1660 };
1661
1662 /* timer8 */
1663 static struct omap_hwmod omap54xx_timer8_hwmod = {
1664         .name           = "timer8",
1665         .class          = &omap54xx_timer_hwmod_class,
1666         .clkdm_name     = "abe_clkdm",
1667         .main_clk       = "timer8_gfclk_mux",
1668         .prcm = {
1669                 .omap4 = {
1670                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
1671                         .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
1672                         .modulemode   = MODULEMODE_SWCTRL,
1673                 },
1674         },
1675 };
1676
1677 /* timer9 */
1678 static struct omap_hwmod omap54xx_timer9_hwmod = {
1679         .name           = "timer9",
1680         .class          = &omap54xx_timer_hwmod_class,
1681         .clkdm_name     = "l4per_clkdm",
1682         .main_clk       = "timer9_gfclk_mux",
1683         .prcm = {
1684                 .omap4 = {
1685                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1686                         .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1687                         .modulemode   = MODULEMODE_SWCTRL,
1688                 },
1689         },
1690 };
1691
1692 /* timer10 */
1693 static struct omap_hwmod omap54xx_timer10_hwmod = {
1694         .name           = "timer10",
1695         .class          = &omap54xx_timer_1ms_hwmod_class,
1696         .clkdm_name     = "l4per_clkdm",
1697         .main_clk       = "timer10_gfclk_mux",
1698         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1699         .prcm = {
1700                 .omap4 = {
1701                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1702                         .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1703                         .modulemode   = MODULEMODE_SWCTRL,
1704                 },
1705         },
1706 };
1707
1708 /* timer11 */
1709 static struct omap_hwmod omap54xx_timer11_hwmod = {
1710         .name           = "timer11",
1711         .class          = &omap54xx_timer_hwmod_class,
1712         .clkdm_name     = "l4per_clkdm",
1713         .main_clk       = "timer11_gfclk_mux",
1714         .prcm = {
1715                 .omap4 = {
1716                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1717                         .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1718                         .modulemode   = MODULEMODE_SWCTRL,
1719                 },
1720         },
1721 };
1722
1723 /*
1724  * 'uart' class
1725  * universal asynchronous receiver/transmitter (uart)
1726  */
1727
1728 static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
1729         .rev_offs       = 0x0050,
1730         .sysc_offs      = 0x0054,
1731         .syss_offs      = 0x0058,
1732         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1733                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1734                            SYSS_HAS_RESET_STATUS),
1735         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1736                            SIDLE_SMART_WKUP),
1737         .sysc_fields    = &omap_hwmod_sysc_type1,
1738 };
1739
1740 static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
1741         .name   = "uart",
1742         .sysc   = &omap54xx_uart_sysc,
1743 };
1744
1745 /* uart1 */
1746 static struct omap_hwmod omap54xx_uart1_hwmod = {
1747         .name           = "uart1",
1748         .class          = &omap54xx_uart_hwmod_class,
1749         .clkdm_name     = "l4per_clkdm",
1750         .main_clk       = "func_48m_fclk",
1751         .prcm = {
1752                 .omap4 = {
1753                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1754                         .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1755                         .modulemode   = MODULEMODE_SWCTRL,
1756                 },
1757         },
1758 };
1759
1760 /* uart2 */
1761 static struct omap_hwmod omap54xx_uart2_hwmod = {
1762         .name           = "uart2",
1763         .class          = &omap54xx_uart_hwmod_class,
1764         .clkdm_name     = "l4per_clkdm",
1765         .main_clk       = "func_48m_fclk",
1766         .prcm = {
1767                 .omap4 = {
1768                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1769                         .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1770                         .modulemode   = MODULEMODE_SWCTRL,
1771                 },
1772         },
1773 };
1774
1775 /* uart3 */
1776 static struct omap_hwmod omap54xx_uart3_hwmod = {
1777         .name           = "uart3",
1778         .class          = &omap54xx_uart_hwmod_class,
1779         .clkdm_name     = "l4per_clkdm",
1780         .flags          = DEBUG_OMAP4UART3_FLAGS,
1781         .main_clk       = "func_48m_fclk",
1782         .prcm = {
1783                 .omap4 = {
1784                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1785                         .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1786                         .modulemode   = MODULEMODE_SWCTRL,
1787                 },
1788         },
1789 };
1790
1791 /* uart4 */
1792 static struct omap_hwmod omap54xx_uart4_hwmod = {
1793         .name           = "uart4",
1794         .class          = &omap54xx_uart_hwmod_class,
1795         .clkdm_name     = "l4per_clkdm",
1796         .flags          = DEBUG_OMAP4UART4_FLAGS,
1797         .main_clk       = "func_48m_fclk",
1798         .prcm = {
1799                 .omap4 = {
1800                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1801                         .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1802                         .modulemode   = MODULEMODE_SWCTRL,
1803                 },
1804         },
1805 };
1806
1807 /* uart5 */
1808 static struct omap_hwmod omap54xx_uart5_hwmod = {
1809         .name           = "uart5",
1810         .class          = &omap54xx_uart_hwmod_class,
1811         .clkdm_name     = "l4per_clkdm",
1812         .main_clk       = "func_48m_fclk",
1813         .prcm = {
1814                 .omap4 = {
1815                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1816                         .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1817                         .modulemode   = MODULEMODE_SWCTRL,
1818                 },
1819         },
1820 };
1821
1822 /* uart6 */
1823 static struct omap_hwmod omap54xx_uart6_hwmod = {
1824         .name           = "uart6",
1825         .class          = &omap54xx_uart_hwmod_class,
1826         .clkdm_name     = "l4per_clkdm",
1827         .main_clk       = "func_48m_fclk",
1828         .prcm = {
1829                 .omap4 = {
1830                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
1831                         .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
1832                         .modulemode   = MODULEMODE_SWCTRL,
1833                 },
1834         },
1835 };
1836
1837 /*
1838  * 'usb_host_hs' class
1839  * high-speed multi-port usb host controller
1840  */
1841
1842 static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
1843         .rev_offs       = 0x0000,
1844         .sysc_offs      = 0x0010,
1845         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1846                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1847                            SYSC_HAS_RESET_STATUS),
1848         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1849                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1850                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1851         .sysc_fields    = &omap_hwmod_sysc_type2,
1852 };
1853
1854 static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
1855         .name   = "usb_host_hs",
1856         .sysc   = &omap54xx_usb_host_hs_sysc,
1857 };
1858
1859 static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
1860         .name           = "usb_host_hs",
1861         .class          = &omap54xx_usb_host_hs_hwmod_class,
1862         .clkdm_name     = "l3init_clkdm",
1863         /*
1864          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1865          * id: i660
1866          *
1867          * Description:
1868          * In the following configuration :
1869          * - USBHOST module is set to smart-idle mode
1870          * - PRCM asserts idle_req to the USBHOST module ( This typically
1871          *   happens when the system is going to a low power mode : all ports
1872          *   have been suspended, the master part of the USBHOST module has
1873          *   entered the standby state, and SW has cut the functional clocks)
1874          * - an USBHOST interrupt occurs before the module is able to answer
1875          *   idle_ack, typically a remote wakeup IRQ.
1876          * Then the USB HOST module will enter a deadlock situation where it
1877          * is no more accessible nor functional.
1878          *
1879          * Workaround:
1880          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1881          */
1882
1883         /*
1884          * Errata: USB host EHCI may stall when entering smart-standby mode
1885          * Id: i571
1886          *
1887          * Description:
1888          * When the USBHOST module is set to smart-standby mode, and when it is
1889          * ready to enter the standby state (i.e. all ports are suspended and
1890          * all attached devices are in suspend mode), then it can wrongly assert
1891          * the Mstandby signal too early while there are still some residual OCP
1892          * transactions ongoing. If this condition occurs, the internal state
1893          * machine may go to an undefined state and the USB link may be stuck
1894          * upon the next resume.
1895          *
1896          * Workaround:
1897          * Don't use smart standby; use only force standby,
1898          * hence HWMOD_SWSUP_MSTANDBY
1899          */
1900
1901         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1902         .main_clk       = "l3init_60m_fclk",
1903         .prcm = {
1904                 .omap4 = {
1905                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
1906                         .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
1907                         .modulemode   = MODULEMODE_SWCTRL,
1908                 },
1909         },
1910 };
1911
1912 /*
1913  * 'usb_tll_hs' class
1914  * usb_tll_hs module is the adapter on the usb_host_hs ports
1915  */
1916
1917 static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
1918         .rev_offs       = 0x0000,
1919         .sysc_offs      = 0x0010,
1920         .syss_offs      = 0x0014,
1921         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1922                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1923                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1924         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1925         .sysc_fields    = &omap_hwmod_sysc_type1,
1926 };
1927
1928 static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
1929         .name   = "usb_tll_hs",
1930         .sysc   = &omap54xx_usb_tll_hs_sysc,
1931 };
1932
1933 static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
1934         .name           = "usb_tll_hs",
1935         .class          = &omap54xx_usb_tll_hs_hwmod_class,
1936         .clkdm_name     = "l3init_clkdm",
1937         .main_clk       = "l4_root_clk_div",
1938         .prcm = {
1939                 .omap4 = {
1940                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
1941                         .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
1942                         .modulemode   = MODULEMODE_HWCTRL,
1943                 },
1944         },
1945 };
1946
1947 /*
1948  * 'usb_otg_ss' class
1949  * 2.0 super speed (usb_otg_ss) controller
1950  */
1951
1952 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
1953         .rev_offs       = 0x0000,
1954         .sysc_offs      = 0x0010,
1955         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1956                            SYSC_HAS_SIDLEMODE),
1957         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1958                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1959                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1960         .sysc_fields    = &omap_hwmod_sysc_type2,
1961 };
1962
1963 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
1964         .name   = "usb_otg_ss",
1965         .sysc   = &omap54xx_usb_otg_ss_sysc,
1966 };
1967
1968 /* usb_otg_ss */
1969 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
1970         { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
1971 };
1972
1973 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
1974         .name           = "usb_otg_ss",
1975         .class          = &omap54xx_usb_otg_ss_hwmod_class,
1976         .clkdm_name     = "l3init_clkdm",
1977         .flags          = HWMOD_SWSUP_SIDLE,
1978         .main_clk       = "dpll_core_h13x2_ck",
1979         .prcm = {
1980                 .omap4 = {
1981                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
1982                         .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
1983                         .modulemode   = MODULEMODE_HWCTRL,
1984                 },
1985         },
1986         .opt_clks       = usb_otg_ss_opt_clks,
1987         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss_opt_clks),
1988 };
1989
1990 /*
1991  * 'wd_timer' class
1992  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1993  * overflow condition
1994  */
1995
1996 static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
1997         .rev_offs       = 0x0000,
1998         .sysc_offs      = 0x0010,
1999         .syss_offs      = 0x0014,
2000         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2001                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2002         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2003                            SIDLE_SMART_WKUP),
2004         .sysc_fields    = &omap_hwmod_sysc_type1,
2005 };
2006
2007 static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
2008         .name           = "wd_timer",
2009         .sysc           = &omap54xx_wd_timer_sysc,
2010         .pre_shutdown   = &omap2_wd_timer_disable,
2011 };
2012
2013 /* wd_timer2 */
2014 static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
2015         .name           = "wd_timer2",
2016         .class          = &omap54xx_wd_timer_hwmod_class,
2017         .clkdm_name     = "wkupaon_clkdm",
2018         .main_clk       = "sys_32k_ck",
2019         .prcm = {
2020                 .omap4 = {
2021                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2022                         .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2023                         .modulemode   = MODULEMODE_SWCTRL,
2024                 },
2025         },
2026 };
2027
2028 /*
2029  * 'ocp2scp' class
2030  * bridge to transform ocp interface protocol to scp (serial control port)
2031  * protocol
2032  */
2033 /* ocp2scp3 */
2034 static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
2035 /* l4_cfg -> ocp2scp3 */
2036 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
2037         .master         = &omap54xx_l4_cfg_hwmod,
2038         .slave          = &omap54xx_ocp2scp3_hwmod,
2039         .clk            = "l4_root_clk_div",
2040         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2041 };
2042
2043 static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
2044         .name           = "ocp2scp3",
2045         .class          = &omap54xx_ocp2scp_hwmod_class,
2046         .clkdm_name     = "l3init_clkdm",
2047         .prcm = {
2048                 .omap4 = {
2049                         .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
2050                         .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
2051                         .modulemode   = MODULEMODE_HWCTRL,
2052                 },
2053         },
2054 };
2055
2056 /*
2057  * 'sata' class
2058  * sata:  serial ata interface  gen2 compliant   ( 1 rx/ 1 tx)
2059  */
2060
2061 static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
2062         .sysc_offs      = 0x0000,
2063         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2064         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2065                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2066                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2067         .sysc_fields    = &omap_hwmod_sysc_type2,
2068 };
2069
2070 static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
2071         .name   = "sata",
2072         .sysc   = &omap54xx_sata_sysc,
2073 };
2074
2075 /* sata */
2076 static struct omap_hwmod omap54xx_sata_hwmod = {
2077         .name           = "sata",
2078         .class          = &omap54xx_sata_hwmod_class,
2079         .clkdm_name     = "l3init_clkdm",
2080         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2081         .main_clk       = "func_48m_fclk",
2082         .mpu_rt_idx     = 1,
2083         .prcm = {
2084                 .omap4 = {
2085                         .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2086                         .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2087                         .modulemode   = MODULEMODE_SWCTRL,
2088                 },
2089         },
2090 };
2091
2092 /* l4_cfg -> sata */
2093 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
2094         .master         = &omap54xx_l4_cfg_hwmod,
2095         .slave          = &omap54xx_sata_hwmod,
2096         .clk            = "l3_iclk_div",
2097         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2098 };
2099
2100 /*
2101  * Interfaces
2102  */
2103
2104 /* l3_main_1 -> dmm */
2105 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
2106         .master         = &omap54xx_l3_main_1_hwmod,
2107         .slave          = &omap54xx_dmm_hwmod,
2108         .clk            = "l3_iclk_div",
2109         .user           = OCP_USER_SDMA,
2110 };
2111
2112 /* l3_main_3 -> l3_instr */
2113 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
2114         .master         = &omap54xx_l3_main_3_hwmod,
2115         .slave          = &omap54xx_l3_instr_hwmod,
2116         .clk            = "l3_iclk_div",
2117         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2118 };
2119
2120 /* l3_main_2 -> l3_main_1 */
2121 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
2122         .master         = &omap54xx_l3_main_2_hwmod,
2123         .slave          = &omap54xx_l3_main_1_hwmod,
2124         .clk            = "l3_iclk_div",
2125         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2126 };
2127
2128 /* l4_cfg -> l3_main_1 */
2129 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
2130         .master         = &omap54xx_l4_cfg_hwmod,
2131         .slave          = &omap54xx_l3_main_1_hwmod,
2132         .clk            = "l3_iclk_div",
2133         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2134 };
2135
2136 /* l4_cfg -> mmu_dsp */
2137 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = {
2138         .master         = &omap54xx_l4_cfg_hwmod,
2139         .slave          = &omap54xx_mmu_dsp_hwmod,
2140         .clk            = "l4_root_clk_div",
2141         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2142 };
2143
2144 /* mpu -> l3_main_1 */
2145 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
2146         .master         = &omap54xx_mpu_hwmod,
2147         .slave          = &omap54xx_l3_main_1_hwmod,
2148         .clk            = "l3_iclk_div",
2149         .user           = OCP_USER_MPU,
2150 };
2151
2152 /* l3_main_1 -> l3_main_2 */
2153 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
2154         .master         = &omap54xx_l3_main_1_hwmod,
2155         .slave          = &omap54xx_l3_main_2_hwmod,
2156         .clk            = "l3_iclk_div",
2157         .user           = OCP_USER_MPU,
2158 };
2159
2160 /* l4_cfg -> l3_main_2 */
2161 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
2162         .master         = &omap54xx_l4_cfg_hwmod,
2163         .slave          = &omap54xx_l3_main_2_hwmod,
2164         .clk            = "l3_iclk_div",
2165         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2166 };
2167
2168 /* l3_main_2 -> mmu_ipu */
2169 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = {
2170         .master         = &omap54xx_l3_main_2_hwmod,
2171         .slave          = &omap54xx_mmu_ipu_hwmod,
2172         .clk            = "l3_iclk_div",
2173         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2174 };
2175
2176 /* l3_main_1 -> l3_main_3 */
2177 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
2178         .master         = &omap54xx_l3_main_1_hwmod,
2179         .slave          = &omap54xx_l3_main_3_hwmod,
2180         .clk            = "l3_iclk_div",
2181         .user           = OCP_USER_MPU,
2182 };
2183
2184 /* l3_main_2 -> l3_main_3 */
2185 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
2186         .master         = &omap54xx_l3_main_2_hwmod,
2187         .slave          = &omap54xx_l3_main_3_hwmod,
2188         .clk            = "l3_iclk_div",
2189         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2190 };
2191
2192 /* l4_cfg -> l3_main_3 */
2193 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
2194         .master         = &omap54xx_l4_cfg_hwmod,
2195         .slave          = &omap54xx_l3_main_3_hwmod,
2196         .clk            = "l3_iclk_div",
2197         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2198 };
2199
2200 /* l3_main_1 -> l4_abe */
2201 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
2202         .master         = &omap54xx_l3_main_1_hwmod,
2203         .slave          = &omap54xx_l4_abe_hwmod,
2204         .clk            = "abe_iclk",
2205         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2206 };
2207
2208 /* mpu -> l4_abe */
2209 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
2210         .master         = &omap54xx_mpu_hwmod,
2211         .slave          = &omap54xx_l4_abe_hwmod,
2212         .clk            = "abe_iclk",
2213         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2214 };
2215
2216 /* l3_main_1 -> l4_cfg */
2217 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
2218         .master         = &omap54xx_l3_main_1_hwmod,
2219         .slave          = &omap54xx_l4_cfg_hwmod,
2220         .clk            = "l4_root_clk_div",
2221         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2222 };
2223
2224 /* l3_main_2 -> l4_per */
2225 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
2226         .master         = &omap54xx_l3_main_2_hwmod,
2227         .slave          = &omap54xx_l4_per_hwmod,
2228         .clk            = "l4_root_clk_div",
2229         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2230 };
2231
2232 /* l3_main_1 -> l4_wkup */
2233 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
2234         .master         = &omap54xx_l3_main_1_hwmod,
2235         .slave          = &omap54xx_l4_wkup_hwmod,
2236         .clk            = "wkupaon_iclk_mux",
2237         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2238 };
2239
2240 /* mpu -> mpu_private */
2241 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
2242         .master         = &omap54xx_mpu_hwmod,
2243         .slave          = &omap54xx_mpu_private_hwmod,
2244         .clk            = "l3_iclk_div",
2245         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2246 };
2247
2248 /* l4_wkup -> counter_32k */
2249 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
2250         .master         = &omap54xx_l4_wkup_hwmod,
2251         .slave          = &omap54xx_counter_32k_hwmod,
2252         .clk            = "wkupaon_iclk_mux",
2253         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2254 };
2255
2256 static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
2257         {
2258                 .pa_start       = 0x4a056000,
2259                 .pa_end         = 0x4a056fff,
2260                 .flags          = ADDR_TYPE_RT
2261         },
2262         { }
2263 };
2264
2265 /* l4_cfg -> dma_system */
2266 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
2267         .master         = &omap54xx_l4_cfg_hwmod,
2268         .slave          = &omap54xx_dma_system_hwmod,
2269         .clk            = "l4_root_clk_div",
2270         .addr           = omap54xx_dma_system_addrs,
2271         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2272 };
2273
2274 /* l4_abe -> dmic */
2275 static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
2276         .master         = &omap54xx_l4_abe_hwmod,
2277         .slave          = &omap54xx_dmic_hwmod,
2278         .clk            = "abe_iclk",
2279         .user           = OCP_USER_MPU,
2280 };
2281
2282 /* l3_main_2 -> dss */
2283 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = {
2284         .master         = &omap54xx_l3_main_2_hwmod,
2285         .slave          = &omap54xx_dss_hwmod,
2286         .clk            = "l3_iclk_div",
2287         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2288 };
2289
2290 /* l3_main_2 -> dss_dispc */
2291 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc = {
2292         .master         = &omap54xx_l3_main_2_hwmod,
2293         .slave          = &omap54xx_dss_dispc_hwmod,
2294         .clk            = "l3_iclk_div",
2295         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2296 };
2297
2298 /* l3_main_2 -> dss_dsi1_a */
2299 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a = {
2300         .master         = &omap54xx_l3_main_2_hwmod,
2301         .slave          = &omap54xx_dss_dsi1_a_hwmod,
2302         .clk            = "l3_iclk_div",
2303         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2304 };
2305
2306 /* l3_main_2 -> dss_dsi1_c */
2307 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c = {
2308         .master         = &omap54xx_l3_main_2_hwmod,
2309         .slave          = &omap54xx_dss_dsi1_c_hwmod,
2310         .clk            = "l3_iclk_div",
2311         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2312 };
2313
2314 /* l3_main_2 -> dss_hdmi */
2315 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi = {
2316         .master         = &omap54xx_l3_main_2_hwmod,
2317         .slave          = &omap54xx_dss_hdmi_hwmod,
2318         .clk            = "l3_iclk_div",
2319         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2320 };
2321
2322 /* l3_main_2 -> dss_rfbi */
2323 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi = {
2324         .master         = &omap54xx_l3_main_2_hwmod,
2325         .slave          = &omap54xx_dss_rfbi_hwmod,
2326         .clk            = "l3_iclk_div",
2327         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2328 };
2329
2330 /* mpu -> emif1 */
2331 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
2332         .master         = &omap54xx_mpu_hwmod,
2333         .slave          = &omap54xx_emif1_hwmod,
2334         .clk            = "dpll_core_h11x2_ck",
2335         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2336 };
2337
2338 /* mpu -> emif2 */
2339 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
2340         .master         = &omap54xx_mpu_hwmod,
2341         .slave          = &omap54xx_emif2_hwmod,
2342         .clk            = "dpll_core_h11x2_ck",
2343         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2344 };
2345
2346 /* l4_wkup -> gpio1 */
2347 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
2348         .master         = &omap54xx_l4_wkup_hwmod,
2349         .slave          = &omap54xx_gpio1_hwmod,
2350         .clk            = "wkupaon_iclk_mux",
2351         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2352 };
2353
2354 /* l4_per -> gpio2 */
2355 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
2356         .master         = &omap54xx_l4_per_hwmod,
2357         .slave          = &omap54xx_gpio2_hwmod,
2358         .clk            = "l4_root_clk_div",
2359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2360 };
2361
2362 /* l4_per -> gpio3 */
2363 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
2364         .master         = &omap54xx_l4_per_hwmod,
2365         .slave          = &omap54xx_gpio3_hwmod,
2366         .clk            = "l4_root_clk_div",
2367         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2368 };
2369
2370 /* l4_per -> gpio4 */
2371 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
2372         .master         = &omap54xx_l4_per_hwmod,
2373         .slave          = &omap54xx_gpio4_hwmod,
2374         .clk            = "l4_root_clk_div",
2375         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2376 };
2377
2378 /* l4_per -> gpio5 */
2379 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
2380         .master         = &omap54xx_l4_per_hwmod,
2381         .slave          = &omap54xx_gpio5_hwmod,
2382         .clk            = "l4_root_clk_div",
2383         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2384 };
2385
2386 /* l4_per -> gpio6 */
2387 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
2388         .master         = &omap54xx_l4_per_hwmod,
2389         .slave          = &omap54xx_gpio6_hwmod,
2390         .clk            = "l4_root_clk_div",
2391         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2392 };
2393
2394 /* l4_per -> gpio7 */
2395 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
2396         .master         = &omap54xx_l4_per_hwmod,
2397         .slave          = &omap54xx_gpio7_hwmod,
2398         .clk            = "l4_root_clk_div",
2399         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2400 };
2401
2402 /* l4_per -> gpio8 */
2403 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
2404         .master         = &omap54xx_l4_per_hwmod,
2405         .slave          = &omap54xx_gpio8_hwmod,
2406         .clk            = "l4_root_clk_div",
2407         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2408 };
2409
2410 /* l4_per -> i2c1 */
2411 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
2412         .master         = &omap54xx_l4_per_hwmod,
2413         .slave          = &omap54xx_i2c1_hwmod,
2414         .clk            = "l4_root_clk_div",
2415         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2416 };
2417
2418 /* l4_per -> i2c2 */
2419 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
2420         .master         = &omap54xx_l4_per_hwmod,
2421         .slave          = &omap54xx_i2c2_hwmod,
2422         .clk            = "l4_root_clk_div",
2423         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2424 };
2425
2426 /* l4_per -> i2c3 */
2427 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
2428         .master         = &omap54xx_l4_per_hwmod,
2429         .slave          = &omap54xx_i2c3_hwmod,
2430         .clk            = "l4_root_clk_div",
2431         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2432 };
2433
2434 /* l4_per -> i2c4 */
2435 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
2436         .master         = &omap54xx_l4_per_hwmod,
2437         .slave          = &omap54xx_i2c4_hwmod,
2438         .clk            = "l4_root_clk_div",
2439         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2440 };
2441
2442 /* l4_per -> i2c5 */
2443 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
2444         .master         = &omap54xx_l4_per_hwmod,
2445         .slave          = &omap54xx_i2c5_hwmod,
2446         .clk            = "l4_root_clk_div",
2447         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2448 };
2449
2450 /* l4_wkup -> kbd */
2451 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
2452         .master         = &omap54xx_l4_wkup_hwmod,
2453         .slave          = &omap54xx_kbd_hwmod,
2454         .clk            = "wkupaon_iclk_mux",
2455         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2456 };
2457
2458 /* l4_cfg -> mailbox */
2459 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
2460         .master         = &omap54xx_l4_cfg_hwmod,
2461         .slave          = &omap54xx_mailbox_hwmod,
2462         .clk            = "l4_root_clk_div",
2463         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2464 };
2465
2466 /* l4_abe -> mcbsp1 */
2467 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
2468         .master         = &omap54xx_l4_abe_hwmod,
2469         .slave          = &omap54xx_mcbsp1_hwmod,
2470         .clk            = "abe_iclk",
2471         .user           = OCP_USER_MPU,
2472 };
2473
2474 /* l4_abe -> mcbsp2 */
2475 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
2476         .master         = &omap54xx_l4_abe_hwmod,
2477         .slave          = &omap54xx_mcbsp2_hwmod,
2478         .clk            = "abe_iclk",
2479         .user           = OCP_USER_MPU,
2480 };
2481
2482 /* l4_abe -> mcbsp3 */
2483 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
2484         .master         = &omap54xx_l4_abe_hwmod,
2485         .slave          = &omap54xx_mcbsp3_hwmod,
2486         .clk            = "abe_iclk",
2487         .user           = OCP_USER_MPU,
2488 };
2489
2490 /* l4_abe -> mcpdm */
2491 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
2492         .master         = &omap54xx_l4_abe_hwmod,
2493         .slave          = &omap54xx_mcpdm_hwmod,
2494         .clk            = "abe_iclk",
2495         .user           = OCP_USER_MPU,
2496 };
2497
2498 /* l4_per -> mcspi1 */
2499 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
2500         .master         = &omap54xx_l4_per_hwmod,
2501         .slave          = &omap54xx_mcspi1_hwmod,
2502         .clk            = "l4_root_clk_div",
2503         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2504 };
2505
2506 /* l4_per -> mcspi2 */
2507 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
2508         .master         = &omap54xx_l4_per_hwmod,
2509         .slave          = &omap54xx_mcspi2_hwmod,
2510         .clk            = "l4_root_clk_div",
2511         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2512 };
2513
2514 /* l4_per -> mcspi3 */
2515 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
2516         .master         = &omap54xx_l4_per_hwmod,
2517         .slave          = &omap54xx_mcspi3_hwmod,
2518         .clk            = "l4_root_clk_div",
2519         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2520 };
2521
2522 /* l4_per -> mcspi4 */
2523 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
2524         .master         = &omap54xx_l4_per_hwmod,
2525         .slave          = &omap54xx_mcspi4_hwmod,
2526         .clk            = "l4_root_clk_div",
2527         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2528 };
2529
2530 /* l4_per -> mmc1 */
2531 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
2532         .master         = &omap54xx_l4_per_hwmod,
2533         .slave          = &omap54xx_mmc1_hwmod,
2534         .clk            = "l3_iclk_div",
2535         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2536 };
2537
2538 /* l4_per -> mmc2 */
2539 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
2540         .master         = &omap54xx_l4_per_hwmod,
2541         .slave          = &omap54xx_mmc2_hwmod,
2542         .clk            = "l3_iclk_div",
2543         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2544 };
2545
2546 /* l4_per -> mmc3 */
2547 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
2548         .master         = &omap54xx_l4_per_hwmod,
2549         .slave          = &omap54xx_mmc3_hwmod,
2550         .clk            = "l4_root_clk_div",
2551         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2552 };
2553
2554 /* l4_per -> mmc4 */
2555 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
2556         .master         = &omap54xx_l4_per_hwmod,
2557         .slave          = &omap54xx_mmc4_hwmod,
2558         .clk            = "l4_root_clk_div",
2559         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2560 };
2561
2562 /* l4_per -> mmc5 */
2563 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
2564         .master         = &omap54xx_l4_per_hwmod,
2565         .slave          = &omap54xx_mmc5_hwmod,
2566         .clk            = "l4_root_clk_div",
2567         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2568 };
2569
2570 /* l4_cfg -> mpu */
2571 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
2572         .master         = &omap54xx_l4_cfg_hwmod,
2573         .slave          = &omap54xx_mpu_hwmod,
2574         .clk            = "l4_root_clk_div",
2575         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2576 };
2577
2578 /* l4_cfg -> spinlock */
2579 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = {
2580         .master         = &omap54xx_l4_cfg_hwmod,
2581         .slave          = &omap54xx_spinlock_hwmod,
2582         .clk            = "l4_root_clk_div",
2583         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2584 };
2585
2586 /* l4_cfg -> ocp2scp1 */
2587 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = {
2588         .master         = &omap54xx_l4_cfg_hwmod,
2589         .slave          = &omap54xx_ocp2scp1_hwmod,
2590         .clk            = "l4_root_clk_div",
2591         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2592 };
2593
2594 /* l4_wkup -> timer1 */
2595 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
2596         .master         = &omap54xx_l4_wkup_hwmod,
2597         .slave          = &omap54xx_timer1_hwmod,
2598         .clk            = "wkupaon_iclk_mux",
2599         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2600 };
2601
2602 /* l4_per -> timer2 */
2603 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
2604         .master         = &omap54xx_l4_per_hwmod,
2605         .slave          = &omap54xx_timer2_hwmod,
2606         .clk            = "l4_root_clk_div",
2607         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2608 };
2609
2610 /* l4_per -> timer3 */
2611 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
2612         .master         = &omap54xx_l4_per_hwmod,
2613         .slave          = &omap54xx_timer3_hwmod,
2614         .clk            = "l4_root_clk_div",
2615         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2616 };
2617
2618 /* l4_per -> timer4 */
2619 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
2620         .master         = &omap54xx_l4_per_hwmod,
2621         .slave          = &omap54xx_timer4_hwmod,
2622         .clk            = "l4_root_clk_div",
2623         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2624 };
2625
2626 /* l4_abe -> timer5 */
2627 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
2628         .master         = &omap54xx_l4_abe_hwmod,
2629         .slave          = &omap54xx_timer5_hwmod,
2630         .clk            = "abe_iclk",
2631         .user           = OCP_USER_MPU,
2632 };
2633
2634 /* l4_abe -> timer6 */
2635 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
2636         .master         = &omap54xx_l4_abe_hwmod,
2637         .slave          = &omap54xx_timer6_hwmod,
2638         .clk            = "abe_iclk",
2639         .user           = OCP_USER_MPU,
2640 };
2641
2642 /* l4_abe -> timer7 */
2643 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
2644         .master         = &omap54xx_l4_abe_hwmod,
2645         .slave          = &omap54xx_timer7_hwmod,
2646         .clk            = "abe_iclk",
2647         .user           = OCP_USER_MPU,
2648 };
2649
2650 /* l4_abe -> timer8 */
2651 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
2652         .master         = &omap54xx_l4_abe_hwmod,
2653         .slave          = &omap54xx_timer8_hwmod,
2654         .clk            = "abe_iclk",
2655         .user           = OCP_USER_MPU,
2656 };
2657
2658 /* l4_per -> timer9 */
2659 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
2660         .master         = &omap54xx_l4_per_hwmod,
2661         .slave          = &omap54xx_timer9_hwmod,
2662         .clk            = "l4_root_clk_div",
2663         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2664 };
2665
2666 /* l4_per -> timer10 */
2667 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
2668         .master         = &omap54xx_l4_per_hwmod,
2669         .slave          = &omap54xx_timer10_hwmod,
2670         .clk            = "l4_root_clk_div",
2671         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2672 };
2673
2674 /* l4_per -> timer11 */
2675 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
2676         .master         = &omap54xx_l4_per_hwmod,
2677         .slave          = &omap54xx_timer11_hwmod,
2678         .clk            = "l4_root_clk_div",
2679         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2680 };
2681
2682 /* l4_per -> uart1 */
2683 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
2684         .master         = &omap54xx_l4_per_hwmod,
2685         .slave          = &omap54xx_uart1_hwmod,
2686         .clk            = "l4_root_clk_div",
2687         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2688 };
2689
2690 /* l4_per -> uart2 */
2691 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
2692         .master         = &omap54xx_l4_per_hwmod,
2693         .slave          = &omap54xx_uart2_hwmod,
2694         .clk            = "l4_root_clk_div",
2695         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2696 };
2697
2698 /* l4_per -> uart3 */
2699 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
2700         .master         = &omap54xx_l4_per_hwmod,
2701         .slave          = &omap54xx_uart3_hwmod,
2702         .clk            = "l4_root_clk_div",
2703         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2704 };
2705
2706 /* l4_per -> uart4 */
2707 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
2708         .master         = &omap54xx_l4_per_hwmod,
2709         .slave          = &omap54xx_uart4_hwmod,
2710         .clk            = "l4_root_clk_div",
2711         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2712 };
2713
2714 /* l4_per -> uart5 */
2715 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
2716         .master         = &omap54xx_l4_per_hwmod,
2717         .slave          = &omap54xx_uart5_hwmod,
2718         .clk            = "l4_root_clk_div",
2719         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2720 };
2721
2722 /* l4_per -> uart6 */
2723 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
2724         .master         = &omap54xx_l4_per_hwmod,
2725         .slave          = &omap54xx_uart6_hwmod,
2726         .clk            = "l4_root_clk_div",
2727         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2728 };
2729
2730 /* l4_cfg -> usb_host_hs */
2731 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
2732         .master         = &omap54xx_l4_cfg_hwmod,
2733         .slave          = &omap54xx_usb_host_hs_hwmod,
2734         .clk            = "l3_iclk_div",
2735         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2736 };
2737
2738 /* l4_cfg -> usb_tll_hs */
2739 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
2740         .master         = &omap54xx_l4_cfg_hwmod,
2741         .slave          = &omap54xx_usb_tll_hs_hwmod,
2742         .clk            = "l4_root_clk_div",
2743         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2744 };
2745
2746 /* l4_cfg -> usb_otg_ss */
2747 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
2748         .master         = &omap54xx_l4_cfg_hwmod,
2749         .slave          = &omap54xx_usb_otg_ss_hwmod,
2750         .clk            = "dpll_core_h13x2_ck",
2751         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2752 };
2753
2754 /* l4_wkup -> wd_timer2 */
2755 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
2756         .master         = &omap54xx_l4_wkup_hwmod,
2757         .slave          = &omap54xx_wd_timer2_hwmod,
2758         .clk            = "wkupaon_iclk_mux",
2759         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2760 };
2761
2762 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
2763         &omap54xx_l3_main_1__dmm,
2764         &omap54xx_l3_main_3__l3_instr,
2765         &omap54xx_l3_main_2__l3_main_1,
2766         &omap54xx_l4_cfg__l3_main_1,
2767         &omap54xx_mpu__l3_main_1,
2768         &omap54xx_l3_main_1__l3_main_2,
2769         &omap54xx_l4_cfg__l3_main_2,
2770         &omap54xx_l3_main_1__l3_main_3,
2771         &omap54xx_l3_main_2__l3_main_3,
2772         &omap54xx_l4_cfg__l3_main_3,
2773         &omap54xx_l3_main_1__l4_abe,
2774         &omap54xx_mpu__l4_abe,
2775         &omap54xx_l3_main_1__l4_cfg,
2776         &omap54xx_l3_main_2__l4_per,
2777         &omap54xx_l3_main_1__l4_wkup,
2778         &omap54xx_mpu__mpu_private,
2779         &omap54xx_l4_wkup__counter_32k,
2780         &omap54xx_l4_cfg__dma_system,
2781         &omap54xx_l4_abe__dmic,
2782         &omap54xx_l4_cfg__mmu_dsp,
2783         &omap54xx_l3_main_2__dss,
2784         &omap54xx_l3_main_2__dss_dispc,
2785         &omap54xx_l3_main_2__dss_dsi1_a,
2786         &omap54xx_l3_main_2__dss_dsi1_c,
2787         &omap54xx_l3_main_2__dss_hdmi,
2788         &omap54xx_l3_main_2__dss_rfbi,
2789         &omap54xx_mpu__emif1,
2790         &omap54xx_mpu__emif2,
2791         &omap54xx_l4_wkup__gpio1,
2792         &omap54xx_l4_per__gpio2,
2793         &omap54xx_l4_per__gpio3,
2794         &omap54xx_l4_per__gpio4,
2795         &omap54xx_l4_per__gpio5,
2796         &omap54xx_l4_per__gpio6,
2797         &omap54xx_l4_per__gpio7,
2798         &omap54xx_l4_per__gpio8,
2799         &omap54xx_l4_per__i2c1,
2800         &omap54xx_l4_per__i2c2,
2801         &omap54xx_l4_per__i2c3,
2802         &omap54xx_l4_per__i2c4,
2803         &omap54xx_l4_per__i2c5,
2804         &omap54xx_l3_main_2__mmu_ipu,
2805         &omap54xx_l4_wkup__kbd,
2806         &omap54xx_l4_cfg__mailbox,
2807         &omap54xx_l4_abe__mcbsp1,
2808         &omap54xx_l4_abe__mcbsp2,
2809         &omap54xx_l4_abe__mcbsp3,
2810         &omap54xx_l4_abe__mcpdm,
2811         &omap54xx_l4_per__mcspi1,
2812         &omap54xx_l4_per__mcspi2,
2813         &omap54xx_l4_per__mcspi3,
2814         &omap54xx_l4_per__mcspi4,
2815         &omap54xx_l4_per__mmc1,
2816         &omap54xx_l4_per__mmc2,
2817         &omap54xx_l4_per__mmc3,
2818         &omap54xx_l4_per__mmc4,
2819         &omap54xx_l4_per__mmc5,
2820         &omap54xx_l4_cfg__mpu,
2821         &omap54xx_l4_cfg__spinlock,
2822         &omap54xx_l4_cfg__ocp2scp1,
2823         &omap54xx_l4_wkup__timer1,
2824         &omap54xx_l4_per__timer2,
2825         &omap54xx_l4_per__timer3,
2826         &omap54xx_l4_per__timer4,
2827         &omap54xx_l4_abe__timer5,
2828         &omap54xx_l4_abe__timer6,
2829         &omap54xx_l4_abe__timer7,
2830         &omap54xx_l4_abe__timer8,
2831         &omap54xx_l4_per__timer9,
2832         &omap54xx_l4_per__timer10,
2833         &omap54xx_l4_per__timer11,
2834         &omap54xx_l4_per__uart1,
2835         &omap54xx_l4_per__uart2,
2836         &omap54xx_l4_per__uart3,
2837         &omap54xx_l4_per__uart4,
2838         &omap54xx_l4_per__uart5,
2839         &omap54xx_l4_per__uart6,
2840         &omap54xx_l4_cfg__usb_host_hs,
2841         &omap54xx_l4_cfg__usb_tll_hs,
2842         &omap54xx_l4_cfg__usb_otg_ss,
2843         &omap54xx_l4_wkup__wd_timer2,
2844         &omap54xx_l4_cfg__ocp2scp3,
2845         &omap54xx_l4_cfg__sata,
2846         NULL,
2847 };
2848
2849 int __init omap54xx_hwmod_init(void)
2850 {
2851         omap_hwmod_init();
2852         return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
2853 }