arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/pm.h>
  22 #include <linux/suspend.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28 #include <linux/clk.h>
  29 #include <linux/delay.h>
  30 #include <linux/slab.h>
  31 #include <linux/console.h>
  32 #include <trace/events/power.h>
  33
  34 #include <asm/suspend.h>
  35
  36 #include <plat/sram.h>
  37 #include "clockdomain.h"
  38 #include "powerdomain.h"
  39 #include <plat/serial.h>
  40 #include <plat/sdrc.h>
  41 #include <plat/prcm.h>
  42 #include <plat/gpmc.h>
  43 #include <plat/dma.h>
  44
  45 #include "common.h"
  46 #include "cm2xxx_3xxx.h"
  47 #include "cm-regbits-34xx.h"
  48 #include "prm-regbits-34xx.h"
  49
  50 #include "prm2xxx_3xxx.h"
  51 #include "pm.h"
  52 #include "sdrc.h"
  53 #include "control.h"
  54
  55 #ifdef CONFIG_SUSPEND
  56 static suspend_state_t suspend_state = PM_SUSPEND_ON;
  57 static inline bool is_suspending(void)
  58 {
  59         return (suspend_state != PM_SUSPEND_ON) && console_suspend_enabled;
  60 }
  61 #else
  62 static inline bool is_suspending(void)
  63 {
  64         return false;
  65 }
  66 #endif
  67
  68 /* pm34xx errata defined in pm.h */
  69 u16 pm34xx_errata;
  70
  71 struct power_state {
  72         struct powerdomain *pwrdm;
  73         u32 next_state;
  74 #ifdef CONFIG_SUSPEND
  75         u32 saved_state;
  76 #endif
  77         struct list_head node;
  78 };
  79
  80 static LIST_HEAD(pwrst_list);
  81
  82 static int (*_omap_save_secure_sram)(u32 *addr);
  83 void (*omap3_do_wfi_sram)(void);
  84
  85 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  86 static struct powerdomain *core_pwrdm, *per_pwrdm;
  87 static struct powerdomain *cam_pwrdm;
  88
  89 static inline void omap3_per_save_context(void)
  90 {
  91         omap_gpio_save_context();
  92 }
  93
  94 static inline void omap3_per_restore_context(void)
  95 {
  96         omap_gpio_restore_context();
  97 }
  98
  99 static void omap3_enable_io_chain(void)
 100 {
 101         int timeout = 0;
 102
 103         omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 104                                    PM_WKEN);
 105         /* Do a readback to assure write has been done */
 106         omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 107
 108         while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
 109                  OMAP3430_ST_IO_CHAIN_MASK)) {
 110                 timeout++;
 111                 if (timeout > 1000) {
 112                         pr_err("Wake up daisy chain activation failed.\n");
 113                         return;
 114                 }
 115                 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
 116                                            WKUP_MOD, PM_WKEN);
 117         }
 118 }
 119
 120 static void omap3_disable_io_chain(void)
 121 {
 122         omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 123                                      PM_WKEN);
 124 }
 125
 126 static void omap3_core_save_context(void)
 127 {
 128         omap3_ctrl_save_padconf();
 129
 130         /*
 131          * Force write last pad into memory, as this can fail in some
 132          * cases according to errata 1.157, 1.185
 133          */
 134         omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
 135                 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
 136
 137         /* Save the Interrupt controller context */
 138         omap_intc_save_context();
 139         /* Save the GPMC context */
 140         omap3_gpmc_save_context();
 141         /* Save the system control module context, padconf already save above*/
 142         omap3_control_save_context();
 143         omap_dma_global_context_save();
 144 }
 145
 146 static void omap3_core_restore_context(void)
 147 {
 148         /* Restore the control module context, padconf restored by h/w */
 149         omap3_control_restore_context();
 150         /* Restore the GPMC context */
 151         omap3_gpmc_restore_context();
 152         /* Restore the interrupt controller context */
 153         omap_intc_restore_context();
 154         omap_dma_global_context_restore();
 155 }
 156
 157 /*
 158  * FIXME: This function should be called before entering off-mode after
 159  * OMAP3 secure services have been accessed. Currently it is only called
 160  * once during boot sequence, but this works as we are not using secure
 161  * services.
 162  */
 163 static void omap3_save_secure_ram_context(void)
 164 {
 165         u32 ret;
 166         int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 167
 168         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 169                 /*
 170                  * MPU next state must be set to POWER_ON temporarily,
 171                  * otherwise the WFI executed inside the ROM code
 172                  * will hang the system.
 173                  */
 174                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 175                 ret = _omap_save_secure_sram((u32 *)
 176                                 __pa(omap3_secure_ram_storage));
 177                 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
 178                 /* Following is for error tracking, it should not happen */
 179                 if (ret) {
 180                         printk(KERN_ERR "save_secure_sram() returns %08x\n",
 181                                 ret);
 182                         while (1)
 183                                 ;
 184                 }
 185         }
 186 }
 187
 188 /*
 189  * PRCM Interrupt Handler Helper Function
 190  *
 191  * The purpose of this function is to clear any wake-up events latched
 192  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 193  * may occur whilst attempting to clear a PM_WKST_x register and thus
 194  * set another bit in this register. A while loop is used to ensure
 195  * that any peripheral wake-up events occurring while attempting to
 196  * clear the PM_WKST_x are detected and cleared.
 197  */
 198 static int prcm_clear_mod_irqs(s16 module, u8 regs)
 199 {
 200         u32 wkst, fclk, iclk, clken;
 201         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 202         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 203         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 204         u16 grpsel_off = (regs == 3) ?
 205                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 206         int c = 0;
 207
 208         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 209         wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
 210         if (wkst) {
 211                 iclk = omap2_cm_read_mod_reg(module, iclk_off);
 212                 fclk = omap2_cm_read_mod_reg(module, fclk_off);
 213                 while (wkst) {
 214                         clken = wkst;
 215                         omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
 216                         /*
 217                          * For USBHOST, we don't know whether HOST1 or
 218                          * HOST2 woke us up, so enable both f-clocks
 219                          */
 220                         if (module == OMAP3430ES2_USBHOST_MOD)
 221                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 222                         omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
 223                         omap2_prm_write_mod_reg(wkst, module, wkst_off);
 224                         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 225                         c++;
 226                 }
 227                 omap2_cm_write_mod_reg(iclk, module, iclk_off);
 228                 omap2_cm_write_mod_reg(fclk, module, fclk_off);
 229         }
 230
 231         return c;
 232 }
 233
 234 static int _prcm_int_handle_wakeup(void)
 235 {
 236         int c;
 237
 238         c = prcm_clear_mod_irqs(WKUP_MOD, 1);
 239         c += prcm_clear_mod_irqs(CORE_MOD, 1);
 240         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
 241         if (omap_rev() > OMAP3430_REV_ES1_0) {
 242                 c += prcm_clear_mod_irqs(CORE_MOD, 3);
 243                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
 244         }
 245
 246         return c;
 247 }
 248
 249 /*
 250  * PRCM Interrupt Handler
 251  *
 252  * The PRM_IRQSTATUS_MPU register indicates if there are any pending
 253  * interrupts from the PRCM for the MPU. These bits must be cleared in
 254  * order to clear the PRCM interrupt. The PRCM interrupt handler is
 255  * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
 256  * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
 257  * register indicates that a wake-up event is pending for the MPU and
 258  * this bit can only be cleared if the all the wake-up events latched
 259  * in the various PM_WKST_x registers have been cleared. The interrupt
 260  * handler is implemented using a do-while loop so that if a wake-up
 261  * event occurred during the processing of the prcm interrupt handler
 262  * (setting a bit in the corresponding PM_WKST_x register and thus
 263  * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
 264  * this would be handled.
 265  */
 266 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 267 {
 268         u32 irqenable_mpu, irqstatus_mpu;
 269         int c = 0;
 270
 271         irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 272                                          OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 273         irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 274                                          OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 275         irqstatus_mpu &= irqenable_mpu;
 276
 277         do {
 278                 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
 279                                      OMAP3430_IO_ST_MASK)) {
 280                         c = _prcm_int_handle_wakeup();
 281
 282                         /*
 283                          * Is the MPU PRCM interrupt handler racing with the
 284                          * IVA2 PRCM interrupt handler ?
 285                          */
 286                         WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
 287                              "but no wakeup sources are marked\n");
 288                 } else {
 289                         /* XXX we need to expand our PRCM interrupt handler */
 290                         WARN(1, "prcm: WARNING: PRCM interrupt received, but "
 291                              "no code to handle it (%08x)\n", irqstatus_mpu);
 292                 }
 293
 294                 omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 295                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 296
 297                 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 298                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 299                 irqstatus_mpu &= irqenable_mpu;
 300
 301         } while (irqstatus_mpu);
 302
 303         return IRQ_HANDLED;
 304 }
 305
 306 static void omap34xx_save_context(u32 *save)
 307 {
 308         u32 val;
 309
 310         /* Read Auxiliary Control Register */
 311         asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
 312         *save++ = 1;
 313         *save++ = val;
 314
 315         /* Read L2 AUX ctrl register */
 316         asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
 317         *save++ = 1;
 318         *save++ = val;
 319 }
 320
 321 static int omap34xx_do_sram_idle(unsigned long save_state)
 322 {
 323         omap34xx_cpu_suspend(save_state);
 324         return 0;
 325 }
 326
 327 void omap_sram_idle(void)
 328 {
 329         /* Variable to tell what needs to be saved and restored
 330          * in omap_sram_idle*/
 331         /* save_state = 0 => Nothing to save and restored */
 332         /* save_state = 1 => Only L1 and logic lost */
 333         /* save_state = 2 => Only L2 lost */
 334         /* save_state = 3 => L1, L2 and logic lost */
 335         int save_state = 0;
 336         int mpu_next_state = PWRDM_POWER_ON;
 337         int per_next_state = PWRDM_POWER_ON;
 338         int core_next_state = PWRDM_POWER_ON;
 339         int per_going_off;
 340         int core_prev_state, per_prev_state;
 341         u32 sdrc_pwr = 0;
 342
 343         pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
 344         pwrdm_clear_all_prev_pwrst(neon_pwrdm);
 345         pwrdm_clear_all_prev_pwrst(core_pwrdm);
 346         pwrdm_clear_all_prev_pwrst(per_pwrdm);
 347
 348         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 349         switch (mpu_next_state) {
 350         case PWRDM_POWER_ON:
 351         case PWRDM_POWER_RET:
 352                 /* No need to save context */
 353                 save_state = 0;
 354                 break;
 355         case PWRDM_POWER_OFF:
 356                 save_state = 3;
 357                 break;
 358         default:
 359                 /* Invalid state */
 360                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 361                 return;
 362         }
 363
 364         /* NEON control */
 365         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 366                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
 367
 368         /* Enable IO-PAD and IO-CHAIN wakeups */
 369         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 370         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 371         if (omap3_has_io_wakeup() &&
 372             (per_next_state < PWRDM_POWER_ON ||
 373              core_next_state < PWRDM_POWER_ON)) {
 374                 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
 375                 if (omap3_has_io_chain_ctrl())
 376                         omap3_enable_io_chain();
 377         }
 378
 379         /* Block console output in case it is on one of the OMAP UARTs */
 380         if (!is_suspending())
 381                 if (per_next_state < PWRDM_POWER_ON ||
 382                     core_next_state < PWRDM_POWER_ON)
 383                         if (!console_trylock())
 384                                 goto console_still_active;
 385
 386         pwrdm_pre_transition();
 387
 388         /* PER */
 389         if (per_next_state < PWRDM_POWER_ON) {
 390                 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
 391                 omap_uart_prepare_idle(2);
 392                 omap_uart_prepare_idle(3);
 393                 omap2_gpio_prepare_for_idle(per_going_off);
 394                 if (per_next_state == PWRDM_POWER_OFF)
 395                                 omap3_per_save_context();
 396         }
 397
 398         /* CORE */
 399         if (core_next_state < PWRDM_POWER_ON) {
 400                 omap_uart_prepare_idle(0);
 401                 omap_uart_prepare_idle(1);
 402                 if (core_next_state == PWRDM_POWER_OFF) {
 403                         omap3_core_save_context();
 404                         omap3_cm_save_context();
 405                 }
 406         }
 407
 408         omap3_intc_prepare_idle();
 409
 410         /*
 411          * On EMU/HS devices ROM code restores a SRDC value
 412          * from scratchpad which has automatic self refresh on timeout
 413          * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
 414          * Hence store/restore the SDRC_POWER register here.
 415          */
 416         if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
 417             (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
 418              omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
 419             core_next_state == PWRDM_POWER_OFF)
 420                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 421
 422         /*
 423          * omap3_arm_context is the location where some ARM context
 424          * get saved. The rest is placed on the stack, and restored
 425          * from there before resuming.
 426          */
 427         if (save_state)
 428                 omap34xx_save_context(omap3_arm_context);
 429         if (save_state == 1 || save_state == 3)
 430                 cpu_suspend(save_state, omap34xx_do_sram_idle);
 431         else
 432                 omap34xx_do_sram_idle(save_state);
 433
 434         /* Restore normal SDRC POWER settings */
 435         if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
 436             (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
 437              omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
 438             core_next_state == PWRDM_POWER_OFF)
 439                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 440
 441         /* CORE */
 442         if (core_next_state < PWRDM_POWER_ON) {
 443                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 444                 if (core_prev_state == PWRDM_POWER_OFF) {
 445                         omap3_core_restore_context();
 446                         omap3_cm_restore_context();
 447                         omap3_sram_restore_context();
 448                         omap2_sms_restore_context();
 449                 }
 450                 omap_uart_resume_idle(0);
 451                 omap_uart_resume_idle(1);
 452                 if (core_next_state == PWRDM_POWER_OFF)
 453                         omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
 454                                                OMAP3430_GR_MOD,
 455                                                OMAP3_PRM_VOLTCTRL_OFFSET);
 456         }
 457         omap3_intc_resume_idle();
 458
 459         pwrdm_post_transition();
 460
 461         /* PER */
 462         if (per_next_state < PWRDM_POWER_ON) {
 463                 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
 464                 omap2_gpio_resume_after_idle();
 465                 if (per_prev_state == PWRDM_POWER_OFF)
 466                         omap3_per_restore_context();
 467                 omap_uart_resume_idle(2);
 468                 omap_uart_resume_idle(3);
 469         }
 470
 471         if (!is_suspending())
 472                 console_unlock();
 473
 474 console_still_active:
 475         /* Disable IO-PAD and IO-CHAIN wakeup */
 476         if (omap3_has_io_wakeup() &&
 477             (per_next_state < PWRDM_POWER_ON ||
 478              core_next_state < PWRDM_POWER_ON)) {
 479                 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
 480                                              PM_WKEN);
 481                 if (omap3_has_io_chain_ctrl())
 482                         omap3_disable_io_chain();
 483         }
 484
 485         clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 486 }
 487
 488 int omap3_can_sleep(void)
 489 {
 490         if (!omap_uart_can_sleep())
 491                 return 0;
 492         return 1;
 493 }
 494
 495 static void omap3_pm_idle(void)
 496 {
 497         local_irq_disable();
 498         local_fiq_disable();
 499
 500         if (!omap3_can_sleep())
 501                 goto out;
 502
 503         if (omap_irq_pending() || need_resched())
 504                 goto out;
 505
 506         trace_power_start(POWER_CSTATE, 1, smp_processor_id());
 507         trace_cpu_idle(1, smp_processor_id());
 508
 509         omap_sram_idle();
 510
 511         trace_power_end(smp_processor_id());
 512         trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
 513
 514 out:
 515         local_fiq_enable();
 516         local_irq_enable();
 517 }
 518
 519 #ifdef CONFIG_SUSPEND
 520 static int omap3_pm_suspend(void)
 521 {
 522         struct power_state *pwrst;
 523         int state, ret = 0;
 524
 525         /* Read current next_pwrsts */
 526         list_for_each_entry(pwrst, &pwrst_list, node)
 527                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 528         /* Set ones wanted by suspend */
 529         list_for_each_entry(pwrst, &pwrst_list, node) {
 530                 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 531                         goto restore;
 532                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 533                         goto restore;
 534         }
 535
 536         omap_uart_prepare_suspend();
 537         omap3_intc_suspend();
 538
 539         omap_sram_idle();
 540
 541 restore:
 542         /* Restore next_pwrsts */
 543         list_for_each_entry(pwrst, &pwrst_list, node) {
 544                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 545                 if (state > pwrst->next_state) {
 546                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 547                                "target state %d\n",
 548                                pwrst->pwrdm->name, pwrst->next_state);
 549                         ret = -1;
 550                 }
 551                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 552         }
 553         if (ret)
 554                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 555         else
 556                 printk(KERN_INFO "Successfully put all powerdomains "
 557                        "to target state\n");
 558
 559         return ret;
 560 }
 561
 562 static int omap3_pm_enter(suspend_state_t unused)
 563 {
 564         int ret = 0;
 565
 566         switch (suspend_state) {
 567         case PM_SUSPEND_STANDBY:
 568         case PM_SUSPEND_MEM:
 569                 ret = omap3_pm_suspend();
 570                 break;
 571         default:
 572                 ret = -EINVAL;
 573         }
 574
 575         return ret;
 576 }
 577
 578 /* Hooks to enable / disable UART interrupts during suspend */
 579 static int omap3_pm_begin(suspend_state_t state)
 580 {
 581         disable_hlt();
 582         suspend_state = state;
 583         omap_uart_enable_irqs(0);
 584         return 0;
 585 }
 586
 587 static void omap3_pm_end(void)
 588 {
 589         suspend_state = PM_SUSPEND_ON;
 590         omap_uart_enable_irqs(1);
 591         enable_hlt();
 592         return;
 593 }
 594
 595 static const struct platform_suspend_ops omap_pm_ops = {
 596         .begin          = omap3_pm_begin,
 597         .end            = omap3_pm_end,
 598         .enter          = omap3_pm_enter,
 599         .valid          = suspend_valid_only_mem,
 600 };
 601 #endif /* CONFIG_SUSPEND */
 602
 603
 604 /**
 605  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 606  *                   retention
 607  *
 608  * In cases where IVA2 is activated by bootcode, it may prevent
 609  * full-chip retention or off-mode because it is not idle.  This
 610  * function forces the IVA2 into idle state so it can go
 611  * into retention/off and thus allow full-chip retention/off.
 612  *
 613  **/
 614 static void __init omap3_iva_idle(void)
 615 {
 616         /* ensure IVA2 clock is disabled */
 617         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 618
 619         /* if no clock activity, nothing else to do */
 620         if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 621               OMAP3430_CLKACTIVITY_IVA2_MASK))
 622                 return;
 623
 624         /* Reset IVA2 */
 625         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 626                           OMAP3430_RST2_IVA2_MASK |
 627                           OMAP3430_RST3_IVA2_MASK,
 628                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 629
 630         /* Enable IVA2 clock */
 631         omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
 632                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 633
 634         /* Set IVA2 boot mode to 'idle' */
 635         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 636                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 637
 638         /* Un-reset IVA2 */
 639         omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 640
 641         /* Disable IVA2 clock */
 642         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 643
 644         /* Reset IVA2 */
 645         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 646                           OMAP3430_RST2_IVA2_MASK |
 647                           OMAP3430_RST3_IVA2_MASK,
 648                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 649 }
 650
 651 static void __init omap3_d2d_idle(void)
 652 {
 653         u16 mask, padconf;
 654
 655         /* In a stand alone OMAP3430 where there is not a stacked
 656          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 657          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 658          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 659         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 660         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 661         padconf |= mask;
 662         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 663
 664         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 665         padconf |= mask;
 666         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 667
 668         /* reset modem */
 669         omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
 670                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
 671                           CORE_MOD, OMAP2_RM_RSTCTRL);
 672         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 673 }
 674
 675 static void __init prcm_setup_regs(void)
 676 {
 677         u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
 678                                         OMAP3630_EN_UART4_MASK : 0;
 679         u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
 680                                         OMAP3630_GRPSEL_UART4_MASK : 0;
 681
 682         /* XXX This should be handled by hwmod code or SCM init code */
 683         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 684
 685         /*
 686          * Enable control of expternal oscillator through
 687          * sys_clkreq. In the long run clock framework should
 688          * take care of this.
 689          */
 690         omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 691                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 692                              OMAP3430_GR_MOD,
 693                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 694
 695         /* setup wakup source */
 696         omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
 697                           OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
 698                           WKUP_MOD, PM_WKEN);
 699         /* No need to write EN_IO, that is always enabled */
 700         omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
 701                           OMAP3430_GRPSEL_GPT1_MASK |
 702                           OMAP3430_GRPSEL_GPT12_MASK,
 703                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 704         /* For some reason IO doesn't generate wakeup event even if
 705          * it is selected to mpu wakeup goup */
 706         omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
 707                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 708
 709         /* Enable PM_WKEN to support DSS LPR */
 710         omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
 711                                 OMAP3430_DSS_MOD, PM_WKEN);
 712
 713         /* Enable wakeups in PER */
 714         omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
 715                           OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
 716                           OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
 717                           OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
 718                           OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
 719                           OMAP3430_EN_MCBSP4_MASK,
 720                           OMAP3430_PER_MOD, PM_WKEN);
 721         /* and allow them to wake up MPU */
 722         omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
 723                           OMAP3430_GRPSEL_GPIO2_MASK |
 724                           OMAP3430_GRPSEL_GPIO3_MASK |
 725                           OMAP3430_GRPSEL_GPIO4_MASK |
 726                           OMAP3430_GRPSEL_GPIO5_MASK |
 727                           OMAP3430_GRPSEL_GPIO6_MASK |
 728                           OMAP3430_GRPSEL_UART3_MASK |
 729                           OMAP3430_GRPSEL_MCBSP2_MASK |
 730                           OMAP3430_GRPSEL_MCBSP3_MASK |
 731                           OMAP3430_GRPSEL_MCBSP4_MASK,
 732                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 733
 734         /* Don't attach IVA interrupts */
 735         omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 736         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 737         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 738         omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 739
 740         /* Clear any pending 'reset' flags */
 741         omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
 742         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
 743         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
 744         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
 745         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
 746         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
 747         omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
 748
 749         /* Clear any pending PRCM interrupts */
 750         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 751
 752         omap3_iva_idle();
 753         omap3_d2d_idle();
 754 }
 755
 756 void omap3_pm_off_mode_enable(int enable)
 757 {
 758         struct power_state *pwrst;
 759         u32 state;
 760
 761         if (enable)
 762                 state = PWRDM_POWER_OFF;
 763         else
 764                 state = PWRDM_POWER_RET;
 765
 766         list_for_each_entry(pwrst, &pwrst_list, node) {
 767                 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
 768                                 pwrst->pwrdm == core_pwrdm &&
 769                                 state == PWRDM_POWER_OFF) {
 770                         pwrst->next_state = PWRDM_POWER_RET;
 771                         pr_warn("%s: Core OFF disabled due to errata i583\n",
 772                                 __func__);
 773                 } else {
 774                         pwrst->next_state = state;
 775                 }
 776                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 777         }
 778 }
 779
 780 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 781 {
 782         struct power_state *pwrst;
 783
 784         list_for_each_entry(pwrst, &pwrst_list, node) {
 785                 if (pwrst->pwrdm == pwrdm)
 786                         return pwrst->next_state;
 787         }
 788         return -EINVAL;
 789 }
 790
 791 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 792 {
 793         struct power_state *pwrst;
 794
 795         list_for_each_entry(pwrst, &pwrst_list, node) {
 796                 if (pwrst->pwrdm == pwrdm) {
 797                         pwrst->next_state = state;
 798                         return 0;
 799                 }
 800         }
 801         return -EINVAL;
 802 }
 803
 804 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 805 {
 806         struct power_state *pwrst;
 807
 808         if (!pwrdm->pwrsts)
 809                 return 0;
 810
 811         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 812         if (!pwrst)
 813                 return -ENOMEM;
 814         pwrst->pwrdm = pwrdm;
 815         pwrst->next_state = PWRDM_POWER_RET;
 816         list_add(&pwrst->node, &pwrst_list);
 817
 818         if (pwrdm_has_hdwr_sar(pwrdm))
 819                 pwrdm_enable_hdwr_sar(pwrdm);
 820
 821         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 822 }
 823
 824 /*
 825  * Enable hw supervised mode for all clockdomains if it's
 826  * supported. Initiate sleep transition for other clockdomains, if
 827  * they are not used
 828  */
 829 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 830 {
 831         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 832                 clkdm_allow_idle(clkdm);
 833         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 834                  atomic_read(&clkdm->usecount) == 0)
 835                 clkdm_sleep(clkdm);
 836         return 0;
 837 }
 838
 839 /*
 840  * Push functions to SRAM
 841  *
 842  * The minimum set of functions is pushed to SRAM for execution:
 843  * - omap3_do_wfi for erratum i581 WA,
 844  * - save_secure_ram_context for security extensions.
 845  */
 846 void omap_push_sram_idle(void)
 847 {
 848         omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
 849
 850         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
 851                 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
 852                                 save_secure_ram_context_sz);
 853 }
 854
 855 static void __init pm_errata_configure(void)
 856 {
 857         if (cpu_is_omap3630()) {
 858                 pm34xx_errata |= PM_RTA_ERRATUM_i608;
 859                 /* Enable the l2 cache toggling in sleep logic */
 860                 enable_omap3630_toggle_l2_on_restore();
 861                 if (omap_rev() < OMAP3630_REV_ES1_2)
 862                         pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
 863         }
 864 }
 865
 866 static int __init omap3_pm_init(void)
 867 {
 868         struct power_state *pwrst, *tmp;
 869         struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
 870         int ret;
 871
 872         if (!cpu_is_omap34xx())
 873                 return -ENODEV;
 874
 875         if (!omap3_has_io_chain_ctrl())
 876                 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
 877
 878         pm_errata_configure();
 879
 880         /* XXX prcm_setup_regs needs to be before enabling hw
 881          * supervised mode for powerdomains */
 882         prcm_setup_regs();
 883
 884         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
 885                           (irq_handler_t)prcm_interrupt_handler,
 886                           IRQF_DISABLED, "prcm", NULL);
 887         if (ret) {
 888                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
 889                        INT_34XX_PRCM_MPU_IRQ);
 890                 goto err1;
 891         }
 892
 893         ret = pwrdm_for_each(pwrdms_setup, NULL);
 894         if (ret) {
 895                 printk(KERN_ERR "Failed to setup powerdomains\n");
 896                 goto err2;
 897         }
 898
 899         (void) clkdm_for_each(clkdms_setup, NULL);
 900
 901         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 902         if (mpu_pwrdm == NULL) {
 903                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
 904                 goto err2;
 905         }
 906
 907         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
 908         per_pwrdm = pwrdm_lookup("per_pwrdm");
 909         core_pwrdm = pwrdm_lookup("core_pwrdm");
 910         cam_pwrdm = pwrdm_lookup("cam_pwrdm");
 911
 912         neon_clkdm = clkdm_lookup("neon_clkdm");
 913         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 914         per_clkdm = clkdm_lookup("per_clkdm");
 915         core_clkdm = clkdm_lookup("core_clkdm");
 916
 917 #ifdef CONFIG_SUSPEND
 918         suspend_set_ops(&omap_pm_ops);
 919 #endif /* CONFIG_SUSPEND */
 920
 921         pm_idle = omap3_pm_idle;
 922         omap3_idle_init();
 923
 924         /*
 925          * RTA is disabled during initialization as per erratum i608
 926          * it is safer to disable RTA by the bootloader, but we would like
 927          * to be doubly sure here and prevent any mishaps.
 928          */
 929         if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
 930                 omap3630_ctrl_disable_rta();
 931
 932         clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
 933         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 934                 omap3_secure_ram_storage =
 935                         kmalloc(0x803F, GFP_KERNEL);
 936                 if (!omap3_secure_ram_storage)
 937                         printk(KERN_ERR "Memory allocation failed when"
 938                                         "allocating for secure sram context\n");
 939
 940                 local_irq_disable();
 941                 local_fiq_disable();
 942
 943                 omap_dma_global_context_save();
 944                 omap3_save_secure_ram_context();
 945                 omap_dma_global_context_restore();
 946
 947                 local_irq_enable();
 948                 local_fiq_enable();
 949         }
 950
 951         omap3_save_scratchpad_contents();
 952 err1:
 953         return ret;
 954 err2:
 955         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
 956         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 957                 list_del(&pwrst->node);
 958                 kfree(pwrst);
 959         }
 960         return ret;
 961 }
 962
 963 late_initcall(omap3_pm_init);