2 * OMAP2/3 PRM module functions
4 * Copyright (C) 2010-2011 Texas Instruments, Inc.
5 * Copyright (C) 2010 Nokia Corporation
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/errno.h>
16 #include <linux/err.h>
19 #include "powerdomain.h"
20 #include "prm2xxx_3xxx.h"
21 #include "prm-regbits-24xx.h"
22 #include "clockdomain.h"
25 * omap2_prm_is_hardreset_asserted - read the HW reset line state of
26 * submodules contained in the hwmod module
27 * @prm_mod: PRM submodule base (e.g. CORE_MOD)
28 * @shift: register bit shift corresponding to the reset line to check
30 * Returns 1 if the (sub)module hardreset line is currently asserted,
31 * 0 if the (sub)module hardreset line is not currently asserted, or
32 * -EINVAL if called while running on a non-OMAP2/3 chip.
34 int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
36 return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
41 * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
42 * @shift: register bit shift corresponding to the reset line to assert
43 * @part: PRM partition, ignored for OMAP2
44 * @prm_mod: PRM submodule base (e.g. CORE_MOD)
45 * @offset: register offset, ignored for OMAP2
47 * Some IPs like dsp or iva contain processors that require an HW
48 * reset line to be asserted / deasserted in order to fully enable the
49 * IP. These modules may have multiple hard-reset lines that reset
50 * different 'submodules' inside the IP block. This function will
51 * place the submodule into reset. Returns 0 upon success or -EINVAL
52 * upon an argument error.
54 int omap2_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset)
59 omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);
65 * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait
66 * @prm_mod: PRM submodule base (e.g. CORE_MOD)
67 * @rst_shift: register bit shift corresponding to the reset line to deassert
68 * @st_shift: register bit shift for the status of the deasserted submodule
69 * @part: PRM partition, not used for OMAP2
70 * @prm_mod: PRM submodule base (e.g. CORE_MOD)
71 * @rst_offset: reset register offset, not used for OMAP2
72 * @st_offset: reset status register offset, not used for OMAP2
74 * Some IPs like dsp or iva contain processors that require an HW
75 * reset line to be asserted / deasserted in order to fully enable the
76 * IP. These modules may have multiple hard-reset lines that reset
77 * different 'submodules' inside the IP block. This function will
78 * take the submodule out of reset and wait until the PRCM indicates
79 * that the reset has completed before returning. Returns 0 upon success or
80 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
81 * of reset, or -EBUSY if the submodule did not exit reset promptly.
83 int omap2_prm_deassert_hardreset(u8 rst_shift, u8 st_shift, u8 part,
84 s16 prm_mod, u16 rst_offset, u16 st_offset)
92 /* Check the current status to avoid de-asserting the line twice */
93 if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, rst) == 0)
96 /* Clear the reset status by writing 1 to the status bit */
97 omap2_prm_rmw_mod_reg_bits(0xffffffff, st, prm_mod, OMAP2_RM_RSTST);
98 /* de-assert the reset control line */
99 omap2_prm_rmw_mod_reg_bits(rst, 0, prm_mod, OMAP2_RM_RSTCTRL);
100 /* wait the status to be set */
101 omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST,
103 MAX_MODULE_HARDRESET_WAIT, c);
105 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
109 /* Powerdomain low-level functions */
111 /* Common functions across OMAP2 and OMAP3 */
112 int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
117 m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
119 omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
125 int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
130 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
132 omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
138 int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
142 m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
144 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST,
148 int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
152 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
154 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
155 OMAP2_PM_PWSTCTRL, m);
158 int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
162 v = pwrst << __ffs(OMAP_LOGICRETSTATE_MASK);
163 omap2_prm_rmw_mod_reg_bits(OMAP_LOGICRETSTATE_MASK, v, pwrdm->prcm_offs,
169 int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
174 * REVISIT: pwrdm_wait_transition() may be better implemented
175 * via a callback and a periodic timer check -- how long do we expect
176 * powerdomain transitions to take?
179 /* XXX Is this udelay() value meaningful? */
180 while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) &
181 OMAP_INTRANSITION_MASK) &&
182 (c++ < PWRDM_TRANSITION_BAILOUT))
185 if (c > PWRDM_TRANSITION_BAILOUT) {
186 pr_err("powerdomain: %s: waited too long to complete transition\n",
191 pr_debug("powerdomain: completed transition in %d loops\n", c);
196 int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
197 struct clockdomain *clkdm2)
199 omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
200 clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
204 int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
205 struct clockdomain *clkdm2)
207 omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
208 clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
212 int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
213 struct clockdomain *clkdm2)
215 return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
216 PM_WKDEP, (1 << clkdm2->dep_bit));
219 /* XXX Caller must hold the clkdm's powerdomain lock */
220 int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
222 struct clkdm_dep *cd;
225 for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
227 continue; /* only happens if data is erroneous */
229 /* PRM accesses are slow, so minimize them */
230 mask |= 1 << cd->clkdm->dep_bit;
231 cd->wkdep_usecount = 0;
234 omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,