4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
22 #include "powerdomain.h"
24 #include "prm-regbits-33xx.h"
26 /* Read a register in a PRM instance */
27 u32 am33xx_prm_read_reg(s16 inst, u16 idx)
29 return readl_relaxed(prm_base + inst + idx);
32 /* Write into a register in a PRM instance */
33 void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
35 writel_relaxed(val, prm_base + inst + idx);
38 /* Read-modify-write a register in PRM. Caller must lock */
39 u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
43 v = am33xx_prm_read_reg(inst, idx);
46 am33xx_prm_write_reg(v, inst, idx);
52 * am33xx_prm_is_hardreset_asserted - read the HW reset line state of
53 * submodules contained in the hwmod module
54 * @shift: register bit shift corresponding to the reset line to check
55 * @part: PRM partition, ignored for AM33xx
56 * @inst: CM instance register offset (*_INST macro)
57 * @rstctrl_offs: RM_RSTCTRL register address offset for this module
59 * Returns 1 if the (sub)module hardreset line is currently asserted,
60 * 0 if the (sub)module hardreset line is not currently asserted, or
61 * -EINVAL upon parameter error.
63 static int am33xx_prm_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
68 v = am33xx_prm_read_reg(inst, rstctrl_offs);
76 * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
77 * @shift: register bit shift corresponding to the reset line to assert
78 * @part: CM partition, ignored for AM33xx
79 * @inst: CM instance register offset (*_INST macro)
80 * @rstctrl_reg: RM_RSTCTRL register address for this module
82 * Some IPs like dsp, ipu or iva contain processors that require an HW
83 * reset line to be asserted / deasserted in order to fully enable the
84 * IP. These modules may have multiple hard-reset lines that reset
85 * different 'submodules' inside the IP block. This function will
86 * place the submodule into reset. Returns 0 upon success or -EINVAL
87 * upon an argument error.
89 static int am33xx_prm_assert_hardreset(u8 shift, u8 part, s16 inst,
92 u32 mask = 1 << shift;
94 am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs);
100 * am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and
102 * @shift: register bit shift corresponding to the reset line to deassert
103 * @st_shift: reset status register bit shift corresponding to the reset line
104 * @part: PRM partition, not used for AM33xx
105 * @inst: CM instance register offset (*_INST macro)
106 * @rstctrl_reg: RM_RSTCTRL register address for this module
107 * @rstst_reg: RM_RSTST register address for this module
109 * Some IPs like dsp, ipu or iva contain processors that require an HW
110 * reset line to be asserted / deasserted in order to fully enable the
111 * IP. These modules may have multiple hard-reset lines that reset
112 * different 'submodules' inside the IP block. This function will
113 * take the submodule out of reset and wait until the PRCM indicates
114 * that the reset has completed before returning. Returns 0 upon success or
115 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
116 * of reset, or -EBUSY if the submodule did not exit reset promptly.
118 static int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part,
119 s16 inst, u16 rstctrl_offs,
123 u32 mask = 1 << st_shift;
125 /* Check the current status to avoid de-asserting the line twice */
126 if (am33xx_prm_is_hardreset_asserted(shift, 0, inst, rstctrl_offs) == 0)
129 /* Clear the reset status by writing 1 to the status bit */
130 am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
132 /* de-assert the reset control line */
135 am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
137 /* wait the status to be set */
138 omap_test_timeout(am33xx_prm_is_hardreset_asserted(st_shift, 0, inst,
140 MAX_MODULE_HARDRESET_WAIT, c);
142 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
145 static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
147 am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK,
148 (pwrst << OMAP_POWERSTATE_SHIFT),
149 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
153 static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
157 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
158 v &= OMAP_POWERSTATE_MASK;
159 v >>= OMAP_POWERSTATE_SHIFT;
164 static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
168 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
169 v &= OMAP_POWERSTATEST_MASK;
170 v >>= OMAP_POWERSTATEST_SHIFT;
175 static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
179 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
180 v &= AM33XX_LASTPOWERSTATEENTERED_MASK;
181 v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT;
186 static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
188 am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK,
189 (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT),
190 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
194 static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
196 am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK,
197 AM33XX_LASTPOWERSTATEENTERED_MASK,
198 pwrdm->prcm_offs, pwrdm->pwrstst_offs);
202 static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
206 m = pwrdm->logicretstate_mask;
210 am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
211 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
216 static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
220 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
221 v &= AM33XX_LOGICSTATEST_MASK;
222 v >>= AM33XX_LOGICSTATEST_SHIFT;
227 static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
231 m = pwrdm->logicretstate_mask;
235 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
242 static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
247 m = pwrdm->mem_on_mask[bank];
251 am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
252 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
257 static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
262 m = pwrdm->mem_ret_mask[bank];
266 am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
267 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
272 static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
276 m = pwrdm->mem_pwrst_mask[bank];
280 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
287 static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
291 m = pwrdm->mem_retst_mask[bank];
295 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
302 static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
307 * REVISIT: pwrdm_wait_transition() may be better implemented
308 * via a callback and a periodic timer check -- how long do we expect
309 * powerdomain transitions to take?
312 /* XXX Is this udelay() value meaningful? */
313 while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs)
314 & OMAP_INTRANSITION_MASK) &&
315 (c++ < PWRDM_TRANSITION_BAILOUT))
318 if (c > PWRDM_TRANSITION_BAILOUT) {
319 pr_err("powerdomain: %s: waited too long to complete transition\n",
324 pr_debug("powerdomain: completed transition in %d loops\n", c);
329 static int am33xx_check_vcvp(void)
331 /* No VC/VP on am33xx devices */
335 struct pwrdm_ops am33xx_pwrdm_operations = {
336 .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst,
337 .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst,
338 .pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst,
339 .pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst,
340 .pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst,
341 .pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst,
342 .pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst,
343 .pwrdm_clear_all_prev_pwrst = am33xx_pwrdm_clear_all_prev_pwrst,
344 .pwrdm_set_lowpwrstchange = am33xx_pwrdm_set_lowpwrstchange,
345 .pwrdm_read_mem_pwrst = am33xx_pwrdm_read_mem_pwrst,
346 .pwrdm_read_mem_retst = am33xx_pwrdm_read_mem_retst,
347 .pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst,
348 .pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst,
349 .pwrdm_wait_transition = am33xx_pwrdm_wait_transition,
350 .pwrdm_has_voltdm = am33xx_check_vcvp,
353 static struct prm_ll_data am33xx_prm_ll_data = {
354 .assert_hardreset = am33xx_prm_assert_hardreset,
355 .deassert_hardreset = am33xx_prm_deassert_hardreset,
356 .is_hardreset_asserted = am33xx_prm_is_hardreset_asserted,
359 int __init am33xx_prm_init(void)
361 return prm_register(&am33xx_prm_ll_data);
364 static void __exit am33xx_prm_exit(void)
366 prm_unregister(&am33xx_prm_ll_data);
368 __exitcall(am33xx_prm_exit);