4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
22 #include "powerdomain.h"
24 #include "prm-regbits-33xx.h"
26 /* Read a register in a PRM instance */
27 u32 am33xx_prm_read_reg(s16 inst, u16 idx)
29 return readl_relaxed(prm_base + inst + idx);
32 /* Write into a register in a PRM instance */
33 void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
35 writel_relaxed(val, prm_base + inst + idx);
38 /* Read-modify-write a register in PRM. Caller must lock */
39 u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
43 v = am33xx_prm_read_reg(inst, idx);
46 am33xx_prm_write_reg(v, inst, idx);
52 * am33xx_prm_is_hardreset_asserted - read the HW reset line state of
53 * submodules contained in the hwmod module
54 * @shift: register bit shift corresponding to the reset line to check
55 * @inst: CM instance register offset (*_INST macro)
56 * @rstctrl_offs: RM_RSTCTRL register address offset for this module
58 * Returns 1 if the (sub)module hardreset line is currently asserted,
59 * 0 if the (sub)module hardreset line is not currently asserted, or
60 * -EINVAL upon parameter error.
62 int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs)
66 v = am33xx_prm_read_reg(inst, rstctrl_offs);
74 * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
75 * @shift: register bit shift corresponding to the reset line to assert
76 * @part: CM partition, ignored for AM33xx
77 * @inst: CM instance register offset (*_INST macro)
78 * @rstctrl_reg: RM_RSTCTRL register address for this module
80 * Some IPs like dsp, ipu or iva contain processors that require an HW
81 * reset line to be asserted / deasserted in order to fully enable the
82 * IP. These modules may have multiple hard-reset lines that reset
83 * different 'submodules' inside the IP block. This function will
84 * place the submodule into reset. Returns 0 upon success or -EINVAL
85 * upon an argument error.
87 static int am33xx_prm_assert_hardreset(u8 shift, u8 part, s16 inst,
90 u32 mask = 1 << shift;
92 am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs);
98 * am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and
100 * @shift: register bit shift corresponding to the reset line to deassert
101 * @st_shift: reset status register bit shift corresponding to the reset line
102 * @part: PRM partition, not used for AM33xx
103 * @inst: CM instance register offset (*_INST macro)
104 * @rstctrl_reg: RM_RSTCTRL register address for this module
105 * @rstst_reg: RM_RSTST register address for this module
107 * Some IPs like dsp, ipu or iva contain processors that require an HW
108 * reset line to be asserted / deasserted in order to fully enable the
109 * IP. These modules may have multiple hard-reset lines that reset
110 * different 'submodules' inside the IP block. This function will
111 * take the submodule out of reset and wait until the PRCM indicates
112 * that the reset has completed before returning. Returns 0 upon success or
113 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
114 * of reset, or -EBUSY if the submodule did not exit reset promptly.
116 static int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part,
117 s16 inst, u16 rstctrl_offs,
121 u32 mask = 1 << st_shift;
123 /* Check the current status to avoid de-asserting the line twice */
124 if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0)
127 /* Clear the reset status by writing 1 to the status bit */
128 am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
130 /* de-assert the reset control line */
133 am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
135 /* wait the status to be set */
136 omap_test_timeout(am33xx_prm_is_hardreset_asserted(st_shift, inst,
138 MAX_MODULE_HARDRESET_WAIT, c);
140 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
143 static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
145 am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK,
146 (pwrst << OMAP_POWERSTATE_SHIFT),
147 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
151 static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
155 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
156 v &= OMAP_POWERSTATE_MASK;
157 v >>= OMAP_POWERSTATE_SHIFT;
162 static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
166 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
167 v &= OMAP_POWERSTATEST_MASK;
168 v >>= OMAP_POWERSTATEST_SHIFT;
173 static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
177 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
178 v &= AM33XX_LASTPOWERSTATEENTERED_MASK;
179 v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT;
184 static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
186 am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK,
187 (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT),
188 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
192 static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
194 am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK,
195 AM33XX_LASTPOWERSTATEENTERED_MASK,
196 pwrdm->prcm_offs, pwrdm->pwrstst_offs);
200 static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
204 m = pwrdm->logicretstate_mask;
208 am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
209 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
214 static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
218 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
219 v &= AM33XX_LOGICSTATEST_MASK;
220 v >>= AM33XX_LOGICSTATEST_SHIFT;
225 static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
229 m = pwrdm->logicretstate_mask;
233 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
240 static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
245 m = pwrdm->mem_on_mask[bank];
249 am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
250 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
255 static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
260 m = pwrdm->mem_ret_mask[bank];
264 am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
265 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
270 static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
274 m = pwrdm->mem_pwrst_mask[bank];
278 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
285 static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
289 m = pwrdm->mem_retst_mask[bank];
293 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
300 static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
305 * REVISIT: pwrdm_wait_transition() may be better implemented
306 * via a callback and a periodic timer check -- how long do we expect
307 * powerdomain transitions to take?
310 /* XXX Is this udelay() value meaningful? */
311 while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs)
312 & OMAP_INTRANSITION_MASK) &&
313 (c++ < PWRDM_TRANSITION_BAILOUT))
316 if (c > PWRDM_TRANSITION_BAILOUT) {
317 pr_err("powerdomain: %s: waited too long to complete transition\n",
322 pr_debug("powerdomain: completed transition in %d loops\n", c);
327 static int am33xx_check_vcvp(void)
329 /* No VC/VP on am33xx devices */
333 struct pwrdm_ops am33xx_pwrdm_operations = {
334 .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst,
335 .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst,
336 .pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst,
337 .pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst,
338 .pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst,
339 .pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst,
340 .pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst,
341 .pwrdm_clear_all_prev_pwrst = am33xx_pwrdm_clear_all_prev_pwrst,
342 .pwrdm_set_lowpwrstchange = am33xx_pwrdm_set_lowpwrstchange,
343 .pwrdm_read_mem_pwrst = am33xx_pwrdm_read_mem_pwrst,
344 .pwrdm_read_mem_retst = am33xx_pwrdm_read_mem_retst,
345 .pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst,
346 .pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst,
347 .pwrdm_wait_transition = am33xx_pwrdm_wait_transition,
348 .pwrdm_has_voltdm = am33xx_check_vcvp,
351 static struct prm_ll_data am33xx_prm_ll_data = {
352 .assert_hardreset = am33xx_prm_assert_hardreset,
353 .deassert_hardreset = am33xx_prm_deassert_hardreset,
356 int __init am33xx_prm_init(void)
358 return prm_register(&am33xx_prm_ll_data);
361 static void __exit am33xx_prm_exit(void)
363 prm_unregister(&am33xx_prm_ll_data);
365 __exitcall(am33xx_prm_exit);