arch/arm/mach-omap2/prm44xx.c

   1 /*
   2  * OMAP4 PRM module functions
   3  *
   4  * Copyright (C) 2011-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2010 Nokia Corporation
   6  * Benoît Cousson
   7  * Paul Walmsley
   8  * Rajendra Nayak <rnayak@ti.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/delay.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/io.h>
  20 #include <linux/of_irq.h>
  21
  22
  23 #include "soc.h"
  24 #include "iomap.h"
  25 #include "common.h"
  26 #include "vp.h"
  27 #include "prm44xx.h"
  28 #include "prm-regbits-44xx.h"
  29 #include "prcm44xx.h"
  30 #include "prminst44xx.h"
  31 #include "powerdomain.h"
  32
  33 /* Static data */
  34
  35 static void omap44xx_prm_read_pending_irqs(unsigned long *events);
  36 static void omap44xx_prm_ocp_barrier(void);
  37 static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
  38 static void omap44xx_prm_restore_irqen(u32 *saved_mask);
  39
  40 static const struct omap_prcm_irq omap4_prcm_irqs[] = {
  41         OMAP_PRCM_IRQ("io",     9,      1),
  42 };
  43
  44 static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
  45         .ack                    = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
  46         .mask                   = OMAP4_PRM_IRQENABLE_MPU_OFFSET,
  47         .nr_regs                = 2,
  48         .irqs                   = omap4_prcm_irqs,
  49         .nr_irqs                = ARRAY_SIZE(omap4_prcm_irqs),
  50         .irq                    = 11 + OMAP44XX_IRQ_GIC_START,
  51         .read_pending_irqs      = &omap44xx_prm_read_pending_irqs,
  52         .ocp_barrier            = &omap44xx_prm_ocp_barrier,
  53         .save_and_clear_irqen   = &omap44xx_prm_save_and_clear_irqen,
  54         .restore_irqen          = &omap44xx_prm_restore_irqen,
  55         .reconfigure_io_chain   = &omap44xx_prm_reconfigure_io_chain,
  56 };
  57
  58 /*
  59  * omap44xx_prm_reset_src_map - map from bits in the PRM_RSTST
  60  *   hardware register (which are specific to OMAP44xx SoCs) to reset
  61  *   source ID bit shifts (which is an OMAP SoC-independent
  62  *   enumeration)
  63  */
  64 static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
  65         { OMAP4430_GLOBAL_WARM_SW_RST_SHIFT,
  66           OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
  67         { OMAP4430_GLOBAL_COLD_RST_SHIFT,
  68           OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
  69         { OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT,
  70           OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
  71         { OMAP4430_MPU_WDT_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
  72         { OMAP4430_SECURE_WDT_RST_SHIFT, OMAP_SECU_WD_RST_SRC_ID_SHIFT },
  73         { OMAP4430_EXTERNAL_WARM_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
  74         { OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT,
  75           OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT },
  76         { OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT,
  77           OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT },
  78         { OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT,
  79           OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT },
  80         { OMAP4430_ICEPICK_RST_SHIFT, OMAP_ICEPICK_RST_SRC_ID_SHIFT },
  81         { OMAP4430_C2C_RST_SHIFT, OMAP_C2C_RST_SRC_ID_SHIFT },
  82         { -1, -1 },
  83 };
  84
  85 /* PRM low-level functions */
  86
  87 /* Read a register in a CM/PRM instance in the PRM module */
  88 static u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
  89 {
  90         return readl_relaxed(prm_base + inst + reg);
  91 }
  92
  93 /* Write into a register in a CM/PRM instance in the PRM module */
  94 static void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
  95 {
  96         writel_relaxed(val, prm_base + inst + reg);
  97 }
  98
  99 /* Read-modify-write a register in a PRM module. Caller must lock */
 100 static u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
 101 {
 102         u32 v;
 103
 104         v = omap4_prm_read_inst_reg(inst, reg);
 105         v &= ~mask;
 106         v |= bits;
 107         omap4_prm_write_inst_reg(v, inst, reg);
 108
 109         return v;
 110 }
 111
 112 /* PRM VP */
 113
 114 /*
 115  * struct omap4_vp - OMAP4 VP register access description.
 116  * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP
 117  * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
 118  */
 119 struct omap4_vp {
 120         u32 irqstatus_mpu;
 121         u32 tranxdone_status;
 122 };
 123
 124 static struct omap4_vp omap4_vp[] = {
 125         [OMAP4_VP_VDD_MPU_ID] = {
 126                 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
 127                 .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
 128         },
 129         [OMAP4_VP_VDD_IVA_ID] = {
 130                 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
 131                 .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
 132         },
 133         [OMAP4_VP_VDD_CORE_ID] = {
 134                 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
 135                 .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
 136         },
 137 };
 138
 139 u32 omap4_prm_vp_check_txdone(u8 vp_id)
 140 {
 141         struct omap4_vp *vp = &omap4_vp[vp_id];
 142         u32 irqstatus;
 143
 144         irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 145                                                 OMAP4430_PRM_OCP_SOCKET_INST,
 146                                                 vp->irqstatus_mpu);
 147         return irqstatus & vp->tranxdone_status;
 148 }
 149
 150 void omap4_prm_vp_clear_txdone(u8 vp_id)
 151 {
 152         struct omap4_vp *vp = &omap4_vp[vp_id];
 153
 154         omap4_prminst_write_inst_reg(vp->tranxdone_status,
 155                                      OMAP4430_PRM_PARTITION,
 156                                      OMAP4430_PRM_OCP_SOCKET_INST,
 157                                      vp->irqstatus_mpu);
 158 };
 159
 160 u32 omap4_prm_vcvp_read(u8 offset)
 161 {
 162         s32 inst = omap4_prmst_get_prm_dev_inst();
 163
 164         if (inst == PRM_INSTANCE_UNKNOWN)
 165                 return 0;
 166
 167         return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 168                                            inst, offset);
 169 }
 170
 171 void omap4_prm_vcvp_write(u32 val, u8 offset)
 172 {
 173         s32 inst = omap4_prmst_get_prm_dev_inst();
 174
 175         if (inst == PRM_INSTANCE_UNKNOWN)
 176                 return;
 177
 178         omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION,
 179                                      inst, offset);
 180 }
 181
 182 u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
 183 {
 184         s32 inst = omap4_prmst_get_prm_dev_inst();
 185
 186         if (inst == PRM_INSTANCE_UNKNOWN)
 187                 return 0;
 188
 189         return omap4_prminst_rmw_inst_reg_bits(mask, bits,
 190                                                OMAP4430_PRM_PARTITION,
 191                                                inst,
 192                                                offset);
 193 }
 194
 195 static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
 196 {
 197         u32 mask, st;
 198
 199         /* XXX read mask from RAM? */
 200         mask = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
 201                                        irqen_offs);
 202         st = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, irqst_offs);
 203
 204         return mask & st;
 205 }
 206
 207 /**
 208  * omap44xx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
 209  * @events: ptr to two consecutive u32s, preallocated by caller
 210  *
 211  * Read PRM_IRQSTATUS_MPU* bits, AND'ed with the currently-enabled PRM
 212  * MPU IRQs, and store the result into the two u32s pointed to by @events.
 213  * No return value.
 214  */
 215 static void omap44xx_prm_read_pending_irqs(unsigned long *events)
 216 {
 217         events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET,
 218                                           OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
 219
 220         events[1] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_2_OFFSET,
 221                                           OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
 222 }
 223
 224 /**
 225  * omap44xx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
 226  *
 227  * Force any buffered writes to the PRM IP block to complete.  Needed
 228  * by the PRM IRQ handler, which reads and writes directly to the IP
 229  * block, to avoid race conditions after acknowledging or clearing IRQ
 230  * bits.  No return value.
 231  */
 232 static void omap44xx_prm_ocp_barrier(void)
 233 {
 234         omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
 235                                 OMAP4_REVISION_PRM_OFFSET);
 236 }
 237
 238 /**
 239  * omap44xx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU* regs
 240  * @saved_mask: ptr to a u32 array to save IRQENABLE bits
 241  *
 242  * Save the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers to
 243  * @saved_mask.  @saved_mask must be allocated by the caller.
 244  * Intended to be used in the PRM interrupt handler suspend callback.
 245  * The OCP barrier is needed to ensure the write to disable PRM
 246  * interrupts reaches the PRM before returning; otherwise, spurious
 247  * interrupts might occur.  No return value.
 248  */
 249 static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
 250 {
 251         saved_mask[0] =
 252                 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
 253                                         OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
 254         saved_mask[1] =
 255                 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
 256                                         OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
 257
 258         omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST,
 259                                  OMAP4_PRM_IRQENABLE_MPU_OFFSET);
 260         omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST,
 261                                  OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
 262
 263         /* OCP barrier */
 264         omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
 265                                 OMAP4_REVISION_PRM_OFFSET);
 266 }
 267
 268 /**
 269  * omap44xx_prm_restore_irqen - set PRM_IRQENABLE_MPU* registers from args
 270  * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
 271  *
 272  * Restore the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers from
 273  * @saved_mask.  Intended to be used in the PRM interrupt handler resume
 274  * callback to restore values saved by omap44xx_prm_save_and_clear_irqen().
 275  * No OCP barrier should be needed here; any pending PRM interrupts will fire
 276  * once the writes reach the PRM.  No return value.
 277  */
 278 static void omap44xx_prm_restore_irqen(u32 *saved_mask)
 279 {
 280         omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_OCP_SOCKET_INST,
 281                                  OMAP4_PRM_IRQENABLE_MPU_OFFSET);
 282         omap4_prm_write_inst_reg(saved_mask[1], OMAP4430_PRM_OCP_SOCKET_INST,
 283                                  OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
 284 }
 285
 286 /**
 287  * omap44xx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
 288  *
 289  * Clear any previously-latched I/O wakeup events and ensure that the
 290  * I/O wakeup gates are aligned with the current mux settings.  Works
 291  * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
 292  * deasserting WUCLKIN and waiting for WUCLKOUT to be deasserted.
 293  * No return value. XXX Are the final two steps necessary?
 294  */
 295 void omap44xx_prm_reconfigure_io_chain(void)
 296 {
 297         int i = 0;
 298         s32 inst = omap4_prmst_get_prm_dev_inst();
 299
 300         if (inst == PRM_INSTANCE_UNKNOWN)
 301                 return;
 302
 303         /* Trigger WUCLKIN enable */
 304         omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK,
 305                                     OMAP4430_WUCLK_CTRL_MASK,
 306                                     inst,
 307                                     OMAP4_PRM_IO_PMCTRL_OFFSET);
 308         omap_test_timeout(
 309                 (((omap4_prm_read_inst_reg(inst,
 310                                            OMAP4_PRM_IO_PMCTRL_OFFSET) &
 311                    OMAP4430_WUCLK_STATUS_MASK) >>
 312                   OMAP4430_WUCLK_STATUS_SHIFT) == 1),
 313                 MAX_IOPAD_LATCH_TIME, i);
 314         if (i == MAX_IOPAD_LATCH_TIME)
 315                 pr_warn("PRM: I/O chain clock line assertion timed out\n");
 316
 317         /* Trigger WUCLKIN disable */
 318         omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0,
 319                                     inst,
 320                                     OMAP4_PRM_IO_PMCTRL_OFFSET);
 321         omap_test_timeout(
 322                 (((omap4_prm_read_inst_reg(inst,
 323                                            OMAP4_PRM_IO_PMCTRL_OFFSET) &
 324                    OMAP4430_WUCLK_STATUS_MASK) >>
 325                   OMAP4430_WUCLK_STATUS_SHIFT) == 0),
 326                 MAX_IOPAD_LATCH_TIME, i);
 327         if (i == MAX_IOPAD_LATCH_TIME)
 328                 pr_warn("PRM: I/O chain clock line deassertion timed out\n");
 329
 330         return;
 331 }
 332
 333 /**
 334  * omap44xx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
 335  *
 336  * Activates the I/O wakeup event latches and allows events logged by
 337  * those latches to signal a wakeup event to the PRCM.  For I/O wakeups
 338  * to occur, WAKEUPENABLE bits must be set in the pad mux registers, and
 339  * omap44xx_prm_reconfigure_io_chain() must be called.  No return value.
 340  */
 341 static void __init omap44xx_prm_enable_io_wakeup(void)
 342 {
 343         s32 inst = omap4_prmst_get_prm_dev_inst();
 344
 345         if (inst == PRM_INSTANCE_UNKNOWN)
 346                 return;
 347
 348         omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
 349                                     OMAP4430_GLOBAL_WUEN_MASK,
 350                                     inst,
 351                                     OMAP4_PRM_IO_PMCTRL_OFFSET);
 352 }
 353
 354 /**
 355  * omap44xx_prm_read_reset_sources - return the last SoC reset source
 356  *
 357  * Return a u32 representing the last reset sources of the SoC.  The
 358  * returned reset source bits are standardized across OMAP SoCs.
 359  */
 360 static u32 omap44xx_prm_read_reset_sources(void)
 361 {
 362         struct prm_reset_src_map *p;
 363         u32 r = 0;
 364         u32 v;
 365         s32 inst = omap4_prmst_get_prm_dev_inst();
 366
 367         if (inst == PRM_INSTANCE_UNKNOWN)
 368                 return 0;
 369
 370
 371         v = omap4_prm_read_inst_reg(inst,
 372                                     OMAP4_RM_RSTST);
 373
 374         p = omap44xx_prm_reset_src_map;
 375         while (p->reg_shift >= 0 && p->std_shift >= 0) {
 376                 if (v & (1 << p->reg_shift))
 377                         r |= 1 << p->std_shift;
 378                 p++;
 379         }
 380
 381         return r;
 382 }
 383
 384 /**
 385  * omap44xx_prm_was_any_context_lost_old - was module hardware context lost?
 386  * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
 387  * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
 388  * @idx: CONTEXT register offset
 389  *
 390  * Return 1 if any bits were set in the *_CONTEXT_* register
 391  * identified by (@part, @inst, @idx), which means that some context
 392  * was lost for that module; otherwise, return 0.
 393  */
 394 static bool omap44xx_prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx)
 395 {
 396         return (omap4_prminst_read_inst_reg(part, inst, idx)) ? 1 : 0;
 397 }
 398
 399 /**
 400  * omap44xx_prm_clear_context_lost_flags_old - clear context loss flags
 401  * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
 402  * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
 403  * @idx: CONTEXT register offset
 404  *
 405  * Clear hardware context loss bits for the module identified by
 406  * (@part, @inst, @idx).  No return value.  XXX Writes to reserved bits;
 407  * is there a way to avoid this?
 408  */
 409 static void omap44xx_prm_clear_context_loss_flags_old(u8 part, s16 inst,
 410                                                       u16 idx)
 411 {
 412         omap4_prminst_write_inst_reg(0xffffffff, part, inst, idx);
 413 }
 414
 415 /* Powerdomain low-level functions */
 416
 417 static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
 418 {
 419         omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
 420                                         (pwrst << OMAP_POWERSTATE_SHIFT),
 421                                         pwrdm->prcm_partition,
 422                                         pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
 423         return 0;
 424 }
 425
 426 static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
 427 {
 428         u32 v;
 429
 430         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 431                                         OMAP4_PM_PWSTCTRL);
 432         v &= OMAP_POWERSTATE_MASK;
 433         v >>= OMAP_POWERSTATE_SHIFT;
 434
 435         return v;
 436 }
 437
 438 static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
 439 {
 440         u32 v;
 441
 442         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 443                                         OMAP4_PM_PWSTST);
 444         v &= OMAP_POWERSTATEST_MASK;
 445         v >>= OMAP_POWERSTATEST_SHIFT;
 446
 447         return v;
 448 }
 449
 450 static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
 451 {
 452         u32 v;
 453
 454         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 455                                         OMAP4_PM_PWSTST);
 456         v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
 457         v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
 458
 459         return v;
 460 }
 461
 462 static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
 463 {
 464         omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
 465                                         (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
 466                                         pwrdm->prcm_partition,
 467                                         pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
 468         return 0;
 469 }
 470
 471 static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
 472 {
 473         omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
 474                                         OMAP4430_LASTPOWERSTATEENTERED_MASK,
 475                                         pwrdm->prcm_partition,
 476                                         pwrdm->prcm_offs, OMAP4_PM_PWSTST);
 477         return 0;
 478 }
 479
 480 static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
 481 {
 482         u32 v;
 483
 484         v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
 485         omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
 486                                         pwrdm->prcm_partition, pwrdm->prcm_offs,
 487                                         OMAP4_PM_PWSTCTRL);
 488
 489         return 0;
 490 }
 491
 492 static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
 493                                     u8 pwrst)
 494 {
 495         u32 m;
 496
 497         m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
 498
 499         omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
 500                                         pwrdm->prcm_partition, pwrdm->prcm_offs,
 501                                         OMAP4_PM_PWSTCTRL);
 502
 503         return 0;
 504 }
 505
 506 static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
 507                                      u8 pwrst)
 508 {
 509         u32 m;
 510
 511         m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
 512
 513         omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
 514                                         pwrdm->prcm_partition, pwrdm->prcm_offs,
 515                                         OMAP4_PM_PWSTCTRL);
 516
 517         return 0;
 518 }
 519
 520 static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
 521 {
 522         u32 v;
 523
 524         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 525                                         OMAP4_PM_PWSTST);
 526         v &= OMAP4430_LOGICSTATEST_MASK;
 527         v >>= OMAP4430_LOGICSTATEST_SHIFT;
 528
 529         return v;
 530 }
 531
 532 static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
 533 {
 534         u32 v;
 535
 536         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 537                                         OMAP4_PM_PWSTCTRL);
 538         v &= OMAP4430_LOGICRETSTATE_MASK;
 539         v >>= OMAP4430_LOGICRETSTATE_SHIFT;
 540
 541         return v;
 542 }
 543
 544 /**
 545  * omap4_pwrdm_read_prev_logic_pwrst - read the previous logic powerstate
 546  * @pwrdm: struct powerdomain * to read the state for
 547  *
 548  * Reads the previous logic powerstate for a powerdomain. This
 549  * function must determine the previous logic powerstate by first
 550  * checking the previous powerstate for the domain. If that was OFF,
 551  * then logic has been lost. If previous state was RETENTION, the
 552  * function reads the setting for the next retention logic state to
 553  * see the actual value.  In every other case, the logic is
 554  * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
 555  * depending whether the logic was retained or not.
 556  */
 557 static int omap4_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
 558 {
 559         int state;
 560
 561         state = omap4_pwrdm_read_prev_pwrst(pwrdm);
 562
 563         if (state == PWRDM_POWER_OFF)
 564                 return PWRDM_POWER_OFF;
 565
 566         if (state != PWRDM_POWER_RET)
 567                 return PWRDM_POWER_RET;
 568
 569         return omap4_pwrdm_read_logic_retst(pwrdm);
 570 }
 571
 572 static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 573 {
 574         u32 m, v;
 575
 576         m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
 577
 578         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 579                                         OMAP4_PM_PWSTST);
 580         v &= m;
 581         v >>= __ffs(m);
 582
 583         return v;
 584 }
 585
 586 static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
 587 {
 588         u32 m, v;
 589
 590         m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
 591
 592         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 593                                         OMAP4_PM_PWSTCTRL);
 594         v &= m;
 595         v >>= __ffs(m);
 596
 597         return v;
 598 }
 599
 600 /**
 601  * omap4_pwrdm_read_prev_mem_pwrst - reads the previous memory powerstate
 602  * @pwrdm: struct powerdomain * to read mem powerstate for
 603  * @bank: memory bank index
 604  *
 605  * Reads the previous memory powerstate for a powerdomain. This
 606  * function must determine the previous memory powerstate by first
 607  * checking the previous powerstate for the domain. If that was OFF,
 608  * then logic has been lost. If previous state was RETENTION, the
 609  * function reads the setting for the next memory retention state to
 610  * see the actual value.  In every other case, the logic is
 611  * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
 612  * depending whether logic was retained or not.
 613  */
 614 static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 615 {
 616         int state;
 617
 618         state = omap4_pwrdm_read_prev_pwrst(pwrdm);
 619
 620         if (state == PWRDM_POWER_OFF)
 621                 return PWRDM_POWER_OFF;
 622
 623         if (state != PWRDM_POWER_RET)
 624                 return PWRDM_POWER_RET;
 625
 626         return omap4_pwrdm_read_mem_retst(pwrdm, bank);
 627 }
 628
 629 static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
 630 {
 631         u32 c = 0;
 632
 633         /*
 634          * REVISIT: pwrdm_wait_transition() may be better implemented
 635          * via a callback and a periodic timer check -- how long do we expect
 636          * powerdomain transitions to take?
 637          */
 638
 639         /* XXX Is this udelay() value meaningful? */
 640         while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
 641                                             pwrdm->prcm_offs,
 642                                             OMAP4_PM_PWSTST) &
 643                 OMAP_INTRANSITION_MASK) &&
 644                (c++ < PWRDM_TRANSITION_BAILOUT))
 645                 udelay(1);
 646
 647         if (c > PWRDM_TRANSITION_BAILOUT) {
 648                 pr_err("powerdomain: %s: waited too long to complete transition\n",
 649                        pwrdm->name);
 650                 return -EAGAIN;
 651         }
 652
 653         pr_debug("powerdomain: completed transition in %d loops\n", c);
 654
 655         return 0;
 656 }
 657
 658 static int omap4_check_vcvp(void)
 659 {
 660         if (prm_features & PRM_HAS_VOLTAGE)
 661                 return 1;
 662
 663         return 0;
 664 }
 665
 666 struct pwrdm_ops omap4_pwrdm_operations = {
 667         .pwrdm_set_next_pwrst   = omap4_pwrdm_set_next_pwrst,
 668         .pwrdm_read_next_pwrst  = omap4_pwrdm_read_next_pwrst,
 669         .pwrdm_read_pwrst       = omap4_pwrdm_read_pwrst,
 670         .pwrdm_read_prev_pwrst  = omap4_pwrdm_read_prev_pwrst,
 671         .pwrdm_set_lowpwrstchange       = omap4_pwrdm_set_lowpwrstchange,
 672         .pwrdm_clear_all_prev_pwrst     = omap4_pwrdm_clear_all_prev_pwrst,
 673         .pwrdm_set_logic_retst  = omap4_pwrdm_set_logic_retst,
 674         .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
 675         .pwrdm_read_prev_logic_pwrst    = omap4_pwrdm_read_prev_logic_pwrst,
 676         .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
 677         .pwrdm_read_mem_pwrst   = omap4_pwrdm_read_mem_pwrst,
 678         .pwrdm_read_mem_retst   = omap4_pwrdm_read_mem_retst,
 679         .pwrdm_read_prev_mem_pwrst      = omap4_pwrdm_read_prev_mem_pwrst,
 680         .pwrdm_set_mem_onst     = omap4_pwrdm_set_mem_onst,
 681         .pwrdm_set_mem_retst    = omap4_pwrdm_set_mem_retst,
 682         .pwrdm_wait_transition  = omap4_pwrdm_wait_transition,
 683         .pwrdm_has_voltdm       = omap4_check_vcvp,
 684 };
 685
 686 static int omap44xx_prm_late_init(void);
 687
 688 /*
 689  * XXX document
 690  */
 691 static struct prm_ll_data omap44xx_prm_ll_data = {
 692         .read_reset_sources = &omap44xx_prm_read_reset_sources,
 693         .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
 694         .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
 695         .late_init = &omap44xx_prm_late_init,
 696         .assert_hardreset       = omap4_prminst_assert_hardreset,
 697         .deassert_hardreset     = omap4_prminst_deassert_hardreset,
 698         .is_hardreset_asserted  = omap4_prminst_is_hardreset_asserted,
 699 };
 700
 701 int __init omap44xx_prm_init(void)
 702 {
 703         if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx())
 704                 prm_features |= PRM_HAS_IO_WAKEUP;
 705
 706         if (!soc_is_dra7xx())
 707                 prm_features |= PRM_HAS_VOLTAGE;
 708
 709         return prm_register(&omap44xx_prm_ll_data);
 710 }
 711
 712 static struct of_device_id omap_prm_dt_match_table[] = {
 713         { .compatible = "ti,omap4-prm" },
 714         { .compatible = "ti,omap5-prm" },
 715         { .compatible = "ti,dra7-prm" },
 716         { }
 717 };
 718
 719 static int omap44xx_prm_late_init(void)
 720 {
 721         struct device_node *np;
 722         int irq_num;
 723
 724         if (!(prm_features & PRM_HAS_IO_WAKEUP))
 725                 return 0;
 726
 727         /* OMAP4+ is DT only now */
 728         if (!of_have_populated_dt())
 729                 return 0;
 730
 731         np = of_find_matching_node(NULL, omap_prm_dt_match_table);
 732
 733         if (!np) {
 734                 /* Default loaded up with OMAP4 values */
 735                 if (!cpu_is_omap44xx())
 736                         return 0;
 737         } else {
 738                 irq_num = of_irq_get(np, 0);
 739                 /*
 740                  * Already have OMAP4 IRQ num. For all other platforms, we need
 741                  * IRQ numbers from DT
 742                  */
 743                 if (irq_num < 0 && !cpu_is_omap44xx()) {
 744                         if (irq_num == -EPROBE_DEFER)
 745                                 return irq_num;
 746
 747                         /* Have nothing to do */
 748                         return 0;
 749                 }
 750
 751                 /* Once OMAP4 DT is filled as well */
 752                 if (irq_num >= 0)
 753                         omap4_prcm_irq_setup.irq = irq_num;
 754         }
 755
 756         omap44xx_prm_enable_io_wakeup();
 757
 758         return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
 759 }
 760
 761 static void __exit omap44xx_prm_exit(void)
 762 {
 763         prm_unregister(&omap44xx_prm_ll_data);
 764 }
 765 __exitcall(omap44xx_prm_exit);