2 * linux/arch/arm/mach-pxa/clock-pxa3xx.c
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/init.h>
13 #include <mach/pxa3xx-regs.h>
17 /* Crystal clock: 13MHz */
18 #define BASE_CLK 13000000
20 /* Ring Oscillator Clock: 60MHz */
21 #define RO_CLK 60000000
23 #define ACCR_D0CS (1 << 26)
24 #define ACCR_PCCE (1 << 11)
26 /* crystal frequency to static memory controller multiplier (SMCFS) */
27 static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
29 /* crystal frequency to HSIO bus frequency multiplier (HSS) */
30 static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
33 * Get the clock frequency as reflected by CCSR and the turbo flag.
34 * We assume these values have been applied via a fcs.
35 * If info is not 0 we also display the current settings.
37 unsigned int pxa3xx_get_clk_frequency_khz(int info)
39 unsigned long acsr, xclkcfg;
40 unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
42 /* Read XCLKCFG register turbo bit */
43 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
49 xn = (acsr >> 8) & 0x7;
50 hss = (acsr >> 14) & 0x3;
55 ro = acsr & ACCR_D0CS;
57 CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
58 HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
61 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
62 RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
64 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
65 XL / 1000000, (XL % 1000000) / 10000, xl);
66 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
67 XN / 1000000, (XN % 1000000) / 10000, xn,
69 pr_info("HSIO bus clock: %d.%02dMHz\n",
70 HSS / 1000000, (HSS % 1000000) / 10000);
77 * Return the current AC97 clock frequency.
79 static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
81 unsigned long rate = 312000000;
82 unsigned long ac97_div;
86 /* This may loose precision for some rates but won't for the
89 rate /= (ac97_div >> 12) & 0x7fff;
90 rate *= (ac97_div & 0xfff);
96 * Return the current HSIO bus clock frequency
98 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
101 unsigned int hss, hsio_clk;
105 hss = (acsr >> 14) & 0x3;
106 hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
111 void clk_pxa3xx_cken_enable(struct clk *clk)
113 unsigned long mask = 1ul << (clk->cken & 0x1f);
121 void clk_pxa3xx_cken_disable(struct clk *clk)
123 unsigned long mask = 1ul << (clk->cken & 0x1f);
131 const struct clkops clk_pxa3xx_cken_ops = {
132 .enable = clk_pxa3xx_cken_enable,
133 .disable = clk_pxa3xx_cken_disable,
136 const struct clkops clk_pxa3xx_hsio_ops = {
137 .enable = clk_pxa3xx_cken_enable,
138 .disable = clk_pxa3xx_cken_disable,
139 .getrate = clk_pxa3xx_hsio_getrate,
142 const struct clkops clk_pxa3xx_ac97_ops = {
143 .enable = clk_pxa3xx_cken_enable,
144 .disable = clk_pxa3xx_cken_disable,
145 .getrate = clk_pxa3xx_ac97_getrate,
148 static void clk_pout_enable(struct clk *clk)
153 static void clk_pout_disable(struct clk *clk)
158 const struct clkops clk_pxa3xx_pout_ops = {
159 .enable = clk_pout_enable,
160 .disable = clk_pout_disable,
164 static uint32_t cken[2];
165 static uint32_t accr;
167 static int pxa3xx_clock_suspend(struct sys_device *d, pm_message_t state)
175 static int pxa3xx_clock_resume(struct sys_device *d)
183 #define pxa3xx_clock_suspend NULL
184 #define pxa3xx_clock_resume NULL
187 struct sysdev_class pxa3xx_clock_sysclass = {
188 .name = "pxa3xx-clock",
189 .suspend = pxa3xx_clock_suspend,
190 .resume = pxa3xx_clock_resume,
193 static int __init pxa3xx_clock_init(void)
196 return sysdev_class_register(&pxa3xx_clock_sysclass);
199 postcore_initcall(pxa3xx_clock_init);